With Charge Trapping Gate Insulator, E.g., Mnos Transistor (epo) Patents (Class 257/E21.423)
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Publication number: 20100117137Abstract: Each of memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate; a charge storage layer formed to surround a side surface of the columnar portions; and a first conductive layer formed to surround the charge storage layer. Each of the select transistors is provided with a second semiconductor layer extending upwardly from an upper surface of the columnar portions; a gate insulating layer formed to surround a side surface of the second semiconductor layer; and a second conductive layer formed to surround the gate insulating layer. An effective impurity concentration of the second semiconductor layer is less than or equal to an effective impurity concentration of the first semiconductor layer.Type: ApplicationFiled: September 15, 2009Publication date: May 13, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki FUKUZUMI, Masaru KITO, Ryota KATSUMATA, Masaru KIDOH, Hiroyasu TANAKA, Yosuke KOMORI, Megumi ISHIDUKI, Hideaki AOCHI
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Publication number: 20100117134Abstract: A dielectric film is formed on a silicon substrate made of single crystal silicon, an opening is formed in the dielectric film, an amorphous silicon film is formed on the dielectric film, the amorphous silicon film being in contact with the silicon substrate through the opening, solid-phase epitaxial growth of this amorphous silicon film is caused to start at the silicon substrate, and thereafter patterning is performed. Thereby, a seed layer made of the single crystal silicon is formed in part of a region deviated from immediately above the opening. Next, the amorphous silicon film is deposited so as to cover the seed layer, forming a single crystal silicon film by solid-phase epitaxial growth of the amorphous silicon film starting at the seed layer. The silicon pillar is formed by patterning the single crystal silicon film.Type: ApplicationFiled: September 18, 2009Publication date: May 13, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Kiyohito NISHIHARA
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Publication number: 20100112772Abstract: A method of fabricating a semiconductor device includes: forming a first polysilicon layer having a first thickness in a peripheral circuit region formed on a substrate; forming a stack structure comprising a first tunneling insulating layer, a charge trap layer, and a blocking insulating layer in a memory cell region formed on the substrate; forming a second polysilicon layer having a second thickness that is less than the first thickness on the blocking insulating layer; and forming gate electrodes by siliciding the first and second polysilicon layers.Type: ApplicationFiled: July 27, 2009Publication date: May 6, 2010Applicant: Samsung Electronics Co., Ltd.Inventors: Eun-ji Jung, Sang-woo Lee, Jeong-gil Lee, Gil-heyun Choi, Chang-won Lee, Byung-hee Kim, Jin-ho Park
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Publication number: 20100109070Abstract: A device and method employing a polyoxide-based charge trapping component. A charge trapping component is patterned by etching a layered stack that includes a tunneling layer positioned on a substrate, a charge trapping layer positioned on the tunneling layer, and an amorphous silicon layer positioned on the charge trapping layer. An oxidation process grows a gate oxide layer from the substrate and converts the amorphous silicon layer into a polyoxide layer.Type: ApplicationFiled: November 6, 2008Publication date: May 6, 2010Applicant: Spansion LLCInventor: Masahiko Higashi
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Publication number: 20100105198Abstract: A method of forming a gate electrode of a semiconductor device includes forming a first polysilicon layer in a peripheral circuit region of a substrate, forming a barrier layer on the first polysilicon layer, the barrier layer providing an ohmic contact, forming a stack structure including a tunneling insulation layer, an electric charge storing layer, and a blocking insulation layer in a memory cell region of the substrate, forming a second polysilicon layer on the barrier layer and the blocking insulation layer, and siliciding the second polysilicon layer and forming a silicide gate electrode.Type: ApplicationFiled: July 22, 2009Publication date: April 29, 2010Inventors: Sang-woo Lee, Gil-heyun Choi, Chang-won Lee, Byung-hee Kim, Jin-ho Park, Eun-ji Jung, Jeong-gil Lee
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Publication number: 20100102377Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, a plurality of charge storage layers formed on the first insulating layer, a plurality of element isolation insulating films formed between the charge storage layers respectively, a second insulating layer formed on the charge storage layers and the element isolation insulating films, the second insulating layer including a stacked structure of a first silicon nitride film, a first silicon oxide film, an intermediate insulating film having a relative dielectric constant of not less than 7 and a second silicon oxide film, and a control electrode formed on the second insulating layer. The first silicon nitride film has a nitrogen concentration of not less than 21×1015 atoms/cm2.Type: ApplicationFiled: May 18, 2009Publication date: April 29, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Hirofumi IIKAWA, Masayuki Tanaka
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Patent number: 7704865Abstract: Methods of forming charge-trapping dielectric layer structures in semiconductor memory devices which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate; (c) forming two or more source/drain regions in the substrate below the oxide layer; (d) re-oxidizing the oxide layer; (e) forming a charge-trapping dielectric layer on the oxide layer; and (f) forming an insulating layer on the charge-trapping dielectric layer; as well as methods which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate in a dry atmosphere; (c) forming two or more source/drain regions in the substrate below the oxide layer; (d) forming a charge-trapping dielectric layer on the oxide layer; (e) forming an insulating layer on the charge-trapping dielectric layer; and (f) annealing the insulating layer in an atmosphere having a hydrogen content of less than about 0.01% are described.Type: GrantFiled: August 23, 2005Date of Patent: April 27, 2010Assignee: MACRONIX International Co., Ltd.Inventors: Yen-Hao Shih, Shih-Chin Lee, Jung-Yu Hsieh, Erh-Kun Lai, Kuang Yeu Hsieh
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Patent number: 7705384Abstract: A non-volatile storage element 100 has a silicon substrate 102, a first memory region 106a composed of a first lower silicon oxide film 108a, a first silicon nitride film 110a, and a first upper layer silicon oxide film 112a provided in this order, a second memory region 106b composed of a second lower layer silicon oxide film 108b, a second silicon nitride film 110b, and a second upper layer silicon oxide film 112b provided in this order, and a first control gate 114 and a second control gate 116 arranged on the first memory region 106a and the second control gate 116, respectively, on the silicon substrate 102. The silicon nitride film 110 is provided so as to be horizontal in a direction within a substrate plane.Type: GrantFiled: March 30, 2006Date of Patent: April 27, 2010Assignee: NEC Electronics CorporationInventor: Akira Yoshino
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Publication number: 20100096688Abstract: A flash memory device and method of forming a flash memory device are provided. The flash memory device includes a silicon nitride layer having a compositional gradient in which the ratio of silicon to nitrogen varies through the thickness of the layer. The silicon nitride layer having a compositional gradient of silicon and nitrogen provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device.Type: ApplicationFiled: October 22, 2008Publication date: April 22, 2010Inventors: Mihaela Balseanu, Vladimir Zubkov, Li-Qun Xia, Atif Noori, Reza Arghavani, Derek R. Witty, Amir Al-Bayati
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Publication number: 20100090212Abstract: A memory cell comprising a metal-insulator-semiconductor (MIS) structure is disclosed using a homogeneous carrier trapping layer interposed between a semiconductor layer and the gate electrode of a transistor structure so that the operation voltage is reduced and the manufacturing is simplified with lowered cost. The MIS structure comprises: a gate electrode; a semiconductor layer; and a homogeneous carrier trapping layer interposed between the gate electrode and the semiconductor layer; wherein the homogeneous carrier trapping layer comprises novolac.Type: ApplicationFiled: December 18, 2009Publication date: April 15, 2010Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventor: Chia-Chieh Chang
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Publication number: 20100090257Abstract: A channel is formed at a recessed portion or a projecting portion of a substrate, and a gate insulating film is formed so as to have first to third insulating regions along the channel. Each of the gate insulating films of the first and third insulating regions has a first gate insulating film containing no electric charge trap formed on a plane different from a principal surface of the substrate, an electric charge accumulating film containing an electric charge trap, and a second gate insulating film containing no electric charge trap. The gate insulating film of the second insulating region at the middle is formed on a plane parallel to the principal surface of the substrate and is composed of only a third gate insulating film containing no electric charge trap.Type: ApplicationFiled: October 23, 2007Publication date: April 15, 2010Inventors: Masayuki Terai, Shinji Fujieda, Akio Toda
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Publication number: 20100093142Abstract: A method of fabricating a device is described. A substrate having at least two isolation structures is provided. A first oxide layer and a first conductive layer are sequentially formed on the substrate between the isolation structures. A first nitridation process is performed to form a first nitride layer on the surface of the first conductive layer and a first oxynitride layer on the surface of the isolation structures. A second oxide layer is formed on the first nitride layer and first oxynitride layer. A densification process is performed to oxidize the first oxynitride layer on the surface of the isolation structures. A second nitride layer and a third oxide layer are sequentially formed on the second oxide layer. A second nitridation process is performed to form a third nitride layer on the surface of the third oxide layer. A second conductive layer is formed on the third nitride layer.Type: ApplicationFiled: October 9, 2008Publication date: April 15, 2010Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Ching-Yuan Ho, Hirotake Fujita, Po-Jui Chiang
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Patent number: 7696563Abstract: A non-volatile memory device includes a tunnel insulating layer pattern on a channel region of a substrate, a charge trapping layer pattern on the tunnel insulating layer pattern, a blocking layer pattern on the charge trapping layer pattern, and a gate electrode including a conductive layer pattern on the blocking layer pattern and a barrier layer pattern on the conductive layer pattern. The conductive layer pattern includes a metal.Type: GrantFiled: September 6, 2007Date of Patent: April 13, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Sug-Hun Hong, Myoung-Bum Lee, Gab-Jin Nam
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Publication number: 20100084719Abstract: The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a metal gate layer on the high k dielectric material layer; forming a top gate layer on the metal gate layer; patterning the top gate layer, the metal gate layer and the high k dielectric material layer to form a gate stack; performing an etching process to selectively recess the metal gate layer; and forming a gate spacer on sidewalls of the gate stack.Type: ApplicationFiled: September 17, 2009Publication date: April 8, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuri MASUOKA, Shyh-Horng YANG, Peng-Soon LIM
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Publication number: 20100065899Abstract: A semiconductor device may include first and second auxiliary gate electrodes and a semiconductor layer crossing the first and second auxiliary gate electrodes. A primary gate electrode may be provided on the semiconductor layer so that the semiconductor layer is between the primary gate electrode and the first and second auxiliary gate electrodes. Moreover, the first and second auxiliary gate electrodes may be configured to induce respective first and second field effect type source/drain regions in the semiconductor layer. Related methods are also discussed.Type: ApplicationFiled: August 20, 2009Publication date: March 18, 2010Inventors: Suk-pil Kim, Yoon-dong Park, Jae-young Choi, June-mo Koo, Byung-hee Hong
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Publication number: 20100067310Abstract: A MOS transistor comprising a conductive extension of its source region, insulated from its substrate, and partially extending under its channel.Type: ApplicationFiled: February 14, 2007Publication date: March 18, 2010Applicant: STMicroelectronics Crolles 1 SASInventors: Pascale Mazoyer, Germain Bossu
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Patent number: 7678654Abstract: A memory cell array includes a number of memory cells, each of the memory cells including a source and a drain region defined by corresponding bitlines within a semiconductor substrate. Each of the bitlines has a doped semiconductor region as well as a conductive region in direct electrical contact with the doped semiconductor region.Type: GrantFiled: June 30, 2006Date of Patent: March 16, 2010Assignee: Qimonda AGInventors: Christoph Kleint, Clemens Fitz, Ulrike Bewersdorff-Sarlette, Christoph Ludwig, David Pritchard, Torsten Müller, Hocine Boubekeur
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Patent number: 7679125Abstract: A method of making a semiconductor device includes providing a first wafer and providing a second wafer having a first side and a second side, the second wafer including a semiconductor substrate, a storage layer, and a layer of gate material. The storage layer may be located between the semiconductor structure and the layer of the gate material and the storage layer may be located closer to the first side of the second wafer than the semiconductor structure. The method further includes boding the first side of the second wafer to the first wafer. The method further includes removing a first portion of the semiconductor structure to leave a layer of the semiconductor structure after the bonding. The method further includes forming a transistor having a channel region, wherein at least a portion of the channel region is formed from the layer of the semiconductor structure.Type: GrantFiled: December 14, 2005Date of Patent: March 16, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Craig T. Swift, Gowrishankar L. Chindalore, Thuy B. Dao, Michael A. Sadd
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Publication number: 20100059812Abstract: Disclosed are a flash memory device and a method for manufacturing the same. The flash memory device includes a semiconductor substrate having a unit cell defined by an isolation layer, a gate formed over the semiconductor substrate, LDD areas formed at shallow areas of the semiconductor substrate at both sides of the gate, a source and a drain formed at deep areas of the semiconductor substrate while making contact with the LDD areas, and spacers formed at sidewalls of the gate. The spacer includes a first oxide layer pattern, a nitride layer pattern, and a second oxide layer pattern, and the semiconductor substrate includes silicon, so that a silicon-oxide-nitride-oxide-silicon structure for the flash memory device is formed by the silicon of the semiconductor substrate and the spacer at the drain side of the gate.Type: ApplicationFiled: August 24, 2009Publication date: March 11, 2010Inventor: Jin Ha Park
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Publication number: 20100062595Abstract: A nonvolatile memory device and a method of forming the nonvolatile memory device, the method including forming a tunnel insulating layer on a substrate, wherein forming the tunnel insulating layer includes forming a multi-element insulating layer by a process including sequentially supplying a first element source, a second element source, and a third element source to the substrate, forming a charge storage layer on the tunnel insulating layer, forming a blocking insulating layer on the charge storage layer, and forming a control gate electrode on the blocking insulating layer.Type: ApplicationFiled: July 21, 2009Publication date: March 11, 2010Inventors: Juwan Lim, Sungkweon Baek, Kwangmin Park, Seungjae Baik, Kihyun Hwang
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Publication number: 20100059809Abstract: A method of fabricating a non-volatile memory is provided. First, a bottom oxide layer is formed on a substrate. Thereafter, a silicon-rich nitride layer is formed on the bottom oxide layer by using NH3 and SiH2Cl2 or SiH4, wherein the thickness of the silicon-rich nitride layer is less than about 40 ?, and the gas flow ratio of NH3 to SiH2Cl2 or SiH4 is about 0.2-0.5. Afterwards, a top oxide layer is formed on the silicon-rich nitride layer. Further, a gate is formed on the top oxide layer. Two doped regions are then formed in the substrate beside the gate.Type: ApplicationFiled: November 11, 2008Publication date: March 11, 2010Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chi-Pin Lu, Jung-Yu Hsieh, Hsing-Ju Lin
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Publication number: 20100059813Abstract: A gate electrode of a select gate transistor includes a gate insulating film that is formed on a semiconductor substrate, a lower gate electrode that is formed on the gate insulating film and that has a tapered portion in which a side surface on a side of a gate electrode of a memory cell transistor is in a tapered shape, a first oxide film, a silicon nitride film, a second oxide film, and a conductive film that are sequentially formed on the tapered portion, and an upper gate electrode that is connected to the conductive film and the lower gate electrode.Type: ApplicationFiled: June 9, 2009Publication date: March 11, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Motoki SUGI
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Publication number: 20100052036Abstract: A semiconductor device disposed on a substrate is provided. The semiconductor device includes two isolation structures, a first conductive layer, a charge trapping layer, a second conductive layer and a gate dielectric layer. The two isolation structures are disposed in the substrate to define an active area. The second conductive layer across the two isolation structures is disposed on the substrate. The first conductive layer is disposed between the two isolation structures and between the second conductive layer and the substrate. The second conductive layer electrically connects with the first conductive layer. The charge trapping layer is disposed on the substrate. The gate dielectric layer is disposed between the first conductive layer and the substrate. An interface between the two isolation structures and the first conductive layer is covered by the charge trapping layer to restrain the kink effect.Type: ApplicationFiled: August 20, 2009Publication date: March 4, 2010Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Cheng-Hong Lee, Chih-Ming Chao, Hann-Ping Hwang, Che-Huai Hung
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Patent number: 7670963Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes first forming a tunnel dielectric layer on a substrate in a first process chamber of a single-wafer cluster tool. A charge-trapping layer is then formed on the tunnel dielectric layer in a second process chamber of the single-wafer cluster tool. A top dielectric layer is then formed on the charge-trapping layer in the second or in a third process chamber of the single-wafer cluster tool.Type: GrantFiled: September 26, 2007Date of Patent: March 2, 2010Assignee: Cypress Semiconductor CorportionInventors: Krishnaswamy Ramkumar, Sagy Levy
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Patent number: 7671405Abstract: A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising performing front end processing, performing a first bitline implant, or pocket implants, or both into the first bitline spacings to establish buried first bitlines within the substrate, depositing a layer of the spacer material over the charge trapping dielectric and the polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the polysilicon layer features to define second bitline spacings between adjacent memory cells, performing a deep arsenic implant into the second bitline spacings to establish a second bitline within the structure that is deeper than the first bit line, removing the sidewall spacers and performing back end processing.Type: GrantFiled: December 26, 2006Date of Patent: March 2, 2010Assignee: Spansion LLCInventors: Timothy Thurgate, Yi He, Ming-Sang Kwan, Zhizheng Liu, Xuguang Wang
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Publication number: 20100048012Abstract: Provided is a method for fabricating a nonvolatile memory device capable of improving charge retention characteristics. The method for fabricating a nonvolatile memory device includes forming a charge trapping layer with a memory region and a charge blocking region on a semiconductor substrate, and trapping charges in the charge blocking region of the charge trapping layer.Type: ApplicationFiled: August 4, 2009Publication date: February 25, 2010Inventors: Juyul Lee, Seungjae Baik, Kihyun Hwang, Siyoung Choi
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Publication number: 20100041206Abstract: According to a method of manufacturing a MONOS nonvolatile semiconductor memory device, a tunnel insulating film, a charge storage layer, a block insulating film containing a metal oxide and a control gate electrode are stacked on a semiconductor substrate. Heat treatment is carried out in an atmosphere containing an oxidizing gas after the tunnel insulating film, the charge storage layer and the block insulating film are stacked on the semiconductor substrate. Thereafter, the control gate electrode is formed on the block insulating film.Type: ApplicationFiled: August 13, 2009Publication date: February 18, 2010Inventors: Ryota Fujitsuka, Katsuyuki Sekine, Yoshio Ozawa
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Publication number: 20100029052Abstract: A method includes forming a silicon nitride layer and patterning it to form a first opening and a second opening separated by a first portion of silicon nitride. Gate material is deposited in the first and second openings to form first and second select gate structures in the first and second openings. Second and third portions of silicon nitride layer are removed adjacent to the first and second gate structures, respectively. A charge storage layer is formed over the semiconductor device after removing the second and third portions. First and second sidewall spacers of gate material are formed on the charge storage layer and adjacent to the first and second gate structures. The charge storage layer is etched using the first and second sidewall spacers as masks. The first portion is removed. A drain region is formed in the semiconductor layer between the first and second gate structures.Type: ApplicationFiled: July 29, 2008Publication date: February 4, 2010Inventors: Sung-Taeg Kang, Jane A. Yater
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Publication number: 20100019312Abstract: A semiconductor device includes a semiconductor region, a tunnel insulating film formed on a surface of the semiconductor region, a charge-storage insulating film formed on a surface of the tunnel insulating film and containing silicon and nitrogen, a block insulating film formed on a surface of the charge-storage insulating film, and a control gate electrode formed on a surface of the block insulating film, wherein the tunnel insulating film has a first insulating film formed on the surface of the semiconductor region and containing silicon and oxygen, a second insulating film formed on a surface of the first insulating film, and a third insulating film formed on a surface of the second insulating film and containing silicon and oxygen, and a charge trap state in the second insulating film has a lower density than that in the charge-storage insulating film.Type: ApplicationFiled: July 28, 2009Publication date: January 28, 2010Inventors: Katsuyuki SEKINE, Akiko Sekihara, Kensuke Takano, Yoshio Ozawa
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Publication number: 20100013001Abstract: A method for manufacturing a non-volatile memory and a structure thereof are provided. The manufacturing method comprises the following steps. Firstly, a substrate is provided. Next, a semiconductor layer is formed on the substrate. Then, a Si-rich dielectric layer is formed on the semiconductor layer. After that, a plurality of silicon nanocrystals is formed in the Si-rich dielectric layer by a laser annealing process to form a charge-storing dielectric layer. Last, a gate electrode is formed on the charge-storing dielectric layer.Type: ApplicationFiled: July 10, 2009Publication date: January 21, 2010Applicant: AU OPTRONICS CORP.Inventors: An-Thung CHO, Chia-Tien PENG, Chih-Wei CHAO, Wan-Yi LIU, Chia-Kai CHEN, Chun-Hsiun CHEN, Wei-Ming HUANG
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Publication number: 20100015773Abstract: A new SONOS memory device is provided, in which a conventional planar surface of multi-dielectric layers (ONO layers) is instead formed with a curved surface such as a cylindrical shape, and included is a method for fabricating the same. A radius of curvature of the upper surface of a blocking oxide can be designed to be larger than that of the lower surface of a tunneling oxide, which restrains electrons from passing through the blocking oxide by back-tunneling on erasing. As a result, a SONOS memory device shows an improvement in erasing speed.Type: ApplicationFiled: June 10, 2009Publication date: January 21, 2010Applicants: SEOUL NATIONAL UNIVERSITY INDUSTRY FOUNDATION, SAMSUNG ELECTRONICS CO., LTD.Inventors: Byung Gook Park, Jung Hoon Lee
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Publication number: 20100012999Abstract: Provided are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device comprises two gate electrodes on a semiconductor substrate between device isolation regions, a common source region on the semiconductor substrate between the two gate electrodes, a drain region on the semiconductor substrate at outer sides of the two gate electrodes, a spacer on the drain region and on outer sidewalls of the two gate electrodes, a third oxide layer on inner sidewalls of the two gate electrodes, and a silicide layer on the common source region.Type: ApplicationFiled: June 29, 2009Publication date: January 21, 2010Inventor: Ji Hwan Park
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Patent number: 7648881Abstract: A non-volatile memory device comprises a cell region defined at a substrate and a plurality of device isolation layers formed in the cell region to define a plurality of active regions. A charge storage insulator covers substantially the entire top surface of the cell region. A plurality of gate lines are formed on the charge storage insulator that cross over the device isolation layers. Conductive patterns are disposed between predetermined gate lines that penetrate the charge storage insulator to electrically connect with the active regions. According to the method of fabricating the device, a plurality of device isolation layers are formed in the substrate and then a charge storage insulator is formed on an entire surface of the substrate and the device isolation layers. A plurality of parallel gate lines that cross over the device isolation layers are formed on the charge storage insulator and then conductive patterns are formed between predetermined gate lines.Type: GrantFiled: July 6, 2006Date of Patent: January 19, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Chang-Hyun Lee
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Patent number: 7648882Abstract: A method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) flash memory includes preparing a silicon substrate including a silicon oxide-silicon nitride-silicon oxide (ONO) layer, a first polysilicon layer and a first etch stop layer in sequence; etching the first etch stop layer along a direction of bit line; selectively etching the first polysilicon layer with the first etch stop layer as a mask, till the silicon oxide-silicon nitride-silicon oxide (ONO) layer is exposed, the etched first polysilicon layer having an inverse trapezia section along a direction of word line; and filling a dielectic layer between portions of the first polysilicon layer, the dielectric layer having a trapezia section along the direction of word line. After the above steps, it becomes easier to remove the portion of the first polysilicon layer on a sidewall of the dielectric layer by vertical etching.Type: GrantFiled: August 19, 2007Date of Patent: January 19, 2010Assignee: Semiconductors Manufacturing International (Shanghai) CorporationInventors: Haitao Jiang, Xinsheng Zhong, Jiangpeng Xue, Gangning Wang
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Publication number: 20100006914Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate that includes a trench, a charge storage layer that is formed inside of the trench, a first gate that is formed above a side surface and a bottom surface of the trench, a second gate that is formed beside the first gate, and that is formed above the charge storage layer, a first diffusion region that is formed on the semiconductor substrate inside of the trench, and a second diffusion region that is formed on the semiconductor substrate outside of the trench.Type: ApplicationFiled: July 8, 2009Publication date: January 14, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: Kenichiro Nakagawa
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Patent number: 7646056Abstract: In a gate structure of a non-volatile memory device is formed, a tunnel insulating layer and a charge trapping layer are formed on a substrate. A composite dielectric layer is formed on the charge trapping layer and has a laminate structure in which first material layers including aluminum oxide and second material layers including hafnium oxide or zirconium oxide are alternately stacked. A conductive layer is formed on the composite dielectric layer and then a gate structure is formed by patterning the conductive layer, the composite dielectric layer, the charge trapping layer, and the tunnel insulating layer.Type: GrantFiled: March 15, 2006Date of Patent: January 12, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Han-Mei Choi, Kyoung-Ryul Yoon, Seung-Hwan Lee, Ki-Yeon Park, Young-Sun Kim
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Publication number: 20100001338Abstract: A non-volatile semiconductor memory device includes a semiconductor substrate, a charge-storage layer that is formed above the semiconductor substrate, a first gate that is formed above the charge-storage layer, and that includes a first surface and a second surface, a second gate that is formed beside the first surface of the first gate, an insulating layer that is formed above the second surface of the first gate, a diffusion region that is formed on the semiconductor substrate at a position corresponding to the second surface of the first gate, and a silicide layer that is formed above the insulating layer and the diffusion region.Type: ApplicationFiled: July 1, 2009Publication date: January 7, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: Kenichiro Nakagawa
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Publication number: 20100001333Abstract: The present invention provides semiconductor device and a fabrication method therefor. The semiconductor device includes trenches (11) formed in a semiconductor substrate (10), first ONO films (18) provided on both side surfaces of the trenches, and first word lines (22) provided on side surfaces of the first ONO films (18) and running in a length direction of the trenches (11). According to the present invention, it is possible to provide a semiconductor deice and a fabrication method therefor, in which higher memory capacity can be achieved.Type: ApplicationFiled: August 18, 2009Publication date: January 7, 2010Inventors: Masaya Hosaka, Masatomi Okanishi
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Method of forming a flash NAND memory cell array with charge storage elements positioned in trenches
Patent number: 7642160Abstract: NAND arrays of memory cells are described, as well as methods of forming and using them. Memory cell charge storage devices, such as conductive floating gates, are oriented vertically in trenches, with control gates positioned both in the trenches between charge storage elements and over a horizontal surface between the trenches. Individual charge storage devices are therefore field coupled with two control gates, one on either side.Type: GrantFiled: December 21, 2006Date of Patent: January 5, 2010Assignee: SanDisk CorporationInventor: Nima Mokhlesi -
Patent number: 7642163Abstract: An electronic device can include a nonvolatile memory cell having DSEs within a dielectric layer. In one aspect, a process of forming the electronic device can include implanting and nucleating a first charge-storage material to form DSEs. The process can also include implanting a second charge-storage material and growing the DSEs such that the DSEs include the first and second charge-storage material. In another aspect, a process of forming the electronic device can include forming a semiconductor layer over a dielectric layer, implanting a charge-storage material, and annealing the dielectric layer. After annealing, substantially none of the charge-storage material remains within a denuded zone within the dielectric layer. In a third aspect, within a dielectric layer, a first set of DSEs can be spaced apart from a second set of DSEs, wherein substantially no DSEs lie between the first set of DSEs and the second set of DSEs.Type: GrantFiled: March 30, 2007Date of Patent: January 5, 2010Assignee: Freescale Semiconductor, IncInventors: Rajesh A. Rao, Tushar P. Merchant, Ramachandran Muralidhar, Gowrishankar Chindalore, David Sing, Jane Yater
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Publication number: 20090321813Abstract: A nonvolatile semiconductor memory device includes: a stacked body with a plurality of insulating films and electrode films alternately stacked therein, through which a through hole extending in the stacking direction is formed; a semiconductor pillar buried inside the through hole; and a charge storage layer located on both sides of each of the electrode films in the stacking direction and insulated from the electrode film and the semiconductor pillar.Type: ApplicationFiled: March 17, 2009Publication date: December 31, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masaru KIDOH, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Hideaki Aochi
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Publication number: 20090325354Abstract: The present invention relates to a semiconductor device that includes a semiconductor substrate (10) having source/drain diffusion regions (14) formed therein and control gates (20) formed thereon, with grooves (18) being formed on the surface of the semiconductor substrate (10) and being located below the control gates (20) and between the source/drain diffusion regions (14). The grooves (18) are separated from the source/drain diffusion regions (14), thereby increasing the effective channel length to maintain a constant channel length for charge accumulation while enabling the manufacture of smaller memory cells. The present invention also provides a method of manufacturing the semiconductor device.Type: ApplicationFiled: July 14, 2009Publication date: December 31, 2009Inventor: Masahiko Higashi
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Publication number: 20090315093Abstract: Methods of forming metal carbide films are provided. In some embodiments, a substrate is exposed to alternating pulses of a transition metal species and an aluminum hydrocarbon compound, such as TMA, DMAH, or TEA. The aluminum hydrocarbon compound is selected to achieve the desired properties of the metal carbide film, such as aluminum concentration, resistivity, adhesion and oxidation resistance. In some embodiments, the methods are used to form a metal carbide layer that determines the work function of a control gate in a flash memory.Type: ApplicationFiled: April 15, 2009Publication date: December 24, 2009Applicant: ASM AMERICA, INC.Inventors: Dong LI, Steven MARCUS, Suvi P. HAUKKA, Wei-Min LI
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Publication number: 20090315100Abstract: Disclosed is a method of manufacturing a semiconductor device. The method includes forming an oxide-nitride-oxide (ONO) layer over a semiconductor substrate, and forming a recess over the semiconductor substrate by etching the ONO layer, forming a vertical structure pattern being higher than the ONO layer over the recess, sequentially forming a spacer oxide film and a first gate poly over the side wall of the vertical structure pattern, and forming a nitride film spacer at a partial region of the side wall of the first gate poly, removing the nitride film spacer, and forming a second gate poly in a spacer shape over the side wall of the first gate poly, and forming a first split gate and a second split gate, symmetrically divided from each other, by removing the vertical structure pattern.Type: ApplicationFiled: June 4, 2009Publication date: December 24, 2009Inventor: Hee-Don Jeong
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Publication number: 20090315098Abstract: A method for manufacturing a semiconductor device is disclosed. The method includes forming a shallow trench isolation (STI) region extending in a first direction on a semiconductor substrate, forming a mask layer extending in a second direction that intersects with the first direction on the semiconductor substrate and forming a trench on the semiconductor substrate by using the STI region and the mask layer as masks. In addition, the method includes forming a charge storage layer so as to cover the trench and forming a conductive layer on side surfaces of the trench and the mask layer. Word lines are formed from the conductive layer on side surfaces of the trench that oppose in the first direction by etching. The word lines are separated from each other and extend in the second direction.Type: ApplicationFiled: December 17, 2008Publication date: December 24, 2009Inventors: Fumiaki Toyama, Fumihiko Inoue
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Publication number: 20090316484Abstract: Disclosed is a semiconductor storage device comprising a semiconductor substrate, a first and a second impurity diffusion layer formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a first gate electrode formed on the semiconductor substrate via the gate insulating film. The gate insulating film has a nitrogen-containing silicon oxide film inside, and a silicon oxide film is so arranged on both sides of the nitrogen-containing silicon oxide film as to sandwich the nitrogen-containing silicon oxide film. In addition, the nitrogen composition in the nitrogen-containing silicon oxide film is increased from the semiconductor substrate side to the first gate electrode side.Type: ApplicationFiled: December 1, 2006Publication date: December 24, 2009Inventors: Hiroshi Sunamura, Kouji Masuzaki, Masayuki Terai
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Publication number: 20090317955Abstract: A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first transistor, and a CMOS section formed at the semiconductor substrate and including a second transistor having a CMOS electrode and a gate dielectric and a second STI region for isolating the second transistor. The height of the top surface of the first STI region is set equal to or smaller than the height of the top surface of the second STI region.Type: ApplicationFiled: September 1, 2009Publication date: December 24, 2009Applicant: PANASONIC CORPORATIONInventors: Nobuyoshi TAKAHASHI, Satoshi Iwamoto, Fumihiko Noro, Masatoshi Arai
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Patent number: 7635630Abstract: A plurality of mesas are formed in the substrate. Each pair of mesas forms a trench. A plurality of diffusion areas are formed in the substrate. A mesa diffusion area is formed in each mesa top and a trench diffusion area is formed under each trench. A vertical, non-volatile memory cell is formed on each sidewall of the trench. Each memory cell is comprised of a fixed threshold element located vertically between a pair of non-volatile gate insulator stacks. In one embodiment, each gate insulator stack is comprised of a tunnel insulator formed over the sidewall, a deep trapping layer, and a charge blocking layer. In another embodiment, an injector silicon rich nitride layer is formed between the deep trapping layer and the charge blocking layer.Type: GrantFiled: May 15, 2008Date of Patent: December 22, 2009Assignee: Micron Technology, Inc.Inventor: Arup Bhattacharyya
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Publication number: 20090311840Abstract: A method of manufacturing a semiconductor device includes forming, over a substrate, a gate insulating film containing a high-k insulating film which is composed of a material having a dielectric constant larger than that of silicon dioxide film; forming a gate electrode containing a metal over the gate insulating film; forming extension regions by implanting an dopant into the substrate using the gate electrode as a mask; and annealing the substrate, having the dopant implanted therein, by flash lamp annealing or laser annealing; wherein the annealing further includes: a first step irradiating a substrate with a light pulse having a predetermined peak intensity; and a second step irradiating a substrate with light pulses having peak intensities lower than that of the light pulse used in the first step.Type: ApplicationFiled: June 15, 2009Publication date: December 17, 2009Applicant: NEC ELECTRONICS CORPORATIONInventor: Takashi ONIZAWA
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Publication number: 20090309154Abstract: Provided are a selection transistor and a method of fabricating the same. A selection transistor can be formed on an active region in a semiconductor substrate to include a gate electrode that includes recessed portions of a sidewall of the gate electrode which are recessed inward adjacent lower portions of the gate electrode to define a T-shaped cross section of the gate electrode. A tunnel insulating layer can be located between the gate electrode and the active region.Type: ApplicationFiled: June 17, 2009Publication date: December 17, 2009Inventors: Byung-kyu Cho, Hee-soo Kang, Dong-uk Choi, Choong-ho Lee