Abstract: A method of forming a flash memory device can include forming a tunneling oxide film on a semiconductor substrate, forming a charge storing layer on the tunneling oxide film, forming a first blocking oxide film on the charge storing layer at a first temperature, forming a second blocking oxide film on the first blocking oxide film at a second temperature higher than the first temperature, and forming a gate electrode on the second blocking oxide film.

Abstract: An isolated-nitride-region non-volatile memory cell is formed in a semiconductor substrate. Spaced-apart source and drain regions are disposed in the semiconductor substrate forming a channel therebetween. An insulating region is disposed over the semiconductor substrate. A gate is disposed over the insulating region and is horizontally aligned with the channel. A plurality of isolated nitride regions are disposed in the insulating region and are not in contact with either the channel or the gate.

Abstract: A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

Abstract: A method for fabricating a non-volatile memory device includes alternately stacking a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, etching the interlayer dielectric layers and the conductive layers to form a trench which exposes a surface of the substrate forming a first material layer over a resulting structure in which the trench is formed, forming a second material layer over the first material layer, removing portions of the second material layer and the first material layer formed on a bottom of the trench to expose the surface of the substrate, removing the second material layer, and burying a channel layer within the trench in which the second material layer is removed.

Abstract: With simply applying the gate voltage, the transistor will start sending out oscillating signals, working like a semiconductor “engine”. A special MOS field effect transistor (FET) includes an extended lightly doped drain and an intrinsic undoped or very lightly doped “gap” between the gate and the heavily doped source. The gap needs to be specially engineered so that the transistor is not always turned on by the MOSFET gate voltage, but will be turned on by the carriers from the forward-biased channel-drain junction diode. Oscillation occurs to the drain current (or voltage) when a suitable gate voltage is applied, due to the repeated back and forth actions of deep depletion in the transistor well and forward bias of the drain-well p-n junction diode. By forming a second spacer gate on one side of the main gate, the device can be used as a non-volatile memory, with the charges stored at the dielectrics / silicon interface, which can significantly impact the oscillating for the READ operation of a memory.

Abstract: A split gate nonvolatile memory cell on a semiconductor layer is made by forming a gate dielectric over the semiconductor layer. A first layer of gate material is deposited over the gate dielectric. The first layer of gate material is etched to remove a portion of the first layer of gate material over a first portion of the semiconductor layer and to leave a select gate portion having a sidewall adjacent to the first portion. A treatment is applied over the semiconductor layer to reduce a relative oxide growth rate of the sidewall to the first portion. Oxide is grown on the sidewall to form a first oxide on the sidewall and on the first portion to form a second oxide on the first portion after the applying the treatment. A charge storage layer is formed over the first oxide and along the second oxide. A control gate is formed over the second oxide and adjacent to the sidewall.

Abstract: Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide insulator nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the insulator nanolaminate layers.

Abstract: A method of making a semiconductor device on a semiconductor layer includes forming a gate dielectric and a first layer of gate material over the gate dielectric. The first layer is etched to remove a portion of the first layer of gate material over a first portion of the semiconductor layer and to leave a select gate portion. A storage layer is formed over the select gate portion and over the first portion of the semiconductor layer. A second layer of gate material is formed over the storage layer. The second layer of gate material is etched to remove a first portion of the second layer of gate material over a first portion of the select gate portion. A portion of the first portion of the select gate is etched out to leave an L-shaped select structure. The result is a memory cell with an L-shaped select gate.

Abstract: Embodiments of tunneling barriers and methods for same can embed modules exhibiting a monodispersion characteristic into a dielectric layer (e.g., between first and second layers forming a dielectric layer). In one embodiment, by embedding C60 molecules inbetween first and second insulating layers forming a dielectric layer, a field sensitive tunneling barrier can be implemented. In one embodiment, the tunneling barrier can be between a floating gate and a channel in a semiconductor structure. In one embodiment, a tunneling film can be used in nonvolatile memory applications where C60 provides accessible energy levels to prompt resonant tunneling through the dielectric layer upon voltage application.

Abstract: The present invention provides a dielectric film having a high permittivity and a high heat resistance. An embodiment of the present invention is a dielectric film (103) including a composite oxynitride containing an element A made of Hf, an element B made of Al or Si, and N and O, wherein mole fractions of the element A, the element B, and N expressed as B/(A+B+N) range from 0.015 to 0.095 and N/(A+B+N) equals or exceeds 0.045, and has a crystalline structure.

Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

Abstract: Methods of fabricating a silicon oxide layer using an inorganic silicon precursor and methods of fabricating a semiconductor device using the same are provided. The methods of fabricating a semiconductor device include forming a tunnel insulating layer and a charge storage layer on a substrate; forming a dielectric layer structure on the charge storage layer using an atomic layer deposition (ALD) method, the dielectric layer structure including a first dielectric layer formed of silicon oxide, a second dielectric layer on the first dielectric layer formed of a material different from the material forming the first dielectric layer, and a third dielectric layer formed of the silicon oxide on the second dielectric layer; and forming a control gate on the dielectric layer structure.

Abstract: A semiconductor device having a non-volatile memory is disclosed, whose disturb defect can be diminished or prevented. A memory cell of the non-volatile memory has a memory gate electrode formed over a main surface of a semiconductor substrate through an insulating film for charge storage. A first side wall is formed on a side face of the memory gate electrode, and at a side face of the first side wall, a second side wall is formed. On an upper surface of an n+-type semiconductor region for source in the memory cell there is formed a silicide layer whose end portion on the memory gate electrode MG side is defined by the second side wall.

Abstract: Nanocrystals are formed over an insulating layer by depositing a semiconductor layer over the insulating layer. The semiconductor layer is annealed to form a plurality of globules from the semiconductor layer. The globules are annealed using oxygen. Semiconductor material is deposited on the plurality of globules to add semiconductor material to the globules. After depositing the semiconductor material, the globules are annealed to form the nanocrystals. The nanocrystals can then be used in a storage layer of a non-volatile memory cell, especially a split-gate non-volatile memory cell having a select gate over the nanocrystals and a control gate adjacent to the select gate.

Abstract: A method of forming a semiconductor device is presented. A substrate prepared with a second gate is provided. The second gate is processed to form a second gate with a rounded corner and a first gate is formed on the substrate. The first gate is adjacent to and overlaps a portion of the second gate and the rounded corner.

Abstract: One aspect of the invention provides a semiconductor device that includes gate electrodes comprising a metal or metal alloy located over a semiconductor substrate, wherein the gate electrodes are free of spacer sidewalls. The device further includes source/drains having source/drain extensions associated therewith, located in the semiconductor substrate and adjacent each of the gate electrodes. A first pre-metal dielectric layer is located on the sidewalls of the gate electrodes and over the source/drains, and a second pre-metal dielectric layer is located on the first pre-metal dielectric layer. Contact plugs extend through the first and second pre-metal dielectric layers.

Abstract: The present invention provides a method of manufacturing a dielectric film having a high permittivity. An embodiment of the present invention is a method of manufacturing, on a substrate, a dielectric film including a metallic oxynitride containing an element A made of Hf or a mixture of Hf and Zr, an element B made of Al, and N and O. The manufacturing method includes: a step of forming a metallic oxynitride whose mole fractions of the element A, the element B, and N expressed as B/(A+B+N) has a range of 0.015?(B/A+B+N))?0.095 and N/(A+B+N) has a range of 0.045?(N/(A+B+N)) and a mole fraction O/A of the element A and O has a range expressed as 1.0<(O/A)<2.0, and having a noncrystalline structure; and a step of performing an annealing treatment at 700° C. or higher on the metallic oxynitride having a noncrystalline structure to form a metallic oxynitride including a crystalline phase with a cubical crystal incorporation percentage of 80% or higher.

Abstract: A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first transistor, and a CMOS section formed at the semiconductor substrate and including a second transistor having a CMOS electrode and a gate dielectric and a second STI region for isolating the second transistor. The height of the top surface of the first STI region is set equal to or smaller than the height of the top surface of the second STI region.

Abstract: A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers functions as gate electrodes of the memory cells.

Abstract: A method for fabricating a non-volatile memory of the invention includes providing a substrate, and a tunnel layer is formed on the substrate. A charge-trapping layer is formed on the tunnel layer using silane (SiH4), nitrous oxide (N2O), and ammonia (NH3) as a reactant gas. The charge-trapping layer has a refractive index greater than or equal to 1.49 but less than 1.96 at a wavelength of 633 nm. A top layer is formed on the charge-trapping layer. A gate is formed on the top layer.

Abstract: An apparatus and method for controlling the net doping in the active region of a semiconductor device in accordance with a gate length. The method includes doping a short channel device and a long channel device with a first dopant, and doping the short channel device and the long channel device with a second dopant at a same implantation energy, dose, and angle for both the short channel device and the long channel device. The second dopant neutralizes the first dopant in portion to a gate length of the short channel device and the second channel device.

Abstract: The object is simplification of a manufacturing process for nonvolatile memory by reducing additional processes for forming a charge storage structure, and downsizing of nonvolatile memory.

Abstract: To provide a technique capable of improving reliability of a semiconductor device having a nonvolatile memory cell by suppressing the reduction of the drive force. A memory cell is configured by a selection pMIS having a selection gate electrode including a conductive film exhibiting a p-type conductivity and a memory pMIS having a memory gate electrode including a conductive film exhibiting a p-type conductivity, and at the time of write, hot electrons are injected into a charge storage layer from the side of a semiconductor substrate 1 and at the time of erase, hot holes are injected into the charge storage layer from the memory gate electrode.

Abstract: A method for manufacturing NAND memory cells includes providing a substrate having a first doped region formed therein; sequentially forming a first dielectric layer, a storage layer and a patterned hard mask on the substrate; forming a STI defining a plurality of recesses in the substrate through the patterned hard mask; sequentially forming a second dielectric layer and a first conductive layer filling the recesses on the substrate; and performing a planarization process to remove a portion of the first conductive layer and the second dielectric layer to form a plurality of self-aligned islanding gate structures.

Abstract: A non-volatile memory located on a substrate is provided. The non-volatile memory includes a tunnel layer, a charge trapping composite layer, a gate and a source/drain region. The tunnel layer is located on the substrate, the charge trapping composite layer is located on the tunnel layer and the gate is located over the charge trapping composite layer. The source/drain region is located in the substrate on both sides of the tunnel layer. With the charge trapping composite layer, the non-volatile memory has relatively better programming and erasing performance and higher data retention ability. Furthermore, since there is no need to perform a thermal process in the formation of the charge trapping composite layer, thermal budget of the manufacturing process is low.

Abstract: A semiconductor memory includes a semiconductor substrate, a buried insulating film formed on a part of an upper surface of the semiconductor substrate, and a semiconductor layer formed on another part of the upper surface of the semiconductor substrate. Each of the memory cell transistors comprises a first-conductivity-type source region, a first-conductivity-type drain region, and a first-conductivity-type channel region arranged in the semiconductor layer in the column direction, and a gate portion formed on a side surface of the channel region in the row direction.

Abstract: A method of manufacturing a semiconductor memory device, the method including forming a tunnel insulation layer on a substrate, forming a preliminary charge trapping layer on the tunnel insulation layer, forming an etch stop layer on the preliminary charge trapping layer, wherein a portion of the preliminary charge trapping layer is not covered by the etch stop layer, removing the exposed portion of the preliminary charge trapping layer to form a charge trapping layer having a uniform thickness, forming a dielectric layer on the charge trapping layer, and forming a gate electrode on the dielectric layer.

Abstract: The charge retention characteristics of a non-volatile memory, particularly, a MONOS-type non-volatile memory is improved. In a non-volatile memory cell including a tunnel silicon oxide film (107), a silicon nitride film (104) serving as a charge storage film, a silicon oxide film (105), and a gate electrode (108) which are sequentially formed on a semiconductor substrate, the tunnel silicon oxide film (107) has a stacked structure of a silicon oxynitride film (102) and a silicon oxide film (103). Herein, it is configured such that a density of nitrogen atoms contained in the silicon oxynitride film (102) decreases as a distance from an interface with the semiconductor substrate increases in a film-thickness direction of the silicon oxynitride film (102).

Abstract: In a nonvolatile semiconductor memory device of the method which enables a single cell to store more than or equal to 2-bit information, it is possible to prevent wire failure and ensure high operation reliability. The nonvolatile semiconductor memory device 200 includes a trench 203 having a round wall portion 203b; a tunnel oxide film 205, silicon nitride films 207a and 207b as charge trapping regions, a silicon dioxide film 209, a gate electrode 211, and a first source/drain region 213a and a second source/drain region 213b formed on Si substrates 201 arranged to have the gate electrode 211 therebetween.

Abstract: The present invention relates to a flash memory device and a fabrication method thereof. A trench may be formed within a junction region between word lines by etching a semiconductor substrate between not only a word line and a select line, but also between adjacent word lines. Accordingly, the occurrence of a program disturbance phenomenon can be prevented as the injection of hot carriers into a program-inhibited cell is minimized in a program operation.

Abstract: A semiconductor device includes: a first layer; a second layer; a columnar structural unit; and a side portion. The second layer is provided on a major surface of the first layer. The columnar structural unit is conductive and aligned in the first layer and the second layer to pass through the major surface. The side portion is added to a side wall of the columnar structural unit on the second layer side of the major surface.

Abstract: An insulating film having Hf and O is formed over a semiconductor substrate. A cap film having oxygen and titanium as constituent elements is formed over the insulating film. The insulating film and cap film are thermally treated in a nitrogen gas or noble gas to diffuse titanium in the cap film into the insulating film to form a gate insulating film. A gate electrode film is formed over the gate insulating film.

Abstract: A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.

Abstract: Disclosed are embodiments of a semiconductor structure and method of forming the structure with selectively adjusted reflectance and absorption characteristics in order to selectively control temperature changes during a rapid thermal anneal and, thereby, to selectively control variations in device performance and/or to selectively optimize the anneal temperature of such devices. Selectively controlling the temperature changes in different devices during a rapid thermal anneal is accomplished by selectively varying the isolation material thickness in different sections of a shallow trench isolation structures. Alternatively, it is accomplished by selectively varying the pattern of fill structures in different sections of a semiconductor wafer so that predetermined amounts of shallow trench isolation regions in the different sections are exposed.

Abstract: A flash memory device and a method of manufacturing a flash memory device. A flash memory device may include an isolation layer and/or an active area over a semiconductor substrate, a memory gate formed over an active area, a control gate formed over a semiconductor substrate including a memory gate, and/or a common source line contact formed over a semiconductor substrate including a control gate. A flash memory device may include a source plate having substantially the same interval as an interval of an active area of a bit line. A source plate may include an active area in which a common source line contact may be formed. A common source line contact may include a long butting contact extending in a direction traversing an active area.

Abstract: Disclosed are a dual bit type NROM flash memory device and a method for manufacturing the same using a self-aligned scheme. The flash memory device includes a plurality of bit lines buried in a substrate in one direction while being spaced apart from each other at a regular interval; floating gates aligned at both sides of each of the bit lines on the substrate; and a plurality of word lines spaced apart from each other at a regular interval while crossing the bit lines. In the flash memory device of an embodiment, polysilicon is used for a trapping layer, so the programming and erasing operations can be performed at a higher speed, a threshold voltage (Vt) window is widened, and retention characteristics are improved.

Abstract: Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layers and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gate layers in the opening.

Abstract: An object of the present invention is to provide a nonvolatile semiconductor storage device with a superior charge holding characteristic in which highly-efficient writing is possible at low voltage, and to provide a manufacturing method thereof. The nonvolatile semiconductor storage device includes a semiconductor film having a pair of impurity regions formed apart from each other and a channel formation region provided between the impurity regions; and a first insulating film, a charge accumulating layer, a second insulating film, and a conductive film functioning as a gate electrode layer which are provided over the channel formation region. In the nonvolatile semiconductor storage device, a second barrier formed by the first insulating film against a charge of the charge accumulating layer is higher in energy than a first barrier formed by the first insulating film against a charge of the semiconductor film.

Abstract: A semiconductor memory device includes: a semiconductor substrate, on which an impurity diffusion layer is formed in a cell array area; a gate wiring stack body formed on the cell array area, in which multiple gate wirings are stacked and separated from each other with insulating films; a gate insulating film formed on the side surface of the gate wiring stack body, in which an insulating charge storage layer is contained; pillar-shaped semiconductor layers arranged along the gate wiring stack body, one side surfaces of which are opposed to the gate wiring stack body via the gate insulating film, each pillar-shaped semiconductor layer having the same conductivity type as the impurity diffusion layer; and data lines formed to be in contact with the upper surfaces of the pillar-shaped semiconductor layers and intersect the gate wirings.

Abstract: A method of manufacturing a flash memory device includes preparing a semiconductor substrate comprising a cell area and a peripheral area, forming a first well and an oxide-nitride-oxide (ONO) layer in the cell area, forming a second well in the peripheral area of the semiconductor substrate comprising the first well and forming a first oxide layer in the peripheral area, forming a first polysilicon layer over the ONO layer and the first oxide layer and performing a first etch process to form a memory gate comprising an ONO layer pattern and a first polysilicon pattern in the cell area, forming a second oxide layer pattern and a second polysilicon pattern over either sidewall of the memory gate and forming a gate in the peripheral area, performing a third etch process so that the second oxide layer pattern and the second polysilicon pattern remain over only the one sidewall of the memory gate to form a select gate, and forming a first impurity area in the semiconductor substrate between the memory gates adjac

Abstract: The semiconductor device has a stacked structure in which a tunnel oxide layer, a charge trapping layer, a blocking oxide layer, and a gate electrode are sequentially formed on a silicon substrate, wherein the blocking oxide layer includes a crystalline layer disposed adjacent to the charge trapping layer and an amorphous layer disposed adjacent to the gate electrode.

Abstract: In a nonvolatile memory cell with charge trapping dielectric (150), the tunnel dielectric (140) includes chlorine adjacent to the charge trapping dielectric but no chlorine (or less chlorine) adjacent to the cell's channel region (120). The chlorine adjacent to the charge trapping dielectric serves to improve the programming and/or erase speed. The low chlorine concentration adjacent to the channel region prevents chlorine from degrading the data retention. Other features are also provided.

Abstract: A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking layer of metal doped silicon oxide material having a medium dielectric constant, such as aluminum doped silicon oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric.

Abstract: A flash memory device and a method of manufacturing a flash memory device. A flash memory device may include a device isolation layer and/or an active area formed on and/or over a semiconductor substrate. A flash memory device may include a memory gate formed on and/or over an active area and/or a control gate formed on and/or over a semiconductor substrate including a memory gate. Active areas may be formed having substantially the same interval with bit lines. A common source line area where a common source line contact may be formed may include a bridge formed between active areas. Neighboring active areas may be connected.

Abstract: Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.

Abstract: A nonvolatile memory device with nanowire channel and a method for fabricating the same are proposed, in which side etching is used to shrink side walls of a side-gate to form a nanowire pattern, thereby fabricating a nanowire channel on the dielectric of the side walls of the side-gate. A nonvolatile memory device with nanowire channel and dual-gate control can thus be achieved. This nonvolatile memory device can enhance data writing and erasing efficiency, and also has the capability of low voltage operation. Moreover, through a process of low cost and easy steps, highly reproducible and mass producible fabrication of nanowire devices can be accomplished.

Abstract: A technique capable of improving the memory retention characteristics of a non-volatile memory is provided. In particular, a technique of fabricating a non-volatile semiconductor memory device is provided capable of enhancing the film quality of a silicon oxide film even when a silicon oxide film as a first potential barrier film is formed with a plasma oxidation method to improve the memory retention characteristics of the non-volatile memory. After a silicon oxide film, which is a main component of a first potential barrier film, is formed with a plasma oxidation method, plasma nitridation at a high temperature and a heat treatment in an atmosphere containing nitric oxide are performed in combination, thereby forming a silicon oxynitride film on the surface of the silicon oxide film, and segregating nitrogen to an interface between the silicon oxide film and a semiconductor substrate.

Abstract: In a method of fabricating a semiconductor device, an additive gas is mixed with an etching gas to reduce a fluorine ratio of the etching gas. The etching gas having a reduced fluorine rate is utilized in the process for etching a nitride layer formed on an oxide layer to prevent the oxide layer formed below the nitride layer from being etched along with the nitride layer. The method comprises primarily etching an exposed charge storage layer using an etching gas; and secondarily etching the charge storage layer using the etching gas under a condition that a ratio of fluorine contained in the etching gas utilized in the secondary etching step is less than a ratio of fluorine contained in the etching gas utilized in the primary etching step. Thus, the tunnel insulating layer formed below the charge storage layer is not damaged when the charge storage layer is patterned.

Abstract: A method of manufacturing a nonvolatile memory device having a three-dimensional memory device includes alternately stacking a plurality of first and second material layers having a different etching selectivity on a semiconductor substrate; forming an opening penetrating the plurality of first and second material layers; removing the first material layers exposed by the opening to form extended portions extending in a direction perpendicular to the semiconductor substrate from the opening; conformally forming a charge storage layer along a surface of the opening and the extended portions; and removing the charge storage layer formed on sidewalls of the second material layers to locally form the charge storage layer patterns in the extended portions.