Abstract: According to one embodiment, a semiconductor memory device includes a base, a stacked body, a memory film, a channel body, a contact plug, a global bit line, and a plurality of local bit lines. The base has a substrate and a peripheral circuit formed on the substrate. The stacked body has a plurality of conductive layers and insulating layers stacked alternately above the base. The memory film includes a charge storage film provided on an inner wall of a memory hole formed in a stacking direction of the stacked body. The channel body is provided inside the memory film in the memory hole. The contact plug is provided by piercing the stacked body. The global bit line is provided between the peripheral circuit and the stacked body and connected to a lower end portion of the contact plug. The plurality of local bit lines are provided above the stacked body and divided in an extending direction of the plurality of local bit lines.

Abstract: The memory device is described, which includes a substrate, a conductive layer, a plurality of charge storage layers and a plurality of doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layers are disposed between the substrate and the conductive layer in the trenches respectively, wherein the charge storage layers are separated from each other. The doped regions are configured in the substrate under bottoms of the trenches, respectively.

Abstract: Storage transistors for flash memory areas in semiconductor devices may be provided on the basis of a self-aligned charge storage region. To this end, a floating spacer element may be provided in some illustrative embodiments, while, in other cases, the charge storage region may be efficiently embedded in the electrode material in a self-aligned manner during a replacement gate approach. Consequently, enhanced bit density may be achieved, since additional sophisticated lithography processes for patterning the charge storage region may no longer be required.

Abstract: Nonvolatile memory devices are provided including an integrated circuit substrate and a charge storage pattern on the integrated circuit substrate. The charge storage pattern has a sidewall and a tunnel insulating layer is provided between the charge storage pattern and the integrated circuit substrate. A gate pattern is provided on the charge storage pattern. A blocking insulating layer is provided between the charge storage pattern and the gate pattern. The sidewall of the charge storage pattern includes a first nitrogen doped layer. Related methods of fabricating nonvolatile memory devices are also provided herein.

Abstract: A method for making a nitride read only memory device with buried diffusion spacers is disclosed. An oxide-nitride-oxide (ONO) layer is formed on top of a silicon substrate, and a polysilicon gate is formed over the ONO layer. The polysilicon gate is formed less than a length of the ONO layer. Two buried diffusion spacers are formed beside two sidewalls of the polysilicon gate and over the ONO layer. Two buried diffusion regions are implanted on the silicon substrate next to the two buried diffusion spacers. The two buried diffusion regions are then annealed such that the approximate interfaces of the buried diffusion regions are under the sidewalls of the polysilicon gate. The structure of a nitride read only memory device with buried diffusion spacers is also described.

Abstract: A semiconductor device according to example embodiments may include a channel including a nanowire and a charge storage layer including nanoparticles. A twin gate structure including a first gate and a second gate may be formed on the charge storage layer. The semiconductor device may be a memory device or a diode.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include forming a stacked body by alternately stacking a plurality of insulating layers and a plurality of conductive layers above a substrate and forming a resist film above the stacked body. The method can include plasma-etching the insulating layers and the conductive layers by using the resist film as a mask. The method can include forming a hardened layer in an upper surface of the resist film by plasma treatment using a gas containing at least one selected from a group consisting of boron, phosphorus, arsenic, antimony, silicon, germanium, aluminum, gallium, and indium. The method can include slimming a plane size of the resist film by plasma treatment using an oxygen-containing gas in a state where the hardened layer is formed in the upper surface of the resist film.

Abstract: A non-volatile memory device is provided in which quantum dots are embedded in an oxide thin film formed on a substrate. A conventional Si CMOS process can be used to manufacture the non-volatile memory device in a cost-effective way. Also, a photonic device and an electronic/photonic device, which can store a light signal or emit a stored signal as light, can be produced on a Si wafer in a cost-effective manner.

Abstract: A device and method of formation are provided for a high-k gate dielectric and gate electrode. The high-k dielectric material is formed, and a silicon-rich film is formed over the high-k dielectric material. The silicon-rich film is then treated through either oxidation or nitridation to reduce the Fermi-level pinning that results from both the bonding of the high-k material to the subsequent gate conductor and also from a lack of oxygen along the interface of the high-k dielectric material and the gate conductor. A conductive material is then formed over the film through a controlled process to create the gate conductor.

Abstract: A semiconductor device includes an element region having a channel region, and a unit gate structure inducing a channel in the channel region, the unit gate structure including a tunnel insulating film formed on the element region, a charge storage insulating film formed on the tunnel insulating film, a block insulating film formed on the charge storage insulating film, and a control gate electrode formed on the block insulating film, wherein a distance between the element region and the control gate electrode is shorter at a center portion of the unit gate structure than at both ends thereof, as viewed in a section parallel to a channel width direction.

Abstract: The electrically erasable programmable memory and its manufacturing method of the present invention forms above the floating gate the polysilicon spacer regions that are extended from the central part of the source region; the insulating part between the polysilicon spacer region and the floating gate has a smaller thickness to increase the capacitance between the floating gate and the polysilicon spacer region and further increasing the voltage coupled to the floating gate. Therefore, the present invention can effectively increase the coupling capacitance at the drain terminal, and has an advantage of low cost and easy production.

Abstract: A memory device includes a first active region on a substrate and first and second source/drain regions on the substrate abutting respective first and second sidewalls of the first active region. A first gate structure is disposed on the first active region between the first and second source/drain regions. A second active region is disposed on the first gate structure between and abutting the first and second source/drain regions. A second gate structure is disposed on the second active region overlying the first gate structure.

Abstract: A flash memory and a manufacturing method and an operating method thereof are provided. The flash memory includes a substrate, a charge-trapping structure, a first gate, a second gate, a third gate, a first doped region and a second doped region. The substrate has a protrusion portion. The charge-trapping structure is disposed over the substrate. The first gate and the second gate are disposed respectively over the charge-trapping structure at two sides of the protrusion portion. The top surfaces of the first gate and the second gate are lower than the top surface of the charge-trapping structure located on the top of the protrusion portion. The third gate is disposed over the charge-trapping structure located on the top of the protrusion portion. The first doped region and the second doped region are disposed respectively in the substrate at two sides of the protrusion portion.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor layer; first and second insulating layers; a functional layer; first and second gate electrodes. The first insulating layer opposes the semiconductor layer. The second insulating layer is provided between the semiconductor layer and the first insulating layer. The functional layer is provided between the first and second insulating layers. The second gate electrode is separated from the first gate electrode. The first insulating layer is disposed between the first gate electrode and the semiconductor layer and between the second gate electrode and the semiconductor layer. The charge storabilities in first and second regions of the functional layer are different from that of a third region of the functional layer. The first and second regions oppose the first and second gate electrodes, respectively. The third region is between the first and the second regions.

Abstract: Methods of manufacturing NOR-type flash memory device include forming a tunnel oxide layer on a substrate, forming a first conductive layer on the tunnel oxide layer, forming first mask patterns parallel to one another on the first conductive layer in a y direction of the substrate, and selectively removing the first conductive layer and the tunnel oxide layer using the first mask patterns as an etch mask. Thus, first conductive patterns and tunnel oxide patterns are formed, and first trenches are formed to expose the surface of the substrate between the first conductive patterns and the tunnel oxide patterns. A photoresist pattern is formed to open at least one of the first trenches, and impurity ions are implanted using the photoresist pattern as a first ion implantation mask to form an impurity region extending in a y direction of the substrate. The photoresist pattern is removed.

Abstract: A method for fabricating SONOS memory is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer on the surface of the semiconductor substrate; forming a hard mask on the second silicon oxide layer; patterning the hard mask, the second silicon oxide layer, the silicon nitride layer, and the first silicon oxide layer to form a patterned hard mask and a stacked structure; forming a gate oxide layer on surface of the patterned hard mask; removing the gate oxide layer and the patterned hard mask; forming a patterned polysilicon layer on surface of the stacked structure; and forming a source/drain region in the semiconductor substrate adjacent to two sides of the polysilicon layer.

Abstract: A nonvolatile semiconductor memory device includes a first stacked body on a silicon substrate, and a second stacked body is provided thereon. The first stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films, and a first portion of a through-hole extending in a stacking direction is formed. The second stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films, and a second portion of the through-hole is formed. A memory film is formed on an inner face of the through-hole, and a silicon pillar is buried in an interior of the through-hole. A central axis of the second portion of the through-hole is shifted from a central axis of the first portion, and a lower end of the second portion is positioned lower than an upper portion of the first portion.

Abstract: A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers.

Abstract: A flash memory device and a method for fabricating the same are disclosed. The flash memory device includes an ONO layer on a substrate, polysilicon gates on the ONO layer, a gate oxide layer on the substrate, the ONO layer and the polysilicon gates, and a low temperature oxide layer and polysilicon sidewall spacers on outer side surfaces of the polysilicon gates, except in a region between nearest adjacent polysilicon gates.

Abstract: A method of making a semiconductor device on a semiconductor layer is provided. The method includes: forming a select gate dielectric layer over the semiconductor layer; forming a select gate layer over the select gate dielectric layer; and forming a sidewall of the select gate layer by removing at least a portion of the select gate layer. The method further includes growing a sacrificial layer on at least a portion of the sidewall of the select gate layer and under at least a portion of the select gate layer and removing the sacrificial layer to expose a surface of the at least portion of the sidewall of the select gate layer and a surface of the semiconductor layer under the select gate layer. The method further includes forming a control gate dielectric layer, a charge storage layer, and a control gate layer.

Abstract: A method for manufacturing NAND memory cells includes providing a substrate having a first doped region formed therein; sequentially forming a first dielectric layer, a storage layer and a patterned hard mask on the substrate; forming a STI defining a plurality of recesses in the substrate through the patterned hard mask; sequentially forming a second dielectric layer and a first conductive layer filling the recesses on the substrate; and performing a planarization process to remove a portion of the first conductive layer and the second dielectric layer to form a plurality of self-aligned islanding gate structures.

Abstract: The present invention relates to a flash memory device and a fabrication method thereof. A trench may be formed within a junction region between word lines by etching a semiconductor substrate between not only a word line and a select line, but also between adjacent word lines. Accordingly, the occurrence of a program disturbance phenomenon can be prevented as the injection of hot carriers into a program-inhibited cell is minimized in a program operation.

Abstract: The present invention provides a manufacturing method of a dielectric film which reduces a leak current value while suppressing the reduction of a relative permittivity, suppresses the reduction of a deposition rate caused by the reduction of a sputtering rate, and also provides excellent planar uniformity. A dielectric film manufacturing method according to an embodiment of the present invention is forms a dielectric film of a metal oxide mainly containing Al, Si, and O on a substrate, and comprises steps of forming the metal oxide having an amorphous structure in which a molar fraction between an Al element and a Si element, Si/(Si+Al), is 0<Si/(Si+Al)?0.1, and subjecting the metal oxide having the amorphous structure to annealing treatment at a temperature of 1000° C. or more to form the metal oxide including a crystalline phase.

Abstract: A method of fabricating a semiconductor device includes: forming a first polysilicon layer having a first thickness in a peripheral circuit region formed on a substrate; forming a stack structure comprising a first tunneling insulating layer, a charge trap layer, and a blocking insulating layer in a memory cell region formed on the substrate; forming a second polysilicon layer having a second thickness that is less than the first thickness on the blocking insulating layer; and forming gate electrodes by siliciding the first and second polysilicon layers.

Abstract: Some embodiments include methods of utilizing polysilazane in forming non-volatile memory cells. The memory cells may be multi-level cells (MLCs). The polysilazane may be converted to silicon nitride, silicon dioxide, or silicon oxynitride with thermal processing and exposure to an ambient that contains one or both of oxygen and nitrogen. The methods may include using the polysilazane in forming a charge trapping layer of a non-volatile memory cell. The methods may alternatively, or additionally include using the polysilazane in forming intergate dielectric material of a non-volatile memory cell. Some embodiments include methods of forming memory cells of a NAND memory array.

Abstract: A semiconductor device having a non-volatile memory and a method of manufacturing the same are provided. The semiconductor device includes a base material and a stack structure. The stack structure disposed on the base material at least includes a tunneling layer, a trapping layer and a dielectric layer. The trapping layer is disposed on the tunneling layer. The dielectric layer has a dielectric constant and is disposed on the trapping layer. The dielectric layer is transformed from a first solid state to a second solid state when the dielectric layer undergoes a process.

Abstract: A method for manufacturing a twin bit cell structure with an aluminum oxide material includes forming a gate dielectric layer overlying a semiconductor substrate and a polysilicon gate structure overlying the gate dielectric layer. An undercut region is formed in each side of the gate dielectric layer underneath the polysilicon gate structure. Thereafter, an oxidation process is performed to form a first silicon oxide layer on a peripheral surface of the polysilicon gate structure and a second silicon oxide layer on an exposed surface of the semiconductor substrate. Then, an aluminum oxide material is deposited over the first and second silicon oxide layers including the undercut region and the gate dielectric layer. The aluminum oxide material is selectively etched to form an insert region in a portion of the undercut region. A sidewall spacer is formed to isolate and protect the exposed aluminum oxide material and the polysilicon gate structure.

Abstract: A method for forming a twin-bit cell structure is provided. The method includes providing a semiconductor substrate including a surface region. A gate dielectric layer is formed overlying the surface region. The method forms a polysilicon gate structure overlying the gate dielectric layer. In a specific embodiment, the method subjects the gate polysilicon structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the gate polysilicon structure. Preferably, an undercut region is allowed to be formed underneath the gate polysilicon structure. The method includes forming an undoped polysilicon material overlying the polysilicon gate structure including the undercut region and the gate dielectric layer. The undoped polysilicon material is subjected to a selective etching process to form an insert region in a portion of the undercut region while the insert region remains filled with the undoped polysilicon material.

Abstract: A method of manufacturing a flash memory device is provided. First and second gates are formed on first and second dielectrics and spaced apart from each other on a cell area of a substrate. A third gate is formed on a third dielectric that is formed on first opposing sidewalls of the first gate and extending on a portion of the substrate from the first opposing sidewalls. A fourth gate is formed on a fourth dielectric that is formed on second opposing sidewalls of the second gate and extending on a portion of the substrate from the second opposing sidewalls. The third gate and third dielectric on one of the first opposing sidewalls facing the second gate and the fourth gate and fourth dielectric on one of the second opposing sidewalls facing the first gate are removed. Drain areas are formed at outer sides of the third and fourth gates, and a common source area is formed between the first and second gates.

Abstract: A semiconductor storage element includes: a semiconductor layer constituted of a line pattern with a predetermined width formed on a substrate; a quantum dot forming an electric charge storage layer formed on the semiconductor layer through a first insulating film serving as a tunnel insulating film; an impurity diffusion layer formed in a surface layer of the semiconductor layer so as to sandwich the quantum dot therebetween; and a control electrode formed on the quantum dot through a second insulating film.

Abstract: A charge trap type non-volatile memory device has memory cells formed on a silicon substrate at a predetermined interval via an element isolation trench along a first direction in which word lines extend. Each of the memory cells has a tunnel insulating film formed on the silicon substrate, a charge film formed on the tunnel insulating film, and a common block film formed on the charge film. The common block film is formed in common with the memory cells along first direction. An element isolation insulating film buried in the element isolation trench has an upper portion of a side wall of the element isolation insulating film which contacts with a side wall of the charge film in each of the memory cells and a top portion of the element isolation insulating film which contacts with the common block film. A control electrode film is formed on the common block film.

Abstract: A multi-functional and multi-level memory cell comprises a tunnel layer formed over a substrate. In one embodiment, the tunnel layer comprises two layers such as HfO2 and LaAlO3. A charge blocking layer is formed over the tunnel layer. In one embodiment, this layer is formed from HfSiON. A control gate is formed over the charge blocking layer. A discrete trapping layer is embedded in either the tunnel layer or the charge blocking layer, depending on the desired level of non-volatility. The closer the discrete trapping layer is formed to the substrate/insulator interface, the lower the non-volatility of the device. The discrete trapping layer is formed from nano-crystals having a uniform size and distribution.

Abstract: A method for making a nitride read only memory device with buried diffusion spacers is disclosed. An oxide-nitride-oxide (ONO) layer is formed on top of a silicon substrate, and a polysilicon gate is formed over the ONO layer. The polysilicon gate is formed less than a length of the ONO layer. Two buried diffusion spacers are formed beside two sidewalls of the polysilicon gate and over the ONO layer. Two buried diffusion regions are implanted on the silicon substrate next to the two buried diffusion spacers. The two buried diffusion regions are then annealed such that the approximate interfaces of the buried diffusion regions are under the sidewalls of the polysilicon gate. The structure of a nitride read only memory device with buried diffusion spacers is also described.

Abstract: A method of manufacturing a nonvolatile semiconductor memory device includes the steps of preparing a wafer having multiple memory cells, each memory cell having a gate electrode formed on a semiconductor substrate, charge storage units formed on both sides of the gate electrode, lightly doped regions formed beneath the charge storage units, respectively, in the upper part of the semiconductor substrate, and highly doped regions formed in a pair of regions sandwiching a region underneath the gate electrode and the lightly doped regions in between; erasing data stored in the charge storage units electrically; and treating the wafer at a high temperature for a predetermined period of time.

Abstract: A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.

Abstract: A method of fabricating a non-volatile memory device includes forming an isolation trench in a semiconductor substrate, and the isolation trench defines first and second fins. The method further includes forming an isolation layer partially filling the isolation trench, forming first and second charge trap patterns respectively covering parts of the first and second fins projecting from the isolation layer, and forming a control gate electrode covering the first and second charge trap patterns and crossing the first and second fins.

Abstract: An integrated circuit includes flash memory cells, and peripheral circuitry including low voltage transistors (LVT) and high voltage transistors (HVT). The integrated circuit includes a tunnel barrier layer comprising SiON, SiN or other high-k material. The tunnel barrier layer may comprise a part of the gate dielectric of the HVTs. The tunnel barrier layer may constitute the entire gate dielectric of the HVTs. The corresponding tunnel barrier layer may be formed between or upon shallow trench isolation (STIs). Therefore, the manufacturing efficiency of a driver chip IC may be increased.

Abstract: The present invention provides a system comprising a semiconductor device, a method of controlling the semiconductor device in the system, and a method of manufacturing the semiconductor device in the system. The semiconductor device includes: a semiconductor region located in a semiconductor layer formed on an isolating layer; an ONO film on the semiconductor region; bit lines on either side of the semiconductor region, which are located in the semiconductor layer, and are in contact with the isolating layer; a device isolating region on two different sides of the semiconductor region from the sides on which the bit lines are located, the device isolating region being in contact with the isolating layer; and a first voltage applying unit that is coupled to the semiconductor region. In this semiconductor device, the semiconductor region is surrounded by the bit lines and the device isolating region, and is electrically isolated from other semiconductor regions.

Abstract: A memory device includes a first active region on a substrate and first and second source/drain regions on the substrate abutting respective first and second sidewalls of the first active region. A first gate structure is disposed on the first active region between the first and second source/drain regions. A second active region is disposed on the first gate structure between and abutting the first and second source/drain regions. A second gate structure is disposed on the second active region overlying the first gate structure.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a foundation layer, a lower layer side stacked body, an upper layer side stacked body, an inter-layer insulating layer, and a plurality of contact electrodes. The foundation layer is provided in the second contact region to form a difference in levels between the second contact region and the first contact region. The lower layer side stacked body includes a plurality of conductive layers stacked alternately with a plurality of insulating layers. An upper level portion of the lower layer side stacked body stacked on the foundation layer is patterned into a stairstep configuration. The upper layer side stacked body is provided on a lower level portion of the lower layer side stacked body stacked in the first contact region. The upper layer side stacked body includes a plurality of conductive layers stacked alternately with a plurality of insulating layers.

Abstract: Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.

Abstract: A method of fabricating a non-volatile memory cell is disclosed. The method includes the steps of: forming two separate charge trapping structures on a semiconductor substrate; forming first spacers on sidewalls of the two charge trapping structures; forming a gate dielectric layer on the substrate; forming a gate on the two charge trapping structures and the gate dielectric layer between the two charge trapping structures; and forming two doped regions in the substrate besdie the gate.

Abstract: Devices and methods for forming self-aligned charge storage regions are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a layer of a nitride film stacked between two oxide films on a semiconductor substrate, and forming a gate electrode on the layer of the nitride film stacked between the two oxide films. In addition, the method comprises removing side portions of the nitride film such that a central portion of the nitride film below a center portion of the gate electrode remains, oxidizing the central portion of the nitride film, and forming charge storage layers in the side portions of the nitride film, where the charge storage layers are separated by the central portion of the nitride film.

Abstract: In a non-volatile flash memory device, and a method of fabricating the same, the device includes a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, a tunneling layer pattern, a charge trap layer pattern and a shielding layer pattern, which are sequentially stacked on the semiconductor substrate between the source region and the drain region, adjacent to the source region, a first channel region disposed in the semiconductor substrate below the tunneling layer pattern, a gate insulating layer disposed on the semiconductor substrate between the drain region and the first channel region, a second channel region disposed in the semiconductor substrate below the gate insulating layer, a concentration of the second channel region being different from that of the first channel region, and a gate electrode covering the shielding layer pattern and the gate insulating layer.

Abstract: On a silicon substrate is formed a stacked body by alternately stacking a plurality of silicon oxide films and silicon films, a trench is formed in the stacked body, an alumina film, a silicon nitride film and a silicon oxide film are formed in this order on an inner surface of the trench, and a channel silicon crystalline film is formed on the silicon oxide film. Next, a silicon oxide layer is formed at an interface between the silicon oxide film and the channel silicon crystalline film by performing thermal treatment in an oxygen gas atmosphere.

Abstract: A device comprises an impurity ion disposed in an insulating region, a semiconductor region adjacent to the insulating region, an electrometer arranged to detect charge carriers in the semiconductor region and at least one control gate configured to apply an electric field to the insulating region and semiconductor region. The at least one control gate is operable to cause at least one charge carrier in the semiconducting material region to bind to the impurity ion without the at least one charge carrier leaving the semiconductor material region. The electrometer is operable to detect whether the at least one charge carrier is bound to the impurity ion.

Abstract: Embodiments of methods of forming non-volatile memory structures are provided. In one such embodiment, first and second source/drain regions are formed on a substrate so that the first and second source/drain regions define an intervening channel region. A charge blocking layer is formed over the channel region. A trapping layer is formed over the charge blocking layer. A tunnel layer of two or more sub-layers is formed over the trapping layer, where the two or more sub-layers form a crested barrier tunnel layer. A control gate is formed over the tunnel layer.

Abstract: To manufacture a MOS semiconductor memory device having an insulating film laminate in which adjacent insulating films have band-gaps of different sizes, a plasma processing device which transmits microwaves to a chamber by means of a planar antenna having a plurality of holes is used to perform plasma CVD under pressure conditions that differ from at least pressure conditions used when forming the adjacent insulating films, and the insulating films are sequentially formed by altering the band-gaps of the adjacent insulating films that constitute the insulating film laminate.

Abstract: A non-volatile memory device having a Polysilicon Oxide Nitride Oxide Semiconductor (SONOS) structure in which a charge trap layer is separated physically in a horizontal direction, and a method of manufacturing the same. The charge trap layer that traps electric charges toward the source and the drain is physically divided. It can fundamentally prevent the charges at both sides from being moved mutually. It is therefore possible to prevent interference between charges at both sides although the cell size is reduced.

Abstract: A memory cell is provided. The memory cell includes a substrate, an isolation layer, a gate, a charge storage structure, a first source/drain region, a second source/drain region and a channel layer. The isolation layer is disposed over the substrate. The gate is disposed over the isolation layer. The charge storage structure is disposed over the isolation layer and the gate. The first source/drain region is disposed over the charge storage structure at two sides of the gate. The second source/drain region is disposed over the charge storage structure at top of the gate. The channel layer is disposed over the charge storage structure at sidewall of the gate and is electrically connected with the first source/drain region and the second source/drain region.