Testing Or Measuring During Manufacture Or Treatment Or Reliability Measurement, I.e., Testing Of Parts Followed By No Processing Which Modifies Parts As Such (epo) Patents (Class 257/E21.521)

  • Publication number: 20130292817
    Abstract: A structure and method for monitoring interlevel dielectric stress damage. The structure includes a monitor solder bump and normal solder bumps; a set of stacked interlevel dielectric layers between the substrate and the monitor solder bump and the normal solder bumps, one or more ultra-low K dielectric layers comprising an ultra-low K material having a dielectric constant of 2.4 or less; a monitor structure in a region directly under the monitor solder bump in the ultra-low K dielectric layers and wherein the conductor density in at least one ultra-low K dielectric layer in the region directly under the monitor solder bumps is less than a specified minimum density and the conductor density in corresponding regions of the ultra-low K dielectric layers directly under normal solder bumps is greater than the specified minimum density.
    Type: Application
    Filed: May 2, 2012
    Publication date: November 7, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Luke D. LaCroix, Mark Lamorey, Janak G. Patel, Peter Slota, JR., David B. Stone
  • Patent number: 8574931
    Abstract: Strip testing is applied to a plurality of integrated circuit dies that are each encapsulated in an encapsulant, that each have a set of externally accessible leads connected thereto, and that are electrically isolated from one another. Provision is made for the strip testing to be performed without mounting the encapsulated integrated circuit dies on a support tape.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: November 5, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Donald C Abbott
  • Patent number: 8563993
    Abstract: A capacitor unit in a display device includes: a capacitor element having a first capacitor electrode connected to a power line and provided in a GM electrode layer and a second capacitor electrode connected to a line and provided in an SD electrode layer; a backup capacitor element having a first backup capacitor electrode provided in the GM electrode layer and a second backup capacitor electrode connected to the power line and provided in the SD electrode layer; a disconnect-able portion at which a connection between the second capacitor electrode and the line can be disconnected; and a connectable portion at which the first backup capacitor electrode and the line can be connected, and the disconnect-able portion and the connectable portion are arranged at a position in which the disconnect-able portion and the connectable portion overlap in a stacking direction.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: October 22, 2013
    Assignee: Panasonic Corporation
    Inventors: Hiroshi Shirouzu, Kenichi Tajika
  • Patent number: 8563435
    Abstract: Methods for reducing electron beam induced damage on semiconductor substrates employ compositions such as small chain organic solvents and non-neutral pH solutions to reduce or eliminate charge imbalances on semiconductor substrates caused by electron beam inspection of the semiconductor substrates. Damage to semiconductor substrates by electron beam inspection processes may also be reduced by generating or otherwise forming passivation films on a semiconductor substrate following electron beam inspection.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: October 22, 2013
    Assignee: Micron Technology, Inc.
    Inventors: David A. Daycock, Paul A. Morgan, Shawn D. Lyonsmith, Curtis R. Olson
  • Publication number: 20130270557
    Abstract: A monitoring method of a semiconductor process includes the following steps. A semiconductor substrate is provided, and a test structure is formed thereon. The method of forming the test structure includes the following steps. A first doped region and a second doped region are formed in the semiconductor substrate, and an insulating layer is formed on the semiconductor substrate. Subsequently, a conductive layer is directly formed on the insulating layer to complete the formation of the test structure, in which the conductive layer in a floating state partially overlaps the first doped region and partially overlaps the second doped region. Then, a voltage signal is applied to the test structure and the breakdown voltage (Vbd) between the first doped region and the second doped region is measured.
    Type: Application
    Filed: April 13, 2012
    Publication date: October 17, 2013
    Inventors: Jian-Bin Shiu, Tung-Sheng Lee
  • Publication number: 20130272027
    Abstract: The present invention provides a method for manufacturing LED light bar, which includes the following steps: (1) providing light-emitting dies of different sizes; (2) measuring luminous intensities of the light-emitting dies; (3) selecting among the light-emitting diodes ones of which the luminous intensities are different from each other by less than 5%; (4) encapsulating the selected ones of the light-emitting dies to form LED lights, which are of substantially identical encapsulated size; and (5) mounting and electrically connecting the LED lights to a printed circuit board to form an LED light bar. The method for manufacturing LED light bar according to the present invention uses light-emitting dies of different sizes so as to improve utilization rate of an entire wafer and effectively reduce the manufacture cost.
    Type: Application
    Filed: April 18, 2012
    Publication date: October 17, 2013
    Applicant: Shenzhen China Star Optoelectronics Technology Co., LTD.
    Inventors: Chechang Hu, Hu He
  • Publication number: 20130267046
    Abstract: A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors.
    Type: Application
    Filed: April 9, 2012
    Publication date: October 10, 2013
    Inventors: Zvi OR-BACH, Deepak C. SEKAR, Brian CRONQUIST
  • Publication number: 20130267045
    Abstract: An apparatus comprises: a shower head having a supply plenum for supplying the gas to the chamber and a vacuum manifold fluidly coupled to the supply plenum; and at least one vacuum system fluidly coupled to the vacuum manifold of the shower head.
    Type: Application
    Filed: April 4, 2012
    Publication date: October 10, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Tsung LEE, Hung Jui CHANG, You-Hua CHOU, Shiu-Ko JANGJIAN, Chung-En KAO, Ming-Chin TSAI, Huan-Wen LAI
  • Publication number: 20130260484
    Abstract: The present disclosure involves a method of fabricating a light-emitting diode (LED) wafer. The method first determines a target surface morphology for the LED wafer. The target surface morphology yields a maximum light output for LEDs on the LED wafer. The LED wafer is etched to form a roughened wafer surface. Thereafter, using a laser scanning microscope, the method investigates an actual surface morphology of the LED wafer. Afterwards, if the actual surface morphology differs from the target surface morphology beyond an acceptable limit, the method repeats the etching step one or more times. The etching is repeated by adjusting one or more etching parameters.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 3, 2013
    Applicant: TSMC Solid State Lighting, Ltd.
    Inventors: Chyi-Shyuan Chern, Hsin-Hsien Wu, Yung-Hsin Yang, Ching-Hua Chiu
  • Patent number: 8546952
    Abstract: A 3D integrated circuit including a first wafer and a second wafer is provided. The first wafer includes a first conduction pattern. The second wafer includes a second conduction pattern which is electrically connected to the first conduction pattern. A displacement between the first wafer and the second wafer is determined by a resistance of the first conduction pattern and the second conduction pattern.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: October 1, 2013
    Assignee: National Chiao Tung University
    Inventors: Kuan-Neng Chen, Shih-Wei Li
  • Patent number: 8541782
    Abstract: Many of the principles of an oxide semiconductor are still unclear and therefore there is no established method for evaluating an oxide semiconductor. Thus, an object is to provide a novel method for evaluating an oxide semiconductor. Carrier density is evaluated, and hydrogen concentration is also evaluated. Specifically, a MOS capacitor (a diode or a triode) is manufactured, and the C-V characteristics of the MOS capacitor are obtained. Then, the carrier density is estimated from the C-V characteristics obtained.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: September 24, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Tatsuya Honda
  • Patent number: 8536670
    Abstract: A semiconductor device includes: a first semiconductor chip; and a second semiconductor chip that is stacked on the first semiconductor chip. The first semiconductor chip includes a first wiring portion of which a side surface is exposed at a side portion of the first semiconductor chip. The second semiconductor chip includes a second wiring portion of which a side surface is exposed at a side portion of the second semiconductor chip. The respective side surfaces of the first wiring portion and the second wiring portion, which are exposed at the side portions of the first semiconductor chip and the second semiconductor chip, are covered by a conductive layer, and the first wiring portion and the second wiring portion are electrically connected to each other through the conductive layer.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: September 17, 2013
    Assignee: Sony Corporation
    Inventors: Ikuo Yoshihara, Taku Umebayashi, Hiroshi Takahashi, Hironobu Yoshida
  • Patent number: 8535968
    Abstract: Provided are novel photovoltaic cell alignment apparatuses and methods for fabricating photovoltaic module sub-assemblies that include multiple aligned photovoltaic cells. The apparatuses and methods provide high-speed precise alignment of the cells with respect to each other and other components of a photovoltaic module. In certain embodiments, a set of photovoltaic cells is first aligned on an alignment plate of an alignment apparatus and then transferred to a sealing sheet of the module such that the respective alignments of the cells are maintained during transfer. The alignment plate may include multiple cell receiving areas that have corresponding alignment edges. Aligning photovoltaic cells on this plate may involve forcing the cells against the alignment edges and/or moving the cells in the receiving areas in a direction parallel to the alignment edges.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: September 17, 2013
    Assignee: Miasole
    Inventors: Bruce Krein, Frank Lema
  • Publication number: 20130228778
    Abstract: A first test structure includes a first isolation region, a first gate electrode over the first isolation region, a first and a second semiconductor fin, and a first contact plug over the first and the second semiconductor fins. A second test structure includes a second isolation region, a second gate electrode over the second isolation region, a third semiconductor fin and a dielectric fin, and a second contact plug over the third semiconductor fin. The first, the second, and the third semiconductor fins and the dielectric fin have substantially a same fin height. A method includes measuring a first capacitance between the first gate electrode and the first contact plug, measuring a second capacitance between the second gate electrode and the second contact plug, and calculating the same fin height from a capacitance difference between the second capacitance and the first capacitance.
    Type: Application
    Filed: March 2, 2012
    Publication date: September 5, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Horn Tsai, Hsiao-Han Liu
  • Patent number: 8508005
    Abstract: A spin-transfer torque memory unit includes a free magnetic layer having a magnetic easy axis; a reference magnetic element having a magnetization orientation that is pinned in a reference direction; an electrically insulating and non-magnetic tunneling barrier layer separating the free magnetic layer from the magnetic reference element; and a compensation element adjacent to the free magnetic layer. The compensation element applies a bias field on the magnetization orientation of the free magnetic layer. The bias field is formed of a first vector component parallel to the easy axis of the free magnetic layer and a second vector component orthogonal to the easy axis of the free magnetic layer. The bias field reduces a write current magnitude required to switch the direction of the magnetization orientation of the free magnetic layer.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: August 13, 2013
    Assignee: Seagate Technology LLC
    Inventors: Kaizhong Gao, Haiwen Xi, Wenzhong Zhu, Olle Heinonen
  • Patent number: 8507908
    Abstract: A probe comprises: contact parts to be electrically connected to input/output terminals of an IC device built in a semiconductor wafer under test; interconnect parts at the front ends of which the contact parts are provided; a plurality of beam parts on the top surface of which the interconnect parts are provided along the longitudinal direction; and a base part supporting the plurality of beam parts all together in a cantilever fashion, the beam parts are supported by the base part at a rear end region of the beam parts, and grooves are provided between the adjoining beam parts in the rear end region.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: August 13, 2013
    Assignee: Advantest Corporation
    Inventor: Koichi Wada
  • Patent number: 8505481
    Abstract: In certain desirable embodiments, the present invention relates to the use of 15N isotopes into GaAsN, InAsN or GaSbN films for ion beam analysis. A semiconductor-nitride assembly for growing and analyzing crystal growth in a group III-V semiconductor sample that includes: a substrate; a buffer layer deposited on the substrate, a nitrogen gas injector to incorporate enriched nitrogen gas and the nitrogen gas injector includes a concentration of enriched nitrogen gas, a thin film consisting of at least one group III element containing compound where at least one group III element is covalently bonded with the nitrogen in the presence of the same or different group V element of the buffer layer, and a proton beam to analyze the incorporation of the nitrogen gas in the thin film layer is described.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: August 13, 2013
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Stefan P Svensson, John D Demaree
  • Patent number: 8507297
    Abstract: A wafer containing a plurality of electro-optical devices, each device being enclosed in chamber that has a translucent cover. An X-Y matrix of pairs of interconnections on the wafer are connected to the circuitry of the electro-optical devices for addressing the electro-optical devices. The pairs of interconnections extend outside of the chambers enclosing the devices to testing areas on the periphery of the wafer. Testing is done by signals applied through the interconnections while simultaneously exposing the devices to light through the translucent covers.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: August 13, 2013
    Assignee: Spatial Photonics, Inc.
    Inventors: Shaoher X. Pan, Vlad Novotny
  • Publication number: 20130193573
    Abstract: Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. To avoid warpage, the tensile stress of a conductive layer deposited onto a GaAs substrate can be offset by depositing a compensating layer having negative stress over the GaAs substrate. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.
    Type: Application
    Filed: January 27, 2012
    Publication date: August 1, 2013
    Applicant: SKYWORKS SOLUTIONS, INC.
    Inventor: Hong Shen
  • Patent number: 8487294
    Abstract: A nanostructure quick-switch memristor includes an upper electrode, a lower electrode and three layers of nanomembrane provided between the upper electrode and the lower electrode. The three layers of nanomembrane consist of an N-type semiconductor layer, a neutral semiconductor layer on the N-type semiconductor layer, and a P-type semiconductor layer on the neutral semiconductor layer. The nanostructure quick-switch memristor of the present invention has the quick switching speed, simple manufacturing method, and low manufacturing cost.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: July 16, 2013
    Assignee: Heilongjiang University
    Inventors: Dianzhong Wen, Xiaohui Bai
  • Publication number: 20130175527
    Abstract: A sensor arrangement is provided, the sensor arrangement including a chip including a sensor circuit configured to detect a bending of the chip; and a package structure configured to protect the chip; wherein the package structure includes a first region and a second region, and wherein the package structure is configured such that it is easier to be deformed in the first region than in the second region.
    Type: Application
    Filed: January 9, 2012
    Publication date: July 11, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Horst Theuss, Klaus Elian
  • Patent number: 8481345
    Abstract: A method reconstructs the charge collection from regions beneath opaque metallization of a semiconductor device, as determined from focused laser charge collection response images, and thereby derives a dose-rate dependent correction factor for subsequent broad-area, dose-rate equivalent, laser measurements. The position- and dose-rate dependencies of the charge-collection magnitude of the device are determined empirically and can be combined with a digital reconstruction methodology to derive an accurate metal-correction factor that permits subsequent absolute dose-rate response measurements to be derived from laser measurements alone. Broad-area laser dose-rate testing can thereby be used to accurately determine the peak transient current, dose-rate response of semiconductor devices to penetrating electron, gamma- and x-ray irradiation.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: July 9, 2013
    Assignee: Sandia Corporation
    Inventor: Kevin M. Horn
  • Patent number: 8476659
    Abstract: The present disclosure relates to methods for performing wafer-level measurement and wafer-level binning of LED devices. The present disclosure also relates to methods for reducing thermal resistance of LED devices. The methods include growing epitaxial layers consisting of an n-doped layer, an active layer, and a p-doped layer on a wafer of a growth substrate. The method further includes forming p-contact and n-contact to the p-doped layer and the n-doped layer, respectively. The method further includes performing a wafer-level measurement of the LED by supplying power to the LED through the n-contact and the p-contact. The method further includes dicing the wafer to generate diced LED dies, bonding the diced LED dies to a chip substrate, and removing the growth substrate from the diced LED dies.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: July 2, 2013
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Hsing-Kuo Hsia, Hung-Weng Huang, Ching-Hua Chiu, Gordon Kuo
  • Publication number: 20130166248
    Abstract: A method and apparatus for estimating a height of an epitaxially grown semiconductor material in other semiconductor devices. The method includes epitaxially growing first, second, and third portions of semiconductor material on a first semiconductor device, measuring a height of the third portion of semiconductor material and a height of the first or second portion of semiconductor material, measuring a first saturation current through the first and second portions of semiconductor material, measuring a second saturation current through the first and third portions of semiconductor material, and preparing a model of the first saturation current relative to the height of the first or second portion of semiconductor material and the second saturation current relative to an average of the height of the first and third portions of semiconductor material. The model is used to estimate the height of an epitaxially grown semiconductor material in the other semiconductor devices.
    Type: Application
    Filed: December 23, 2011
    Publication date: June 27, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Sheng Chang, Chia-Cheng Ho, Yi-Tang Lin
  • Publication number: 20130146872
    Abstract: A semiconductor device has a semiconductor die and conductive pillar with a recess or protrusion formed over a surface of the semiconductor die. The conductive pillar is made by forming a patterning layer over the semiconductor die, forming an opening with a recess or protrusion in the patterning layer, depositing conductive material in the opening and recess or protrusion, and removing the patterning layer. A substrate has bump material deposited over a conductive layer formed over a surface of the substrate. The bump material is melted. The semiconductor die is pressed toward the substrate to enable the melted bump material to flow into the recess or over the protrusion if the conductive pillar makes connection to the conductive layer. A presence or absence of the bump material in the recess or protrusion of the conductive pillar is detected by X-ray or visual inspection.
    Type: Application
    Filed: December 13, 2011
    Publication date: June 13, 2013
    Applicant: STATS ChipPAC, LTD.
    Inventors: Jen Yu Chen, Ting Yu Fu, Men Hsien Li, Chien Chen Lee
  • Patent number: 8460947
    Abstract: A fluid ejection device includes one or more digital data storage arrays having plural EPROM cells. A method for affirming performance adequacy of EPROM cells in the one or more arrays includes the steps of identifying a reference cell in each array, measuring a selected performance criterion for the reference cells, obtaining a reference criterion value, and evaluating the actual performance of at least one cell in each array with respect to the reference criterion value.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: June 11, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Stan E Leigh, Kevin Bruce, Joseph M Torgerson, Trudy Benjamin
  • Patent number: 8450125
    Abstract: A method of evaluating an epitaxial growing process includes forming a mold layer on each of a plurality of substrates, forming a photoresist pattern on each mold layer, the photoresist pattern having opening portions, a total area of a bottom portion of the opening portions being different for each substrate, patterning each mold layer to expose a surface portion of the substrate to form an evaluation pattern on each substrate, evaluation patterns including opening portions corresponding to the opening portion in the photoresist pattern, determining substrate opening ratios for each substrate based on the opening portions in the evaluation pattern thereon, the substrate opening ratios being different for each substrate, performing a selective epitaxial process on each substrate to form an epitaxial layer, and evaluating characteristics of the epitaxial layer for each substrate to determine an optimal substrate opening ratio.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: May 28, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Suk Shin, Yong-Joo Lee, Dong-Hyuk Kim, Myung-Sun Kim, Hoi-Sung Chung
  • Publication number: 20130127059
    Abstract: A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component.
    Type: Application
    Filed: November 17, 2011
    Publication date: May 23, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Lai, Ming-Che Ho, Tzong-Hann Yang, Chien Rhone Wang, Chia-Tung Chang, Hung-Jui Kuo, Chung-Shi Liu
  • Patent number: 8445296
    Abstract: Methods and apparatus for performing end point determination. A method includes receiving a wafer into an etch tool chamber for performing an RIE etch; beginning the RIE etch to form vias in the wafer; receiving in-situ measurements of one or more physical parameters of the etch tool chamber that are correlated to the RIE etch process; providing a virtual metrology model for the RIE etch in the chamber; inputting the received in-situ measurements to the virtual metrology model for the RIE etch in the chamber; executing the virtual metrology model to estimate the current via depth; comparing the estimated current via depth to a target depth; and when the comparing indicates the current via depth is within a predetermined threshold of the target depth; outputting a stop signal. An apparatus for use with the method embodiment is disclosed.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: May 21, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Rhone Wang, Tzu-Cheng Lin, Yu-Jen Cheng, Chih-Wei Lai, Hung-Pin Chang, Tsang-Jiuh Wu
  • Patent number: 8445295
    Abstract: An electrical characteristics test for a semiconductor integrated circuit using a Kelvin contact method can be conducted in a pre-process without obstructing the reduction in size of a semiconductor chip or without complicating the circuit design. A probe card in a testing apparatus includes probes for Kelvin contact, the probes for Kelvin contact including a coil probe and a POGO pin probe disposed inside the coil probe, and a probe for two-terminal measurement. Electrode pads formed in each chip area over a wafer are in a relation of A=B<2A, given that the area of one of the electrode pads with which the probe for Kelvin contact comes into contact is B and the area of the other electrode pad with which the probe for two-terminal measurement comes into contact is A.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: May 21, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Akio Shibuya, Katsuyoshi Tsuchiya, Akira Imaizumi, Hiroshi Matsumoto, Shoji Tsuchioka
  • Patent number: 8436454
    Abstract: The present invention is directed to a system that programmably interconnects integrated circuit chips and other components at near-intra-chip density. The system's contact structure allows it to adapt to components with a wide variety of contact spacings and interconnection requirements, the use of releasable attachment means allows component placement to be modified as needed, the system identifies the contacts and the components to facilitate specifying the inter-component connections, and the system provides signal conditioning and retiming to minimize issues with signal integrity and signal skew.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: May 7, 2013
    Inventor: Richard Norman
  • Publication number: 20130105762
    Abstract: A nitride semiconductor light-emitting device includes a support base and a diode structure. The support base has a primary surface of a hexagonal nitride semiconductor. The diode structure is provided on the primary surface of the support base. The diode structure includes a first conductivity type group-III nitride semiconductor layer provided on the primary surface of the support base, a light-emitting layer provided on the first conductivity type group-III nitride semiconductor layer, and a second conductivity type group-III nitride semiconductor layer provided on the light-emitting layer. The light-emitting layer has a multiple quantum well structure including first and second well layers and a barrier layer. The thickness of the barrier layer is 4.5 nm or less. The primary surface of the support base tilts at a tilt angle in the range of 50 to 80 degrees or 130 to 170 degrees from a c-plane of the hexagonal nitride semiconductor.
    Type: Application
    Filed: August 17, 2012
    Publication date: May 2, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takashi KYONO, Yohei ENYA, Masaki UENO
  • Patent number: 8420498
    Abstract: An alignment method of chips that are formed on a surface of a semiconductor wafer with alignment marks corresponding to the chips includes the steps of irradiating an alignment mark corresponding to a predetermined alignment chip in a predetermined area including the chips with a laser light; detecting reflected waves from the alignment mark of the predetermined alignment chip to obtain a position of the alignment mark of the predetermined alignment chip; irradiating an alignment mark of an alternative chip different from the predetermined alignment chip with the laser light in case of not being able to obtain the position of the alignment mark of the predetermined alignment chip; obtaining a position of the alignment mark of the alternative chip by detecting the reflected waves from the alignment mark of the alternative chip; and aligning the chips in the predetermined area based on positions of alignment marks including the position of the alignment mark of the alternative chip.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: April 16, 2013
    Assignee: Mitsumi Electric Co., Ltd.
    Inventor: Yukihiro Tanemura
  • Patent number: 8423942
    Abstract: A fill-placement method, according to which symmetrical fill patterns are used to insert fill tiles into one or more interconnect levels corresponding to symmetrical circuitry. The fill-placement method can be used, for example, in the fabrication of an integrated circuit having at least two complementary portions for which relatively tight circuit-matching requirements need to be met.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: April 16, 2013
    Assignee: Agere Systems LLC
    Inventor: Jason K. Werkheiser
  • Publication number: 20130082257
    Abstract: Method form via chain and serpentine/comb test structures in kerf areas of a wafer. The via chain test structures comprise a first via chain and a second via chain in a first kerf area. The via chain test structures are formed such that geometrically shaped portions of the first via chain and geometrically shaped portions of the second via chain alternate along the length of the first kerf area. The methods perform relatively low (first) magnification testing to identify a defective geometrically shaped portion that contains a defective via structure. The methods then perform relatively high (second) magnification testing only within the defective geometrically shaped portion. The first magnification testing is performed at a lower magnification relative to the second magnification testing.
    Type: Application
    Filed: October 3, 2011
    Publication date: April 4, 2013
    Applicants: ST MICROELECTRONICS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahierathan Balasingham, Christopher B. D'Aleo, Gregory M. Johnson, Muthukumarasamy Karthikeyan, Shenzhi Yang
  • Publication number: 20130084661
    Abstract: A wafer-level optical deflector assembly is formed on a front surface side of a wafer. Then, the front surface side of the wafer is etched by using elements of the wafer-level optical deflector assembly, to form a front-side dicing street. Then, a transparent substrate with an inside cavity is adhered to the front surface side of the wafer. Then, a second etching mask is formed on a back surface side of the wafer. Then, the back surface side of the wafer is etched to create a back-side dicing street. Then, an adhesive sheet with a ring-shaped rim is adhered to the back surface side of the wafer. Then, the transparent substrate is removed. Finally, the ring-shaped rim is expanded to widen the front-side dicing street and the back-side dicing street to pick up optical deflectors one by one from the wafer.
    Type: Application
    Filed: September 13, 2012
    Publication date: April 4, 2013
    Applicant: STANLEY ELECTRIC CO., LTD.
    Inventor: Yoshiaki YASUDA
  • Publication number: 20130084657
    Abstract: A first embodiment is a method for semiconductor processing. The method comprises forming a component on a wafer in a chamber; determining a non-uniformity of the plasma in the chamber, the determining being based at least in part on the component on the wafer; and providing a material on a surface of the chamber corresponding to the non-uniformity. The forming the component includes using a plasma. The material can have various shapes, compositions, thicknesses, and/or placements on the surface of the chamber. Other embodiments include a chamber having a material on a surface to control a plasma uniformity.
    Type: Application
    Filed: September 29, 2011
    Publication date: April 4, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Sheng Wu, Fei-Fan Chen, Chia-I Shen, Hua-Sheng Chiu
  • Patent number: 8409967
    Abstract: A method for manufacturing semiconductor chips from a semiconductor wafer, including the steps of: fastening, on a first support frame, a second support frame having outer dimensions smaller than the outer dimensions of the first frame and greater than the inner dimensions of the first frame; arranging the wafer on a surface of a film stretched on the second frame; carrying out wafer processing operations by using equipment capable of receiving the first frame; separating the second frame from the first frame and removing the first frame; and carrying out wafer processing operations by using equipment capable of receiving the second frame.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: April 2, 2013
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Vincent Jarry, Patrick Hougron, Dominique Touzet, José Mendez
  • Publication number: 20130075725
    Abstract: A semiconductor wafer has a die area and a scribe area. A first dummy pad is formed in a first test line area of the scribe area and filled with a first material as part of a first metal layer. A first interlayer dielectric is formed over the first metal layer. A first interconnect pattern is formed in the die area and above the first interlayer dielectric, and a first trench pattern is formed in the first test line area of the scribe area and above the interlayer dielectric. The first interconnect pattern and the first trench pattern are filled with a second metal layer, and the first trench pattern is aligned above the first dummy pad. An enhanced test line structure including the first trench pattern and the first dummy pad is formed and probed in a back end of line (BEOL) process.
    Type: Application
    Filed: September 27, 2011
    Publication date: March 28, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jiun-Jie Huang, Chi-Yen Lin, Ling-Sung Wang
  • Publication number: 20130071957
    Abstract: Methods and systems for predicting semiconductor device performance criteria during processing. A method is described that includes receiving a semiconductor wafer; performing semiconductor processing on the semiconductor wafer forming active devices that, when completed, will exhibit a device performance criteria; during the semiconductor processing, measuring in line at least one device performance criteria related physical parameter; projecting an estimated value for the device performance criteria of the active devices using the at least one in line measurement and using estimated measurements for device performance criteria related physical parameters corresponding to later semiconductor processing steps; comparing the estimated value for the device performance criteria to an acceptable range; and determining, based on the comparing, whether the active devices on the semiconductor wafer will have a device performance criteria within the acceptable range.
    Type: Application
    Filed: September 16, 2011
    Publication date: March 21, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Pan Wang, Chao-Chi Chen, Yaling Huang
  • Patent number: 8399891
    Abstract: An active device array substrate and a fabricating method thereof are provided. A first patterned conductive layer including separated scan line patterns is formed on a substrate. Each scan line pattern includes a first and second scan lines adjacent to each other. Both the first and the second scan lines have first and second contacts. An open inspection on the scan line patterns is performed. Channel layers are formed on the substrate. A second patterned conductive layer including data lines interlaced with the first and second scan lines, sources and drains located above the channel layers, and connectors is formed on the substrate. The sources electrically connect the data lines correspondingly. At least one of the connectors electrically connects the first and second scan lines, so as to form a loop in each scan line pattern. Pixel electrodes electrically connected to the drains are formed.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: March 19, 2013
    Assignee: Au Optronics Corporation
    Inventors: Po-Lin Lai, Ying-Fa Huang, Chun-Ming Yang, Wen-Bin Wu, Wen-Yi Lin
  • Patent number: 8394719
    Abstract: System and method for implementing multi-resolution advanced process control (“APC”) are described. One embodiment is a method including obtaining low resolution metrology data and high resolution metrology data related to a process module for performing a process on the wafer. A process variable of the process is modeled as a function of the low resolution metrology data to generate a low-resolution process model and the process variable is modeled as a function of the high resolution metrology data to generate a high-resolution process model.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: March 12, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Andy Tsen, Jin-Ning Sung, Po-Feng Tsai, Jong-I Mou, Yen-Wei Cheng
  • Publication number: 20130059403
    Abstract: An apparatus is provided for measuring a substrate temperature during an etching process, comprising: one or more windows formed in a substrate supporting surface; a first signal generator configured to pulse a first signal; and a first sensor positioned to receive energy transmitted from the first signal generator through the one or more windows. A method is provided for measuring a substrate temperature during an etching process comprising: heating a substrate using radiant energy; pulsing a first light; determining a metric indicative of total transmittance through the substrate when the first light is pulsed on; determining a metric indicative of background transmittance through the substrate when the first light is pulsed off; and determining a process temperature.
    Type: Application
    Filed: June 30, 2012
    Publication date: March 7, 2013
    Applicant: Applied Materials, Inc.
    Inventors: Jared Ahmad Lee, Jiping Li
  • Publication number: 20130059402
    Abstract: In a method for producing a semi-conductor module (10) comprising at least two semi-conductor chips (12, 14) and an interposer (20) which has electrically conductive structures (28) connecting the semi-conductor chips (12, 14) to one another, the interposer (20) is printed directly onto a first (12) of the semi-conductor chips. When the interposer (20) is printed on, the electrically conductive structures (28) are produced by means of electrically conductive ink (68). The second semi-conductor chip (14) is mounted on the interposer (20) such that the two semi-conductor chips (12, 14) are arranged one above the other and that the interposer (20) forms an intermediate layer between the two semi-conductor chips (12, 14).
    Type: Application
    Filed: February 22, 2011
    Publication date: March 7, 2013
    Inventors: Andreas Jakob, Thomas Kaiser
  • Publication number: 20130056872
    Abstract: A method includes placing a plurality of bottom units onto a jig, wherein the plurality of bottom units is not sawed apart and forms an integrated component. Each of the plurality of bottom units includes a package substrate and a die bonded to the package substrate. A plurality of upper component stacks is placed onto the plurality of bottom units, wherein solder balls are located between the plurality of upper component and the plurality of bottom units. A reflow is performed to join the plurality of upper component stacks with respective ones of the plurality of bottom units through the solder balls.
    Type: Application
    Filed: September 2, 2011
    Publication date: March 7, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Juin Liu, Chita Chuang, Ching-Wen Hsiao, Chen-Shien Chen, Chen-Cheng Kuo, Chih-Hua Chen
  • Publication number: 20130056880
    Abstract: An assembly has at least one integrated circuit (IC) die fixed in a medium. The assembly has a redistribution layer over the IC die. The redistribution layer has conductors connecting first pads on active faces of the IC die to second pads at an exposed surface of the assembly. A die unit is provided over the IC die. The die unit has a bottom die interconnected to a package substrate. Respective portions of the redistribution layer corresponding to each of the at least one IC die partially underlie the bottom die, and extend beyond the bottom die. The package substrate has contacts connected to the ones of the second pads corresponding to the at least one IC die.
    Type: Application
    Filed: September 1, 2011
    Publication date: March 7, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Ding WANG, Chien-Hsiun Lee
  • Publication number: 20130052760
    Abstract: In an exemplary method of inspecting a stack chip package, a first chip is prepared. The first chip includes a through-silicon via, first pad electrodes connected to the through-silicon via and probe pad electrodes connected to the through-silicon via. A testing chip is prepared. The testing chip includes second pad electrodes that are arranged to correspond with the first pad electrodes. The testing chip is temporarily adhered to the first chip such that the second pad electrodes are electrically connected to the first pad electrode respectively, to form a stack structure wherein the probe pad electrodes are exposed to for testing. An electrical signal is applied to the exposed probe pad electrodes to test the through-silicon via included in the first chip.
    Type: Application
    Filed: July 10, 2012
    Publication date: February 28, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Dong CHO, Yeong-Lyeol PARK, Min-Seung YOON
  • Publication number: 20130049029
    Abstract: An organic light-emitting display device includes a gate electrode, a source electrode, and a drain electrode on a substrate, a gate interconnection line connected to the gate electrode, a source and drain interconnection line connected to the source and drain electrodes, a first test pad electrically connected to the source and drain interconnection line, and a second test pad electrically connected to the gate interconnection line. The second test pad is at a same level as the first test pad, and the gate electrode is on a different layer than the source and drain electrodes.
    Type: Application
    Filed: March 13, 2012
    Publication date: February 28, 2013
    Inventors: Kwang-Hae KIM, Jae-Beom Choi, Kwan-Wook Jung, June-Woo Lee
  • Publication number: 20130049788
    Abstract: A semiconductor device comprises a plurality of transistor mismatch circuits formed on a semiconductor wafer; and a characterization circuit formed on the semiconductor wafer. The characterization circuit is coupled to receive input provided by the absolute value circuits simultaneously which themselves receive inputs from the mismatch circuits simultaneously and is configured to output a standard deviation of mismatch between transistors in the mismatch circuits.
    Type: Application
    Filed: August 31, 2011
    Publication date: February 28, 2013
    Inventors: COLIN C. MCANDREW, BRANDT BRASWELL
  • Patent number: 8375558
    Abstract: A semiconductor apparatus includes a semiconductor chip through-line for transmitting signals commonly to a plurality of stacked semiconductor chips. The apparatus includes a first test pulse signal transmission unit configured to transmit a first test pulse signal to a first end of the semiconductor chip through-line when a power-up operation is performed; a second test pulse signal transmission unit configured to transmit a second test pulse signal to a second end of the semiconductor chip through-line after the first test pulse signal is transmitted; a first signal reception unit coupled to the first end of the semiconductor chip through-line, and configured to receive signals transmitted from the first and second test pulse signal transmission units; and a second signal reception unit coupled to the second end of the semiconductor chip through-line, and configured to receive the signals transmitted by the first and second test pulse signal transmission units.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: February 19, 2013
    Assignee: SK Hynix Inc.
    Inventors: Tae Sik Yun, Won Woong Seok