Abstract: Methods for making and testing a semiconductor device with through substrate vias are described. In some examples, a method of making a semiconductor device includes: forming through substrate vias (TSVs) in a substrate having an integrated circuit (IC) die, the substrate including an active side and a backside, the active side having conductive interconnect formed thereon, the TSVs including exposed portions on the backside of the substrate; patterning first metal on the active side of the substrate to electrically couple the TSVs to a portion of the conductive interconnect; and coupling the exposed portions of the TSVs on the backside of the substrate to electrically couple together the plurality of TSVs.

Abstract: Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region.

Abstract: A rule-based method of optimizing wire bonding jumps is disclosed which minimizes the amount of wire used for wire bonds and/or minimizes a number of power and ground pads on a substrate to support all wired connections.

Abstract: A method for forming a semiconductor device can include electrically testing a plurality of semiconductor dies in wafer form subsequent to performing a first wafer dicing process, then performing a second wafer dicing process to dice the wafer and to singularize the plurality of semiconductor dies. Electrically testing the plurality of semiconductor dies in wafer form subsequent to the first dicing process can identify chips damaged during the first dicing process. The method can also include forming a plurality of grooves between adjacent dies which leaves a full wafer thickness at a perimeter of the wafer to result in a wafer which is more resistant to deflection and damage during handling.

Abstract: A method of manufacturing a stacked semiconductor package in which a plurality of semiconductor chips are stacked includes preparing a first semiconductor chip including a first semiconductor device, a first penetration electrode, and a first connection unit electrically connected to the first semiconductor device or the first penetration electrode, attaching the first semiconductor chip to a base substrate with the first connection unit interposed therebetween, forming a first rewiring pattern and a first protection layer on the first semiconductor chip by using a printing method, wherein the first rewiring pattern is electrically connected to the first penetration electrode and the first protection layer partially covers the first rewiring pattern and exposes other portions of the first rewiring pattern, and attaching a second semiconductor chip including a second semiconductor device to the first semiconductor chip to electrically connect the second semiconductor device to the first rewiring pattern.

Abstract: Provided are a wafer level package in which a communication line can be readily formed between an internal device and the outside of the package, and a method of fabricating the wafer level package. The wafer level package includes a first substrate having a cavity in which a first internal device is disposed, an Input/Output (I/O) pad formed on the first substrate and electrically connected with the first internal device, a second substrate disposed over the first substrate and from which a part corresponding to the I/O pad is removed, and a solder bonding the first and second substrates. According to the wafer level package and the method of fabricating the same, upper and lower substrates are sawed to different cutting widths, or a hole is formed in the upper substrate, such that a communication line of an internal device can be readily formed without a via process which penetrates a substrate.

Abstract: An organic EL device is provided and, in particular, a top-emission-type organic EL device, which can maintain excellent light emission efficiency over a prolonged period of time. The organic EL device includes a substrate; and an organic EL element that is formed on the substrate and that includes a lower electrode, an organic EL layer, an upper electrode, and a protective layer. The protective layer includes at least one inorganic film provided that at least one film thereof is a SiN:H film having a stretching-mode peak area ratio, as determined by infrared absorption spectrum measurements, of N—H bonds to Si—N bonds that is greater than 0.06 but does not exceed 0.1, and having a stretching-mode peak area ratio, as determined by infrared absorption spectrum measurements, of Si—H bonds to Si—N bonds that is greater than 0.12 but does not exceed 0.17.

Abstract: A packaging technology for silicon chips is similar to ball grid array packaging technology of the prior art without, however, the use of printed board substrate of the prior art Instead pins are used that are part of a planar frame, the pins folded to a position 90 degrees from the plane of the frame, after which the frame is disposed in contact with the chip, pads on the frame and the chip are connected, and then entire assembly is then encapsulated. The edges of the frame are then cut off, leaving the encapsulation to maintain the configuration of the package in place.

Abstract: Provided is a light emitting device fabricating apparatus, which includes a light emitting device, first and second contact parts, a power source part, a loading plate, and a chamber. The first and second contact parts are connected to the light emitting device to apply a first current to the light emitting device. The power source part supplies power to the first and second contact parts. The loading plate supports and heats the light emitting device. The chamber accommodates the light emitting device, the first and second contact parts, and the loading plate, and has a vacuum state or oxygen atmosphere.

Abstract: It is an object of the present invention to provide a doping apparatus, a doping method, and a method for fabricating a thin film transistor that can carry out doping to the carrier concentration which is optimum for obtaining the desired electric characteristic non-destructively and in an easy manner. In accordance with the present invention, an electric characteristic of a semiconductor element (threshold voltage in a transistor and the like) is correctly and precisely monitored by using a contact angle, and is controlled by controlling a doping method. In addition, the present invention can be momentarily acquired information by in-situ monitoring the characteristic and can be fed back without a time lag.

Abstract: A method for reclamation of scrap materials during the formation of Group III-V materials by metal-organic chemical vapor deposition (MOCVD) processes and/or hydride vapor phase epitaxial (HVPE) processes is provided. More specifically, embodiments described herein generally relate to methods for repairing or replacing defective films or layers during the formation of devices formed by these materials. By periodic testing of the layers during the formation process, low-quality layers that may result in low-quality or defective devices may be detected prior to completion of the device. These low-quality layers may be partially or completely removed and redeposited to reclaim the substrate and any remaining high-quality layers that were previously deposited under the low-quality layer.

Abstract: a 4D device comprises a 2D multi-core logic and a 3D memory stack connected through the memory stack sidewall using a fine pitch T&J connection. The 3D memory in the stack is thinned from the original wafer thickness to no remaining Si. A tounge and groove device at the memory wafer top and bottom surfaces allows an accurate stack alignment. The memory stack also has micro-channels on the backside to allow fluid cooling. The memory stack is further diced at the fixed clock-cycle distance and is flipped on its side and re-assembled on to a template into a pseudo-wafer format. The top side wall of the assembly is polished and built with BEOL to fan-out and use the T&J fine pitch connection to join to the 2D logic wafer. The other side of the memory stack is polished, fanned-out, and bumped with C4 solder. The invention also comprises a process for manufacturing the device.

Abstract: In a display apparatus and a method of manufacturing the display apparatus, a gate line, a data line, and a plurality of layers are formed on an array substrate on which a pixel area, a pad area, and a peripheral area are defined. During the forming processes of the gate line, the data line, and the layers, the gate line and the data line are partially exposed in the peripheral area, or contact portions formed on the gate line and the data line in the peripheral area are exposed. Thus, the gate line and the data line may be tested using the contact portions as electrical terminals during the manufacturing process of the display apparatus.

Abstract: The present invention concerns methods for producing photovoltaic material and a device able to exploit high energy photons. The photovoltaic material is obtained from a conventional photovoltaic material having a top surface intended to be exposed to photonic radiation, having a built-in P-N junction delimiting an emitter part and a base part and comprising at least one area or region specifically designed, treated or adapted to absorb high energy or energetic photons, located adjacent or near at least one hetero-interface. According to the invention, this material is subjected to treatments resulting in the formation of at least one semiconductor based metamaterial field or region being created, as a transitional region of the or a hetero-interface, in an area located continuous or proximate to the or an absorption area or region for the energetic photons of the photonic radiation impacting said photovoltaic material.

Abstract: Semiconductor process evaluation methods perform multiple scans of a test semiconductor substrate (e.g., test wafer) using ion beams under different ion implanting conditions. Parameters of the test semiconductor substrate that was scanned using the ion beams under different ion implanting conditions are then measured to conduct the semiconductor process evaluation.

Abstract: Various embodiments of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, a semiconductor apparatus may include a chip, scribe lanes disposed around the chip, and a probe test logic circuit for conducting a probe test on the chip. The probe test logic circuit is disposed on a portion of the scribe lanes.

Abstract: A method and system for tracing die at unit level, comprising: assigning a first identification to a support member including a plurality of die support units; generating a second identification corresponding to a die support unit, the second identification including the first identification and a coordinate of the die support unit within the support member; correlating the second identification to a third identification of a die; attaching the die to the die support unit to generate a packaged die; and assigning the second identification to the packaged die.

Abstract: A method for forming a light emitting device includes providing a light emitting diode (LED) configured to emit light of a first color and providing a plurality of semi-spherical lenses made of a silicone material that contains no phosphor material. Each of the lenses has a layer of phosphor material attached thereto. The method also includes testing the plurality of lenses to select a subset of lenses that converts light of the first color to light of a second color. The method further includes forming the light emitting device using the LED, one of the selected subset of lenses, and a heat conductive substrate. In an embodiment, after the testing of the plurality of lenses, one of the selected subset of lenses is disposed overlying the LED. In another embodiment, the testing of the plurality of lenses is conducted with a light source other than the LED.

Abstract: A serpentine double gated diode array for monitoring stress induced defects is disclosed. The diode array is configured with adjacent gate segments and gate loops in close proximity to active areas to maximize a sensitivity to stress induced defects. The diode array is compatible with conventional electrical testing. Scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM) may be used to isolate individual stress induced defects. Variations in the gate configuration allow estimation of effects of circuit layout on formation of stress induced defects.

Abstract: Computer-implemented methods that include correlating a backside defect with a frontside defect detected on a specimen are provided. The defects are correlated if a portion of the backside defect on the backside of the specimen is opposite to a portion of the frontside defect on the frontside of the specimen. In particular, the defects are correlated if the portion of the backside defect is aligned with the portion of the frontside defect along an axis perpendicular to the frontside and the backside of the specimen. The method may also include altering a parameter of a process tool in response to the backside defect to reduce frontside defects on additional specimen processed in the process tool. Computer-implemented methods for analyzing data representing spatial characteristics of backside defects detected on a specimen to classify the backside defects are also provided. Analyzing the data may include spatial signature analysis of the data.

Abstract: A semiconductor device fabrication method can improve yield of semiconductor devices and decrease (or prevent) waste of non-defective semiconductor chips. This fabrication method has a step of performing characteristic inspection after packaging a semiconductor chip every time a semiconductor chip layer is formed. The fabrication method makes another semiconductor chip layer on this semiconductor chip layer only when the inspection indicates that the semiconductor chip is a non-defective product.

Abstract: Methods are disclosed for monitoring the amount of metal contamination imparted during wafer processing operations such as polishing and cleaning. The methods include subjecting a silicon-on-insulator structure to the semiconductor process, precipitating metal contamination in the structure and delineating the metal contaminants.

Abstract: The present invention relates to a method and system for testing integrity of a passivation layer (108) covering a semiconductor device. A structured layer of electrically conducting material (104) is deposited onto at least a portion of a top surface of a substrate (102) of the semiconductor device. The structured layer (104) comprises a plurality of bands (104.1, 104.2) connected to at least two contacts (106.1, 106.2) and disposed on the at least a portion of the top surface such that one of consecutive bands (104.1, 104.2) and consecutive portions of the bands (104.1, 104.2) are connected to different contacts (106.1, 106.2). A passivation layer (108) is deposited onto the at least a portion of the top surface of the substrate (102) and the structured layer (104) such that material of the passivation layer(108) is disposed between the bands of conducting material (104.1, 104.2) and on top of the structured layer (104).

Abstract: A method for polishing a substrate having a metal film thereon is described. The substrate has metal interconnects formed from part of the metal film. The polishing method includes performing a first polishing process of removing the metal film, after the first polishing process, performing a second polishing process of removing the barrier film, after the second polishing process, performing a third polishing process of polishing the insulating film. During the second polishing process and the third polishing process, a polishing state of the substrate is monitored with an eddy current sensor, and the third polishing process is terminated when an output signal of the eddy current sensor reaches a predetermined threshold.

Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.

Abstract: By providing a protective layer in an intermediate manufacturing stage, an increased surface protection with respect to particle contamination and surface corrosion may be achieved. In some illustrative embodiments, the protective layer may be used during an electrical test procedure, in which respective contact portions are contacted through the protective layer, thereby significantly reducing particle contamination during a respective measurement process.

Abstract: A method and apparatus is provided for use in an integrated circuit or printed circuit board for reducing or minimizing interference. An inductance is formed using two or more inductors coupled together and configured such that current flows through the inductors in different directions, thus at least partially canceling magnetic fields. When designing a circuit, the configuration of the inductors, as well as the relative positions of portions of the circuit, can be tweaked to provide optimal interference or noise control.

Abstract: Semiconductor wafer inspection device comprising a wager transport arm provided with at least one wafer support element, a wafer gripper, the gripper having two distant branches designed to take hold of the opposed edges of the wafer, the gripper being mounted so as to rotate on a shaft in order to be able to rotate the wafer between an approximately horizontal position and an approximately vertical position, and at least two inspection systems placed on one side of the wafer and on the other, in an approximately vertical position symmetrically with respect to the plane passing through the wafer.

Abstract: In certain desirable embodiments, the present invention relates to the use of 15N isotopes into GaAsN, InAsN or GaSbN films for ion beam analysis. A semiconductor-nitride assembly for growing and analyzing crystal growth in a group III-V semiconductor sample that includes: a substrate; a buffer layer deposited on the substrate, a nitrogen gas injector to incorporate enriched nitrogen gas and the nitrogen gas injector includes a concentration of enriched nitrogen gas, a thin film consisting of at least one group III element containing compound where at least one group III element is covalently bonded with the nitrogen in the presence of the same or different group V element of the buffer layer, and a proton beam to analyze the incorporation of the nitrogen gas in the thin film layer is described.

Abstract: The invention relates to a method for capping a MEMS wafer (1), in particular a sensor and/or actuator wafer, with at least one mechanical functional element (10). According to the invention, it is provided that the movable mechanical functional element (10) is fixed by means of a sacrificial layer (14), and that a cap layer (19) is applied to, in particular epitaxially grown onto, the sacrificial layer (14) and/or to at least one intermediate layer (17) applied to the sacrificial layer (14). The invention also relates to a capped MEMS wafer (1).

Abstract: A blank wafer is placed in an etch chamber. A layer is deposited over the blank wafer, comprising providing a deposition gas, forming the deposition gas into a deposition plasma, and stopping the deposition gas. The blank wafer with the deposited layer is removed from the etch chamber. The thickness of the deposited layer is measured. Wafer temperature accuracy is calculated from the measured thickness of the deposited layer. The etch chamber is compensated according to the calculated wafer temperature accuracy. A wafer with an etch layer over the wafer and a patterned mask over the etch layer is placed into the etch chamber. The etch layer is etched in the etch chamber.

Abstract: One embodiment is a method for fabricating ICs from a semiconductor wafer. The method includes performing a first process on the semiconductor wafer; taking a first measurement indicative of an accuracy with which the first process was performed; and using the first measurement to generate metrology calibration data, wherein the metrology calibration data includes an effective portion and a non-effective portion. The method further includes removing the non-effective portion from the metrology calibration data and modeling the effective portion with a metrology calibration model; combining the metrology calibration model with a first process model to generate a multi-resolution model, wherein the first process model models an input-output relationship of the first process; and analyzing a response of the multi-resolution model and second measurement data to control performance a second process.

Abstract: An integrated circuit comprises a receiver and an oscillator circuit. The receiver has a first input port for receiving a first oscillatory input signal, a second input port for receiving a second oscillatory input signal, and an output port for delivering an oscillatory output signal which is a function of both the first input signal and the second input signal. The oscillator circuit has a first output port for delivering a first oscillatory signal, and a second output port for delivering a second oscillatory signal. The first output port of the oscillator circuit is coupled to the HF port, and the second output port of the oscillator circuit is coupled to the LO port. The integrated circuit may be designed such that the HF port may be disconnected from the first output port of the oscillator circuit without affecting the operability of the receiver. An apparatus for testing the proper functioning of an integrated circuit as described above and a method of producing a receiver are also disclosed.

Abstract: One or more heating elements are disposed on a semiconductor substrate proximate a temperature sensitive circuit disposed on the substrate (e.g., bandgap circuit, oscillator). The heater element(s) can be controlled to heat the substrate and elevate the temperature of the circuit to one or more temperature points. One or more temperature measurements can be made at each of the one or more temperature points for calibrating one or more reference values of the circuit (e.g., bandgap voltage).

Abstract: An aspect of the invention provides a method of manufacturing a method of manufacturing a semiconductor element comprises the steps of: growing epitaxially a semiconductor layer on top of a semiconductor substrate; forming a patterned portion of the grown semiconductor layer by forming a pattern by a patterning process on top of the grown semiconductor layer; removing a portion of the semiconductor layer other than the patterned portion by a first etching method with a first etchant; and immersing a resultant from the first etching method in a second etchant that etches only the semiconductor substrate by a second etching method thereby removing the substrate from the semiconductor layer.

Abstract: A method for the fabrication of a semiconductor structure that includes areas that have different crystalline orientation and semiconductor structure formed thereby. The disclosed method allows fabrication of a semiconductor structure that has areas of different semiconducting materials. The method employs templated crystal growth using a Vapor-Liquid-Solid (VLS) growth process. A silicon semiconductor substrate having a first crystal orientation direction is etched to have an array of holes into its surface. A separation layer is formed on the inner surface of the hole for appropriate applications. A growth catalyst is placed at the bottom of the hole and a VLS crystal growth process is initiated to form a nanowire. The resultant nanowire crystal has a second different crystal orientation which is templated by the geometry of the hole.

Abstract: A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.

Abstract: A semiconductor package includes a wiring board, a semiconductor device mounted on the wiring board, an electrically-conductive thermal interface material provided on the semiconductor device, a test electrode in contact with a first surface of the thermal interface material to be electrically connected to the thermal interface material, and an electrically-conductive heat spreader in contact with a second surface of the thermal interface material opposite to its first surface.

Abstract: A microelectronic package includes a first substrate (120) having a first surface area (125) and a second substrate (130) having a second surface area (135). The first substrate includes a first set of interconnects (126) having a first pitch (127) at a first surface (121) and a second set of interconnects (128) having a second pitch (129) at a second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes a third set of interconnects (236) having a third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with a microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.

Abstract: A deposition apparatus includes: a first electrode for placing a processing object; a second electrode for generating plasma with the first electrode, the second electrode being opposed to the first electrode; and a heat flow control heat transfer part for drawing heat from the processing object to generate a heat flow from a central area to a peripheral area of the processing object.

Abstract: Systems and methods for detecting and monitoring Nickel-silicide process and induced failures. In a first method embodiment, a method of characterizing a Nickel-silicide semiconductor manufacturing process includes accessing a test chip including a parallel coupled chain of transistors, wherein the transistors are designed for inducing stress into Nickel-silicide features of the transistors, and for increasing a probability of a manufacturing failure of the Nickel-silicide features. A biasing voltage is applied to one terminal of the parallel coupled chain, all other terminals of the parallel coupled chain and grounded, and current is measured at each of the all other terminals of the parallel coupled chain. This process is repeated for each terminal of the parallel coupled chain. The measured currents from all possible conduction paths are compared to determine a manufacturing defect in the parallel coupled chain of transistors.

Abstract: A method for manufacturing and for testing an integrated circuit, including the steps of forming, on the upper portion of the integrated circuit, a passivation layer including openings at the level of metal tracks of the last interconnect stack of the integrated circuit; forming, in the openings, first pads connected to second pads formed on the passivation layer by conductive track sections, the first pads being intended for the connection of the integrated circuit; testing the integrated circuit by bringing test tips in contact with the second pads; and eliminating at least a portion of at least one of the conductive track sections.

Abstract: Under one aspect, a method of cooling a circuit element includes providing a thermal reservoir having a temperature lower than an operating temperature of the circuit element; and providing a nanotube article in thermal contact with the circuit element and with the reservoir, the nanotube article including a non-woven fabric of nanotubes in contact with other nanotubes to define a plurality of thermal pathways along the article, the nanotube article having a nanotube density and a shape selected such that the nanotube article is capable of transferring heat from the circuit element to the thermal reservoir.

Abstract: A method of monitoring copper contamination. The method includes method, comprising: (a) ion-implanting an N-type dopant into a region of single-crystal silicon substrate, the region abutting a top surface of the substrate; (c) activating the N-type dopant by annealing the substrate at a temperature of 500° C. or higher in an inert atmosphere; (c) submerging, for a present duration of time, the substrate into an aqueous solution, the aqueous solution to be monitored for copper contamination; and (d) determining an amount of copper adsorbed from the aqueous solution by the region of the substrate.

Abstract: A semiconductor die including a semiconductor chip and a test structure, located in a scribe area, is designed and manufactured. The test structure includes an array of complementary metal oxide semiconductor (CMOS) image sensors that are of the same type as CMOS image sensors employed in another array in the semiconductor chip and having a larger array size. Such a test structure is provided in a design phase by providing a design structure in which the orientations of the CMOS image sensors match between the two arrays. The test structure provides effective and accurate monitoring of manufacturing processes through in-line testing before a final test on the semiconductor chip.

Abstract: The present invention provides a manufacturing technique of a semiconductor device that reduces fluctuation of electric characteristic and a working size of a semiconductor device and can manufacture semiconductor devices at high quality and at high yield.

Abstract: Semiconductor device test structures and methods are disclosed. In a preferred embodiment, a test structure includes a feed line disposed in a first conductive material layer, and a stress line disposed in the first conductive material layer proximate the feed line yet spaced apart from the feed line. The stress line is coupled to the feed line by a conductive feature disposed in at least one second conductive material layer proximate the first conductive material layer.

Abstract: A COF packaging structure includes a substrate, a first conductive foil, and a second conductive foil. The substrate has a first surface and a second surface opposite to the first surface. The first conductive foil is disposed on the first surface of the substrate and has a first designated pattern for bump bonding. The second conductive foil is disposed on the second surface of the substrate and has a second designated pattern, wherein the area of the second designated pattern is not smaller than the area of the first designated pattern.

Abstract: According to one embodiment, a semiconductor device having a multilayer wiring structure includes a function block and a test pad. The function block contains a DFT circuit. The test pad is formed in an intermediate wiring layer, and connected to the DFT circuit of the function block. A functional operation test of the function block is executed by using the test pad.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The method for manufacturing the semiconductor device forms a recess gate region on a semiconductor substrate, forms an isolation layer isolated from the recess gate region using a high-temperature thermal process, and guarantees a larger channel region by filling the isolation layer with a gate electrode material, so that a cell current is increased and on/off characteristics of a transistor are improved.