Abstract: A method of making a backside illuminated sensor is provided. A substrate is provided and a high energy ion implantation is performed over the substrate to implant a first doped region. A layer is formed over the substrate and a self-align high energy ion implantation is performed over the substrate to implant a second doped region over the first doped region. The combined thickness of the first and second doped region is greater than 50 percent of thickness of the substrate and the distance between back surface of the substrate and the first and second doped regions is less than 50 percent of thickness of the substrate. In this way, an enlarged light sensing region is formed through which electrons generated from back surface of the surface may easily reach the pixel.

Abstract: A transient voltage suppressor (TVS) device includes a semiconductor substrate of a first conductivity type, and a first and a second semiconductor regions of a second conductivity type overlying the semiconductor substrate. A semiconductor layer of the second conductivity type overlies the first and the second semiconductor regions. The TVS device has a first trench extending through the semiconductor layer and the first semiconductor region and into the semiconductor substrate, and a fill material of the second conductivity type disposed in the first trench. A clamping diode in the TVS device has a junction between an out-diffused region from the fill material and a portion of the semiconductor substrate. The TVS device also includes a first P-N diode formed in a first portion of the semiconductor layer, and a second P-N diode having a junction between the second semiconductor region and the semiconductor substrate.

Abstract: An objective is simplification of a manufacturing method of a liquid crystal display device or the like. In a manufacturing method of a thin film transistor, a stack in which a first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked in this order is formed, and the first conductive film is exposed by first etching and a pattern of the second conductive film is formed by second etching. Further, after thin film transistors are formed, a color filter layer is formed so that unevenness caused by the thin film transistors or the like is relieved; thus, the level difference of the surface where the pixel electrode layer is formed is reduced. Alternatively, a color filter layer is selectively formed utilizing the unevenness caused by thin film transistors or the like.

Abstract: The present invention relates to a method for forming a package structure for a light emitting diode (LED) and the LED package structure thereof. By employing the same sawing process to cut through the trenches of the leadframe, the package units are singulated and different lead portions are simultaneously separated from each other in each package unit. Therefore, the overflow issues of the encapsulant can be avoided without using extra taping process.

Abstract: Provided is an image sensor and method for manufacturing the same. The image sensor includes a semiconductor substrate including a photodiode for each unit pixel, an interlayer insulating layer including metal lines on the semiconductor substrate, and an optical refractive part in a region of the interlayer insulating layer corresponding to the photodiode for focusing light on the photodiode. The optical refractive part can be formed by implanting impurities into the interlayer insulating layer.

Abstract: A 3D memory device is based on an array of conductive pillars and a plurality of patterned conductor planes including left side and right side conductors adjacent the conductive pillars at left side and right side interface regions. Memory elements in the left side and right side interface regions comprise a programmable element and a rectifier. The conductive pillars can be selected using two-dimensional decoding, and the left side and right side conductors in the plurality of planes can be selected using decoding on a third dimension, combined with left and right side selection.

Abstract: Described herein are wafer-level semiconductor device packages with stacking functionality and related stacked package assemblies and methods. In one embodiment, a semiconductor device package includes a set of connecting elements disposed adjacent to a periphery of a set of stacked semiconductor devices. At least one of the connecting elements is wire-bonded to an active surface of an upper one of the stacked semiconductor devices.

Abstract: A heterogeneous integrated circuit having at least one tier made of multiple technologies and a method of making the heterogeneous integrated circuit. The heterogeneous integrated circuit includes a package substrate, a first die of a first technology, and a second die of a second technology, where the two dies are located in the same tier. One die can surround the other die. The heterogeneous integrated circuit can also include a wire-bond and/or horizontal micro-bump coupling the two dies. The heterogeneous integrated circuit can also include a wire bond or vertical micro-bump coupling one of the dies to the package substrate. The vertical micro-bump coupling can include a through-via. The two technologies can be any of various technologies including CMOS, glass, sapphire and quartz. One die can also be adjacent to the other die on the same tier and the two dies coupled using a horizontal micro-bump.

Abstract: A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each connecting a contact area of the semiconductor chips. The method of making the semiconductor package includes the steps of connecting one or more connecting plates to a plurality of semiconductor chips, applying a molding material to encapsulate the chips and the connecting plates, separating a plurality of connecting plate portions of the connecting plates by shallow cutting through or by grinding.

Abstract: A method for packaging a stacked integrated circuit (IC) includes pre-processing the stacked IC before releasing the stacked IC from the carrier wafer. Pre-processing reduces wafer warpage and simplifies the packaging process by dicing materials separately. Pre-processing may be performed on the first tier wafer of a stacked IC during manufacturing to partially or completely dice the first tier wafer into first tier dies before release from the carrier wafer. Pre-processing may also be performed by laser cutting the mold compound surrounding the first tier wafer and second tier dies before releasing the stacked IC from the carrier wafer. Openings in the first tier wafer and/or mold compound allows balancing of stresses in the packaging process and reduction of wafer warpage.

Abstract: A method for forming a semiconductor structure includes forming an isolation region in a semiconductor substrate; forming a conductive layer over the isolation region; forming a first dielectric layer over the conductive layer; forming a plurality of conductive vias extending through the first dielectric layer to the conductive layer and electrically contacting the conductive layer; forming a second dielectric layer over the first dielectric layer; and forming a conductive ground plane in the second dielectric layer. Each of the plurality of conductive vias is in electrical contact with the conductive ground plane, and the conductive ground plane includes an opening, wherein the opening is located directly over the conductive layer. At least one interconnect layer may be formed over the second dielectric layer and may include a transmission line which transmits a signal having a frequency of at least 30 gigahertz.

Abstract: A semiconductor device has a semiconductor die mounted over a carrier. An encapsulant is deposited over the semiconductor die and carrier. An insulating layer is formed over the semiconductor die and encapsulant. A plurality of first vias is formed through the insulating layer and semiconductor die while mounted to the carrier. A plurality of second vias is formed through the insulating layer and encapsulant in the same direction as the first vias while the semiconductor die is mounted to the carrier. An electrically conductive material is deposited in the first vias to form conductive TSV and in the second vias to form conductive TMV. A first interconnect structure is formed over the insulating layer and electrically connected to the TSV and TMV. The carrier is removed. A second interconnect structure is formed over the semiconductor die and encapsulant and electrically connected to the TSV and TMV.

Abstract: Embodiments of an integrated circuit are provided. In one embodiment, the integrated circuit includes a substrate and a plurality of locally interconnected multi-gate transistors. The plurality of locally interconnected multi-gate transistors includes a continuous fin structure formed on the substrate and first and second multi-gate transistors formed on the substrate and including first and second fin segments of the continuous fin structure, respectively. The continuous fin structure electrically interconnects the first and second multi-gate transistors.

Abstract: A Configurable device comprising, a logic die connected by at least one through silicon-via (TSV), to an input/output (I/O) die.

Abstract: A thin film transistor array panel including a substrate, a gate line and a gate-layer signal transmitting line of a gate driving circuit portion formed on the substrate, a gate insulating layer formed on the gate line and the gate-layer signal transmitting line and having a first contact hole exposing a portion of the gate-layer signal transmitting line, a semiconductor layer formed on the gate insulating layer, a data line including a source electrode, and a drain electrode formed on the gate insulating layer and the semiconductor layer, a data-layer signal transmitting line of the gate driving circuit portion formed on the gate insulating layer and connected to the gate-layer signal transmitting line through the first contact hole, a pixel electrode connected to the drain electrode, and a passivation layer formed on the data line, the drain electrode, and the data-layer signal transmitting line of the driving circuit portion.

Abstract: Methods and systems are provided that may be used to utilize and manufacture a light sources apparatus. A first light emitting diode emits light having a first wavelength, and a second light emitting diode for emitting light having a second wavelength. Each of the first and second light emitting diodes may comprise angled facets to reflect incident light in a direct toward a top end of the first light emitting diode. The second light emitting diode comprising angled facets may reflect incident light in a direction toward a top end of the second light emitting diode. A first distributed Bragg reflector is disposed between the top end of the first light emitting diode and a bottom end of the second light emitting diode to allow light from the first light emitting diode to pass through and to reflect light from the second light emitting diode.

Abstract: A method of forming the structure of the semiconductor device having a waveguide. Firstly, a SOI substrate including a bulk silicon, an insulating layer, and a silicon layer is provided and a device region and a waveguide region are defined on the SOI substrate. Afterwards, a protection layer and a patterned shielding layer are formed to cover the waveguide region and expose the device region. Subsequently, a recess is formed by etching the protection layer, the silicon layer and the insulating layer and thereby the bulk silicon is exposed. After that, an epitaxial silicon layer is formed in the recess and a semiconductor device is subsequently formed on the epitaxial silicon layer. Also, the present invention conquers the poor electrical performance of the semiconductor device integrated into the SOI substrate.

Abstract: Disclosed is an organic light emitting display. In the organic light emitting display, a substrate is divided into a display region, in which an image is displayed, and a non-display region surrounding the display region. The organic light emitting display includes a plurality of pixels provided on the display region. At least one thin film transistor is formed on the non-display region. The display region includes a first electrode connected to the thin film transistor, an organic light emitting layer formed on the first electrode, and a second electrode formed on the organic light emitting layer to apply voltage to the organic light emitting layer with the first electrode. A light blocking layer having an opening formed below the semiconductor layer is formed on the non-display region.

Abstract: A feedthrough in an IC scribe seal is disclosed. The feedthrough is structured to maintain isolation of components in the IC from mechanical damage and chemical impurities introduced during fabrication and assembly operations. A conductive structure penetrates the scribe seal, possibly in more than one location, connecting an interior region to an exterior region. A feedthrough vertical seal surrounds the conductive element in the IC and connects to the scribe seal. A horizontal diffusion barrier connects to the scribe seal and the feedthrough vertical seal. The feedthrough vertical seal, the horizontal diffusion barrier and the IC substrate form a continuous barrier to chemical impurities around the conductive element in the interior region. The conductive structure includes any combination of a doped region in an active area, an MOS transistor gate layer, and one or more interconnect metal layers. The feedthrough is compatible with aluminum and copper interconnect metallization.

Abstract: A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode.

Abstract: A system for treating distinct batches of workpieces to serial procedures comprises first and second multi-site structures. In each multi-site structure the sites are rotatable for alignment in turn with loading and unloading stations together constituting treatment or process stations. Workpieces of a batch are loaded onto all of the treatment sites and then simultaneously and identically treated by operation of treatment stations with which the process sites are aligned. After treatment in the first structure, workpieces of a batch are transferred from the unloading stations of the first structure to the loading stations of the second structure for further processing.

Abstract: Methods of forming packaged micro-electromechanical devices include forming a first substrate having a micro-electromechanical device therein, which extends adjacent a first surface of the first substrate. A first surface of a second substrate is then bonded to the first surface of the first substrate, to thereby encapsulate the micro-electromechanical device within a space provided between the first and second substrates. Subsequent to bonding, a second surface of the second substrate is selectively etched to define at least one through-substrate opening therein, which exposes an electrode of the micro-electromechanical device. Thereafter, the through-substrate opening is filled with an electrically conductive through-substrate via.

Abstract: An integrated circuit chip and a method of fabricating an integrated circuit chip. The integrated circuit chip includes: a continuous first stress ring proximate to a perimeter of the integrated circuit chip, respective edges of the first stress ring parallel to respective edges of the integrated circuit chip; a continuous second stress ring between the first stress ring and the perimeter of the integrated circuit chip, respective edges the second stress ring parallel to respective edges of the integrated circuit chip, the first and second stress rings having opposite internal stresses; a continuous gap between the first stress ring and the second stress ring; and a set of wiring levels from a first wiring level to a last wiring level on the substrate.

Abstract: A memory card includes a circuit board, a first semiconductor chip mounted on the circuit board with a bump sandwiched between the first semiconductor chip and the circuit board, a second semiconductor chip mounted on the circuit board with a bump sandwiched between the second semiconductor chip and the circuit board with a clearance not greater than 1 mm between the first semiconductor chip and the second semiconductor chip, a first sealing resin layer surrounding the bump and existing between the first semiconductor chip and the circuit board, and a second sealing resin layer surrounding the bump and existing between the second semiconductor chip and the circuit board, and a cover covering the first semiconductor chip, the second semiconductor chip on a principal face of the circuit board.

Abstract: Disclosed are an ink composition and a method for fabricating a liquid crystal display (LCD) device using the same, wherein in forming patterns of the LCD device using an imprint lithography and a roll printing, an ink composition with high thermal resistance, consisting of polymer resin and additive both endurable even at a high temperature is used to form fine patterns with constantly maintaining pattern linewidths and line intervals, the ink composition consisting of 5-45% by weight of polymer resin, 5-45% by weight of additive added to retain thermal stability, and 50-90% by weight of organic solvent, wherein the ink composition is endurable even at a high temperature of 90-250° C.

Abstract: Method and apparatus for semiconductor device fabrication using a reconstituted wafer is described. In one embodiment, diced semiconductor chips are placed within openings on a frame. A reconstituted wafer is formed by filling a mold compound into the openings. The mold compound is formed around the chips. Finished dies are formed within the reconstituted wafer. The finished dies are separated from the frame.

Abstract: A storage system and method for forming a storage system that uses punch-through diodes as a steering element in series with a reversible resistivity-switching element is described. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in cross-point memory arrays having resistive switching elements. The punch-through diode may be a N+/P?/N+ device or a P+/N?/P+ device.

Abstract: A lower electrode is formed over a semiconductor substrate via an insulator film, first and second insulator films are formed to cover the lower electrode, an upper electrode is formed over the second insulator film, third to fifth insulator films are formed to cover the upper electrode and a void is formed between the first and second insulator films between the lower and upper electrodes. An ultrasonic transducer comprises the lower electrode, the first insulator film, the void, the second insulator film and the upper electrode. A portion of the first insulator film contacting with the lower electrode is made of silicon oxide, a portion of the second insulator film contacting with the upper electrode is made of silicon oxide and the first or second insulator film includes a silicon nitride film positioned between the upper and lower electrodes and not in contact with the upper and lower electrodes.

Abstract: A combined thermoelectric/photovoltaic device features a photovoltaic cell with a common electrode, an electrically insulative, thermally conductive layer applied to the common electrode, and an array of thermoelectric couples each including a p-type semiconductor element and an n-type semiconductor element. There is an electrically conductive bridge for each thermoelectric couple formed on the electrically insulative thermally conductive layer. Methods of making such a hybrid device also including a heat sink are also disclosed.

Abstract: A method of forming an active region structure includes preparing a semiconductor substrate including a cell array region and a peripheral circuit region, forming preliminary cell active regions in the cell array region of the semiconductor substrate, and forming cell active regions in the preliminary cell active regions and at least one peripheral active region in the peripheral circuit region of the semiconductor substrate, such that the preliminary cell active regions, the cell active regions, and the at least one peripheral active region are integrally formed with the semiconductor substrate and protrude from the semiconductor substrate.

Abstract: A carrier applicable to a laser releasing process and for carrying at least a flexible display panel is provided. The flexible display panel is formed on a transparent substrate and includes a display main body and a driving circuit module connected to an edge of the display main body. The carrier includes a carrying plate having at least a carrying area for carrying the flexible display panel and a protecting cover disposed on the carrying plate and located at an edge of the carrying area. A receiving space is formed between the protecting cover and the carrying plate for receiving the driving circuit module. The protecting cover is for shielding the driving circuit module to prevent the driving circuit module from being irradiated by a laser beam in the laser releasing process. A method for manufacturing flexible display panel also is provided.

Abstract: A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing at least one semiconductor substrate having a CMOS device area including dielectric layers and metallization layers; applying at least one protective layer overlying the CMOS device area; forming at least one opening on the protective layer and patterning the dielectric and metallization layers to access the semiconductor substrate; forming at least one opening on the semiconductor substrate by etching the dielectric and metallization layers; applying at least one filler layer in the at least one opening on the semiconductor substrate; positioning at least one chip on the filler layer, the chip including a prefabricated front face and a bare backside; applying a first insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip; forming at least one via opening on the insulating layer covering the chip to access at least one contac

Abstract: A viscosity measurement device includes a flexible membrane, an actuation heating element, and a displacement sensor apparatus. The actuation heating element is on and spaced in from an outer periphery of the flexible membrane.

Abstract: The invention relates to the manufacture of a matrix sensor using a sensitive layer of a ferroelectric P(VDF/TrFE) copolymer, deposited on an integrated circuit. In order to simplify the manufacture and improve the yields, deposited first on the integrated circuit is a first layer of titanium and it is etched in order to form a matrix array of electrodes electrically connected to the integrated circuit; next, a P(VDF/TrFE) copolymer comprising a small proportion of around 1 to 10% of a second polymer that favors the adhesion of the P(VDF/TrFE) copolymer is deposited on the integrated circuit; the polymer is either underneath the P(VDF/TrFE) or blended therewith. The copolymer and its adhesion promoter are etched in a single step, and finally a second conductive layer is deposited and it is etched in order to form a counter electrode for the whole of the matrix array. For use in ultrasonic image sensors.

Abstract: An apparatus and method is described for measuring a local surface temperature of a semiconductor device under stress. The apparatus includes a substrate, and a reference MOSFET. The reference MOSFET may be disposed closely adjacent to the semiconductor device under stress. A local surface temperature of the semiconductor device under stress may be measured using the reference MOSFET, which is not under stress. The local surface temperature of the semiconductor device under stress may be determined as a function of drain current values of the reference MOSFET measured before applying stress to the semiconductor device and while the semiconductor device is under stress.

Abstract: The invention relates to the fabrication of electronic circuits on a thinned semiconductor substrate. To produce a connection pad on the back side of the thinned substrate, the procedure is as follows: an integrated circuit is produced on an unthinned substrate, in which a portion of a polycrystalline silicon layer (18) dedicated for the connection of the pad is provided. The circuit is transferred onto a transfer substrate (30) and then its back side is thinned. A via is opened in the thinned semiconductor layer (12) in order to gain access to the polycrystalline silicon; aluminum (80) is deposited and this layer is etched so as to define a pad which is in contact with the internal interconnects of the integrated circuit by way of the polycrystalline silicon.

Abstract: An IC inductor structure is provided which includes a first inductor element formed on a semiconductor substrate and at least a second inductor element formed on the semiconductor substrate proximate the first inductor element. The first inductor element has a first effective magnetic field direction associated therewith, and the second inductor element has a second effective magnetic field direction associated therewith. The first and second inductor elements are oriented relative to one another so as to create a non-zero angle between the first and second effective magnetic field directions.

Abstract: A semiconductor device includes a semiconductor constituent provided with a semiconductor substrate and a plurality of electrodes for external connection provided under the semiconductor substrate. A lower-layer insulating film is provided under and around the semiconductor constituent. A plurality of lower-layer wirings are electrically connected to the electrodes for external connection of the semiconductor constituent, and provided under the lower-layer insulating film. An insulation layer is provided on the lower-layer insulating film in the periphery of the semiconductor constituent. An upper-layer insulating film is provided on the semiconductor constituent and the Insulation layer. A plurality of upper-layer wirings are provided on the upper-layer insulating film. A base plate on which the semiconductor constituent and the insulation layer are mounted is removed.

Abstract: The reliability of the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via the insulating film which has adhesive property is improved. In the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via DAF, thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit was formed was made thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit was formed. Hereby, the defect that the bonding wire which connects the uppermost semiconductor chip and a wiring substrate contacts the main surface corner part of a lower layer semiconductor chip can be reduced.

Abstract: A layered chip package includes a plurality of layer portions stacked, each layer portion including a semiconductor chip having a first surface with a device formed thereon and a second surface opposite thereto. The plurality of layer portions include at least a pair of layer portions disposed such that the first surfaces of the respective semiconductor chips face toward each other. A manufacturing method for the layered chip package includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure.

Abstract: A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.

Abstract: Process for producing strip-shaped and/or point-shaped electrically conducting contacts on a semiconductor component like a solar cell, includes the steps of applying a moist material forming the contacts in a desired striplike and/or point-like arrangement on at least one exterior surface of the semiconductor component; drying the moist material by heating the semiconductor component to a temperature T1 and keeping the semiconductor element at temperature T1 over a time t1; sintering the dried material by heating the semiconductor component to a temperature T2 and keeping the semiconductor component at temperature T2 over a time t2; cooling the semiconductor component to a temperature T3 that is equal or roughly equal to room temperature, and keeping the semiconductor component at temperature T3 over a time T3; cooling the semiconductor component to a temperature T4 with T4??35° C.

Abstract: A semiconductor device includes a housing defining a cavity, a magnetic sensor chip disposed in the cavity, and mold material covering the magnetic sensor chip and substantially filling the cavity. One of the housing or the mold material is ferromagnetic, and the other one of the housing or the mold material is non-ferromagnetic.

Abstract: The invention relates to semiconductor substrates and methods for producing such semiconductor substrates. In this connection, it is the object of the invention to provide semiconductor substrates which can be produced more cost-effectively and with which a high arrangement density as well as good electrical conductivity and closed surfaces can be achieved. In accordance with the invention, an electrically conductive connection is guided from its front side through the substrate up to the rear side. The electrically conductive connection is completely surrounded from the outside. The insulator is formed by an opening which is filled with material. The inner wall is provided with a dielectric coating and/or filled with an electrically insulating or conductive material. The electrically conductive connection is formed with a further opening which is filled with an electrically conductive material and is arranged in the interior of the insulator.

Abstract: A method for producing an encapsulation module and/or for encapsulating a micromechanical arrangement, wherein electronic connection provisions are formed from a blank of electrically conductive semiconductor material, by one or more structuring processes and/or etching processes, wherein, in the course of forming the electronic connection provisions, a pedestal of the semiconductor material arises, on which the electronic connection provisions are arranged, wherein the latter are subsequently embedded with an embedding material and the embedding material and/or the semiconductor pedestal are removed after the embedding to an extent such that a defined number of the electronic connection provisions have electrical contacts on at least one of the outer surfaces of the encapsulation module thus produced, wherein upon forming the electronic connection provisions, on the pedestal of the semiconductor material, an insular material hump is formed, on which a plated-through hole is arranged in each case, and which e

Abstract: A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.

Abstract: A first wire layer (19) including first memory wires (12) is connected to a second wire layer (20) including second memory wires (17) via first contacts (21) penetrating a first interlayer insulating layer (13). The first wire layer (13) is connected to and led out to upper wires (22) via second contacts (26) connected to the second wire layer (20) and penetrating the second interlayer insulating layer (18). The first contacts (21) penetrate semiconductor layer (17b) or insulator layer (17c) of the second wire layer (20).

Abstract: Light emitting diode (LED) structures are fabricated in wafer scale by mounting singulated LED dies on a carrier wafer or a stretch film, separating the LED dies to create spaces between the LED dies, applying a reflective coating over the LED dies and in the spaces between the LED dies, and separating or breaking the reflective coating in the spaces between the LED dies such that some reflective coating remains on the lateral sides of the LED die. Portions of the reflective coating on the lateral sides of the LED dies may help to control edge emission.

Abstract: A silicon biosensor and a manufacturing method thereof is provided, the silicon biosensor includes: a light source performing self emission a light detector generating a photoelectric current corresponding to an amount of incident light an optical fiber transmitting the light from the light source to the light detector and a micro fluidic channel adjusting an optical transmission rate of the optical fiber according to an antibody-antigen reaction when the antibody-antigen reaction occurs. The silicon biosensor can be easily integrated or bonded with a silicon electronic device, so that it is possible to manufacture the biosensor with a low price, under mass production.

Abstract: Electronic devices are formed on a substrate that is advanced stepwise through a plurality of deposition vessels. Each deposition vessel includes a source of deposition material and has at least two shadow masks associated therewith. Each of the two masks is alternately positioned within the corresponding deposition vessel for patterning the deposition material onto the substrate through apertures in the mask positioned therein, and positioned in an adjacent cleaning vessel for mask cleaning. The patterning onto the substrate and the cleaning of at least one of the masks are performed concurrently.