Abstract: There are provided a display apparatus which can be stably driven for a long period of time and can display an image with high definition and less image defect, and a production method thereof. The display apparatus includes a light-emitting layer, a pair of electrodes sandwiching the light-emitting layer, a transistor with an active layer for driving the light-emitting layer through the pair of the electrodes, and a matrix wiring portion having a scanning electrode line, a signal electrode line, and a first insulating layer, wherein the active layer includes an oxide which contains In and Zn and at least a part of which is amorphous, and wherein a second insulating layer containing hydrogen in an amount of less than 3×1021 atoms/cm3 is disposed between the active layer and the first insulating layer.

Abstract: A semiconductor device of three-dimensional structure in which the operating frequency of a chip can be raised while preventing the chip area from increasing. The three-dimensional structure semiconductor device have a first integrated circuit including a plurality of areas formed on a first conductor layer and a first wiring layer formed on the first conductor layer, a first insulating layer laminated on the first wiring layer, and a second integrated circuit including a plurality of areas formed on a second conductor layer which is laminated on the first insulating layer, and a second wiring layer formed on the second conductor layer. The first integrated circuit and the second integrated circuit are connected electrically by interconnection penetrating in the laminating direction and at least one of bidirectional communication of data, control signal supply, and clock signal supply between the first integrated circuit and the second integrated circuit is carried out through the penetrating interconnection.

Abstract: A thermoelectric device is disclosed which includes metal thermal terminals protruding from a top surface of an IC, connected to vertical thermally conductive conduits made of interconnect elements of the IC. Lateral thermoelectric elements are connected to the vertical conduits at one end and heatsinked to the IC substrate at the other end. The lateral thermoelectric elements are thermally isolated by interconnect dielectric materials on the top side and field oxide on the bottom side. When operated in a generator mode, the metal thermal terminals are connected to a heat source and the IC substrate is connected to a heat sink. Thermal power flows through the vertical conduits to the lateral thermoelectric elements, which generate an electrical potential. The electrical potential may be applied to a component or circuit in the IC. The thermoelectric device may be integrated into an IC without adding fabrication cost or complexity.

Abstract: The present invention relates to a complex type semiconductor device formed by laminating plural semiconductor packages, wherein it comprises: an upper semiconductor package which comprises a substrate for wiring and connecting provided with electrodes for conducting packages on a lower surface in the upper semiconductor package and a principal part of the upper semiconductor package disposed on an upper surface and/or a lower surface of the above substrate and which constitutes a relatively upper part, a lower semiconductor package which comprises a substrate for wiring and connecting provided with electrodes for conducting packages on an upper surface in the lower semiconductor package and a principal part of the lower semiconductor package disposed on an upper surface and/or a lower surface of the above substrate and which constitutes a relatively lower part, a spacer sheet which comprises a space part corresponding to the principal part of the upper semiconductor package and/or the principal part of th

Abstract: The objective of the invention is to prevent electrostatic destruction of semiconductor chips during resin molding. With the semiconductor device manufacturing method, a substrate 400 that includes on the surface multiple semiconductor chips 410 and liquid resin 434 supplied to multiple semiconductor devices is supported by an electrically insulated lower die 200. An upper die 110 in which multiple shape-forming parts (cavities) 112 are formed is pressed against lower die 200 through the medium of a polymer release film 300, and liquid resin 434 on the substrate is molded.

Abstract: A method of fabricating a shuttle wafer is provided. First, a wafer including a number of shots is provided. Each of the shots includes a number of dies. A material layer is then formed on the wafer. After that, a shuttle mask having a number of IC designs is provided. A first IC design corresponds to a first die of each of the shots. A portion of the IC designs on the shuttle mask is covered for exposing the first IC design. Thereafter, the first IC designs of the shuttle mask are transferred onto the material layer, so as to form at least an effective IC pattern on the first die of each of the shots and to form an ineffective IC pattern on each of the other dies of each of the shots.

Abstract: A method of forming a semiconductor card. A semiconductor package having a damaged controller die is reclaimed. The reclaim process includes severing the electrical connections between the controller die and the semiconductor package substrate without exposing the passive component. In one embodiment, the cutting tool comprises a saw blade. An electrically insulating material is deposited over the exposed bond wires to complete the reclaim process. The reclaimed package and a new controller die are affixed to a second substrate to electrically couple the memory die of the reclaimed package with the new controller die—forming a new package. The new package is encapsulated to form a new memory card.

Abstract: A thin film transistor (TFT) substrate includes a transparent substrate, a plurality of TFTs and a photosensitive capacitor formed on the transparent substrate. A capacitance of the photosensitive capacitor is variable on the condition of environment brightness. A method for manufacturing the TFT substrate and an LCD using the TFT substrate are also provided.

Abstract: A semiconductor chip includes a first mark for identifying a position of the chip within an exposure field. The semiconductor chip includes a first matrix in a first layer of the chip and a second mark within the first matrix identifying a position of the exposure field on a wafer.

Abstract: Disclosed is an AC light emitting device having photonic crystal structures and a method of fabricating the same. The light emitting device includes a plurality of light emitting cells and metallic wirings electrically connecting the light emitting cells with one another. Further, each of the light emitting cells includes a first conductive type semiconductor layer, a second conductive type semiconductor layer disposed on one region of the first conductive type semiconductor layer, and an active layer interposed between the first and second conductive type semiconductor layers. In addition, a photonic crystal structure is formed in the second conductive type semiconductor layer. The photonic crystal structure prevents light emitted from the active layer from laterally propagating by means of a periodic array, such that light extraction efficiency of the light emitting device can be improved.

Abstract: A sealable microelectronic device providing mechanical stress endurance which includes a semiconductor substrate. A substantially continuous sealing element is positioned adjacent an outer periphery and between a microelectronic component and the semiconductor substrate, or another microelectronic component. The sealing element seals the microelectronic component to the substrate or another microelectronic component, and provides structural support to the microelectronic device.

Abstract: A negative differential resistance (NDR) device is designed and a possible compact device implementation is presented. The NDR device includes a voltage blocker and a current blocker and exhibits high peak-to-valley current ratio (PVCR) as well as high switching speed. The corresponding process and design are completely compatible with contemporary Si CMOS technology and area efficient. A single-NDR element SRAM cell prototype with a compact size and high speed is also proposed as its application suitable for embedded memory.

Abstract: Methods and systems are provided for low pressure baking to remove impurities from a semiconductor surface prior to deposition. Advantageously, the short, low temperature processes consume only a small portion of the thermal budget, while still proving effective at removing interfacial oxygen from the semiconductor surface. The methods and systems are particularly well suited for treating semiconductor surfaces before epitaxy.

Abstract: By filling an air gap between tiers of a stacked IC device with a thermally conductive material, heat generated at one or more locations within one of the tiers can be laterally displaced. The lateral displacement of the heat can be along the full length of the tier and the thermal material can be electrically insulating. Through silicon-vias (TSVs) can be constructed at certain locations to assist in heat dissipation away from thermally troubled locations.

Abstract: A laser annealing method includes forming a nitrogen-doped layer on a semiconductor layer, the nitrogen-doped layer having a nitrogen concentration of at least 3×1020 atoms/cc, irradiating a first area of the nitrogen-doped layer in a low oxygen environment with a laser beam and irradiating a second area of the nitrogen-doped layer in a low oxygen environment with a laser beam, a part of the second area overlapping with the first area.

Abstract: To provide a structure and a manufacturing method which can manufacture, at a low cost and with good yield, a liquid crystal display panel having a lenticular lens and a substrate formed in a unified manner. When forming a lenticular lens onto a mother CF substrate by using a wet etching method, substrates are dipped into an etching solution while being raised up in such a manner that the length direction of slit openings of a mask is aligned with a vertical direction and an area having no mask pattern comes on a bottom side. With this, the residuals generated due to glass impurities can be drained towards the lower side along the lenticular lens shape to be discharged to the flat area, which makes it possible to suppress deterioration in the etching processed shape.

Abstract: Provided are a semiconductor device including a source/drain and a gate formed using a doped polysilicon process, and a method of fabricating the semiconductor device. The method comprises: forming a gate insulating layer on a part of an active region on a first conductivity type epitaxial layer; forming a conductive layer on the epitaxial layer; implanting high concentration impurities of a second conductivity type a first portion of the conductive layer on the gate insulating layer and second portions of the conductive layer on both sides of the first insulating layer; patterning the conductive layer; forming a second insulating layer on the epitaxial layer and high concentration impurity regions of the second conductivity type below the second conductive pattern; and implanting low-concentration impurities of the second conductivity type into the epitaxial layer between a gate structure and the high concentration impurity regions.

Abstract: The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistances with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.

Abstract: A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.

Abstract: An objective is simplification of a manufacturing method of a liquid crystal display device or the like. In a manufacturing method of a thin film transistor, a stack in which a first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked in this order is formed, and the first conductive film is exposed by first etching and a pattern of the second conductive film is formed by second etching. Further, after thin film transistors are formed, a color filter layer is formed so that unevenness caused by the thin film transistors or the like is relieved; thus, the level difference of the surface where the pixel electrode layer is formed is reduced. Alternatively, a color filter layer is selectively formed utilizing the unevenness caused by thin film transistors or the like.

Abstract: A method for manufacturing a liquid crystal display, the method includes steps of depositing a transparent conductive layer, forming a pixel electrode, and four bottom layers, depositing a semiconductor insulation layer on the pixel electrode and the four bottom layers, defining the semiconductor insulation layer to form two contact openings two of the bottom layers, depositing and defining two top layers and two scanning lines both with an indentation at an edge thereof, and the indentations face the first pixel electrode by an opposite direction, and forming four metal-insulation-metal (MIM) diodes.

Abstract: A semiconductor package is obtained by separately preparing a board having, as formed on the surface thereof, an interconnect pattern containing a fine pattern having a narrow interconnect pitch adapted to connection with a high-pin-count device, and a board having, as formed on the surface thereof, an interconnect pattern containing no fine pattern but only a rough pattern having a wide interconnect pitch adapted to connection with a low-pin-count device; by mounting the devices respectively on these boards; and by stacking these boards.

Abstract: An array of pixels is formed using a substrate, where each pixel has a substrate having an incident side for receiving incident light, a photosensitive region formed in the substrate, and a reflector having a complex-shaped surface. The reflector is formed in a portion of the substrate that is opposed to the incident side such that light incident on the complex-shaped surface of the reflector is reflected towards the photosensitive region.

Abstract: A solid-state image sensor includes a plurality of light-receiving elements arranged in a light-receiving area, and a plurality of micro-lenses corresponding to the light-receiving elements, and has a flattening film formed on the plurality of the micro-lenses. At a center of the light-receiving area, the micro-lenses are placed in positions directly above corresponding photodiodes, and placed in positions which are progressively offset from positions directly above the corresponding photodiodes, towards a center of the light receiving area, as micro-lenses are located farther from the center of the light-receiving area.

Abstract: Provided may be a treatment method to remove defects created on the surface of a substrate, a method of fabricating an image sensor by using the treatment method, and an image sensor fabricated by the same. The treatment method may include providing a semiconductor substrate including a surface defect, providing a chemical solution to a surface of the semiconductor substrate, and removing the surface defect by consuming the surface of the semiconductor substrate and forming a chemical oxide layer on the semiconductor substrate.

Abstract: Disclosed in this specification is a multiphase buck converter package and process for forming such package. The package includes at least four dice and several parallel leads. The dice are electrically connected through a plurality of die attach pads, thus eliminating the need for wirebonding.

Abstract: An embodiment of an array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type, housing a first cathode region, of the second conductivity type, and facing a surface of the body, an anode region, having the first conductivity type and a higher doping level than the body, extending inside the body, and facing the surface laterally to the first cathode region and at a distance therefrom, and an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the first cathode region and the anode region. The insulation region is formed by a mirror region of metal material, a channel-stopper region having the second conductivity type, surrounding the mirror region, and a coating region, of dielectric material, arranged between the mirror region and the channel-stopper region.

Abstract: Embodiments relate to an image sensor. According to embodiments, an image sensor may include a metal interconnection and readout circuitry over a first substrate, a metal layer over the metal interconnection, and an image sensing device electrically connected to the metal layer. According to embodiments, an electric field may not be generated on and/or over an Si surface. This may contribute to a reduction in a dark current of a 3D integrated CMOS image sensor.

Abstract: A plurality of diffused resistors and a plurality of wirings (resistive elements) are alternately disposed along a virtual line, and those diffused resistors and wirings are connected in series by contact vias. In the same wiring layer as that of the wirings, a dummy pattern is formed so as to surround a formation region of the wirings and the diffused resistors. A space between the dummy pattern and the wirings is set in accordance with, for example, a minimum space between wirings in a chip formation portion.

Abstract: The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (1) comprising a bipolar transistor with in that order a collector region (2), a base region (3), and an emitter region (4), wherein the semiconductor body comprises a projecting mesa (5) comprising at least a portion of the collector region (2) and the base region (3), which mesa is surrounded by an isolation region (6). According to the invention, the semiconductor device (10) also comprises a field effect transistor with a source region, a drain region, an interposed channel region, a superimposed gate dielectric (7), and a gate region (8), which gate region (8) forms a highest part of the field effect transistor, and the height of the mesa (5) is greater than the height of the gate region (8). This device can be manufactured inexpensively and easily by a method according to the invention, and the bipolar transistor can have excellent high-frequency characteristics.

Abstract: A field-effect transistor includes a semiconductor layer (14) having a portion functioning as a channel region. The semiconductor layer (14) includes, as its constituent components, a plurality of electrically conductive microparticles (52), organic semiconductor molecules (53) bonded to the microparticles (52) so as to link the microparticles to one another (52), and cyclic molecules. Each of the organic semiconductor molecules (53) includes a ?-electron conjugated chain as its main chain, and the ?-electron conjugated chain is insulated by cyclic molecules.

Abstract: A pixel structure disposed on a substrate and including a common line, a reserved line, a dielectric layer, two repair lines, an active device, and a pixel electrode is provided. The reserved line and the common line are disposed on the substrate and are covered by the dielectric layer. The repair lines are disposed on the dielectric layer, and each repair line has a first repairing region overlapped with the common line and a second repairing region overlapped with the reserved line. When the common line is open, the repair lines in the first and second repairing regions are connected with the common line and the reserved line, such that the common line, the repair lines, and the reserved line are electrically connected. After the common line, the repair lines, and the reserved line are connected, the above-mentioned pixel structure is effectively repaired.

Abstract: A ridge stripe type semiconductor laser device is provided, on a semiconductor substrate (102), with a first conduction type cladding layer (103), an active layer (104), a second conduction type first cladding layer (105), a second conduction type second cladding layer (108) of a ridge type stripe shape for confining direction, and a current block layer (107) formed by removing at least an upper portion of the ridge. In a section normal to the stripe direction of the ridge, each of the two side faces of the ridge is provided with a first face (118) substantially normal to the semiconductor substrate surface and extending downward from the upper end of the ridge, and a second face (119) formed to have a substantially straight skirt slope face inclined at the ridge skirt portion obliquely downward to the ridge outside. The first face and the second face are made to merge either directly or through a third intermediate face into each other.

Abstract: A method of indexing a plurality of dice obtained from a material wafer comprising a plurality of stacked material layers, each die being obtained in a respective die position in the wafer, the method including providing a visible index on each die indicative of the respective die position, wherein providing the visible index on each die includes: forming in a first material layer of the die a reference structure adapted to defining a mapping of the wafer; and forming in a second material layer of the die a marker associated with the reference structure, a position of the marker with respect to the reference structure being adapted to provide an indication of the die position in the wafer.

Abstract: A method of fabricating a pixel structure of liquid crystal display is described. A transparent conductive layer and a first metal layer are formed over a substrate sequentially. The first metal layer and the transparent conductive layer are patterned to form a gate pattern and a pixel electrode pattern. A gate insulating layer and a semiconductor layer are formed over the substrate sequentially. A patterning process is performed to preserve the semiconductor layer and the gate insulating layer above the gate pattern and remove the first metal layer of the pixel electrode pattern. A second metal layer is formed over the substrate. The second metal layer is patterned to form a source pattern and a drain pattern. A black material layer is formed over the substrate, and then the black material layer is patterned to form a black matrix pattern uncovering the transparent conductive layer of the pixel electrode pattern.

Abstract: A chip-to-chip interconnect system suited for MEMS that do not require low-resistance connections is described. The interconnects may be fabricated simultaneously with MEMS ribbon structures such as are found in MEMS optical modulators.

Abstract: A method for dicing a wafer including the following steps is provided. First, a carrier tape is attached to a first side of the wafer. Then, a patterned photoresist layer exposing a scribe line region of the wafer is formed on a second side of the wafer, in which the second side is the opposite side of the first side. After that, a cutting process is performed to the scribe line region from the second side of the wafer to the first side of the wafer through non-mechanical force.

Abstract: A technique for manufacturing a micro-electro-mechanical (MEM) device includes a number of steps. Initially, a first wafer is provided. Next, a bonding layer is formed on a first surface of the first wafer. Then, a portion of the bonding layer is removed to provide a cavity including a plurality of spaced support pedestals within the cavity. Next, a second wafer is bonded to at least a portion of the bonding layer. A portion of the second wafer provides a diaphragm over the cavity and the support pedestals support the diaphragm during processing. The second wafer is then etched to release the diaphragm from the support pedestals.

Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

Abstract: Electronic devices are formed on a substrate that is advanced stepwise through a plurality of deposition vessels. Each deposition vessel includes a source of deposition material and has at least two shadow masks associated therewith. Each of the two masks is alternately positioned within the corresponding deposition vessel for patterning the deposition material onto the substrate through apertures in the mask positioned therein, and positioned in an adjacent cleaning vessel for mask cleaning. The patterning onto the substrate and the cleaning of at least one of the masks are performed concurrently.

Abstract: A method of cutting a semiconductor wafer includes preparing a semiconductor wafer including a scribe region and a chip region, forming a groove in the scribe region, loading the semiconductor wafer with the groove formed therein in a chamber, and cutting the semiconductor wafer into a plurality of chips through increasing a pressure of the chamber by a first pressure change rate, and then reducing the pressure of the chamber by a second pressure change rate.

Abstract: A CMOS image sensor and fabricating method thereof are disclosed, by which a light condensing effect is enhanced by providing an inner microlens to a semiconductor substrate. The present invention includes a plurality of photodiodes on a semiconductor substrate, a plurality of inner microlenses on a plurality of the photodiodes, an insulating interlayer on a plurality of the inner microlenses, a plurality of metal lines within the insulating interlayer, a device protecting layer on the insulating interlayer, and a plurality of microlenses on the device protecting layer.

Abstract: An ultrasound transducer (40,70,100) comprises a combined individual die integrated circuit (42,72,102) and an array of acoustic elements (44,74,104) coupled to the combined individual die integrated circuit via an array of flip-chip bumps (46,76,106). The combined individual die integrated circuit includes a first integrated circuit die (48,78,108) aligned with at least one additional integrated circuit die (50,80,(110,112)). In addition, the first integrated circuit die, the at least one additional die integrated circuits, and the array of acoustic elements together form a large aperture transducer array. large aperture transducer array.

Abstract: A width and a length of the electrostatic discharge (ESD) protection circuit are reduced by changing a connection structure of the electrostatic discharge protection circuit. The ESD protection circuit includes a plurality of gate electrodes disposed between odd signal lines and even signal lines adjacent to the odd signal lines among the signal lines; source/drain electrode pairs each disposed on a respective one of the gate electrodes to form a plurality of transistors; and connection nodes parallel to the source/drain electrode pairs, each connection node adjacent to a respective one of the source/drain electrodes pairs and on a respective one of the gate electrodes, wherein each of the connection nodes is directly connected to the source/drain electrode pair of an adjacent transistor and the gate electrode formed below the source/drain electrode through a contact part.

Abstract: A vertical cavity surface emitting laser diode (VCSEL) with a new structure is disclosed. The VCSEL of the invention provides the active layer, the first spacer layer, the tunnel junction, the second spacer layer burying the tunnel junction. Only the first spacer layer is ion-implanted to form a high-resistive region around the tunnel junction. The current injected into the second spacer layer is confined by the tunnel junction to reach the active layer, which reduces the increase of the parasitic resistance of the device. The high-resistive region around the tunnel junction reduces the parasitic capacitance of the device.

Abstract: A method of manufacturing an active matrix substrate includes forming wiring lines each having a matrix pattern on a substrate such that a wiring line extending in any one of a first direction and a second direction is separated from another wiring line at an intersection; forming a laminated portion composed of an insulating layer and a semiconductor layer on a portion of the wiring line and the intersection; and forming a conductive layer electrically connecting the separated wiring line, and a pixel electrode electrically connected to the wiring line via the semiconductor layer on the laminated portion.

Abstract: A solid-state imaging device having an electrode for reading a signal charge is provided on one side of a light-receiving sensor portion constituting a pixel; a predetermined voltage signal applied to a light-shielding film formed to cover an image pickup area except the light-receiving sensor portion; a second-conductivity-type semiconductor area formed in the center on the surface of a first-conductivity-type semiconductor area constituting a photo-electric conversion area of the light-receiving sensor portion; and areas containing a lower impurity concentration than that of the second-conductivity-type semiconductor area formed on the surface of the first-conductivity-type semiconductor area at the end on the side of the electrode and at the opposite end on the side of a pixel-separation area.

Abstract: An array substrate comprising: a first insulator film arranged to insulate scanning and control lines from signal lines; switching elements, each of which is arranged in vicinity of respective intersection of the scanning and signal lines; a second insulator film that covers a multi-layer wiring pattern including the scanning and control lines and the signal lines; pixel electrodes, each of which is electrically connected to respective one of the signal lines through the respective switching element; island metal patterns, each of which is arranged to at least partly overlap the control line and is electrically connected with the respective switching element; a wiring breakage that separates one of the signal lines into two wiring parts; and bridge wirings, which connect said two wiring parts by way of one of the island metal patterns and are arranged to overlap the pixel electrodes as interposed by the second insulator film therebetween.

Abstract: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Covering material is formed over an elevationally outer lateral interface of the conductive material within the trench and the insulative material of the circuitry area. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area and to expose the conductive material within the trench. The conductive material within the array area is incorporated into a plurality of capacitors.

Abstract: One embodiment is a micro hemispheric resonator gyro having: a plurality of pickoff and forcer electrodes; a hemispheric resonator; a guard ring having first and second opposed sides, the guard ring containing the plurality of pickoff and forcer electrodes, and the hemispheric resonator; a top cover operatively coupled to the first side of the guard ring; and a bottom cover operatively coupled to the second side of the guard ring; wherein the plurality of pickoff and forcer electrodes, the hemispheric resonator, the guard ring, the top cover and the bottom cover form a micro hemispheric resonator gyro.