Abstract: Provided are a monolithic microwave integrated circuit device and a method for forming the same. The method include: forming an HBT on a substrate; forming a wiring of the HBT and a bottom electrode of a capacitor on the substrate, with a first metal, the bottom electrode being spaced apart from the HBT; forming a first insulation layer on the substrate to cover the HBT and the bottom electrode; and forming a top electrode of the capacitor on the first insulation layer and forming a resistance pattern on the substrate, with a second metal, the resistance pattern being spaced apart from the capacitor, wherein an edge of the top electrode is spaced apart from an edge of the bottom electrode.

Abstract: In one embodiment, a plurality of ESD devices are used to form an integrated semiconductor filter circuit. Additional diodes are formed in parallel with the ESD structures in order to increase the input capacitance.

Abstract: A method of manufacturing a bipolar transistor is compatible with FinFET processing. A collector region (18) is formed and patterned, base contact regions (26) formed on either side, and a gap formed between the base contact region. A base (28), spacers (30) and an emitter (32) are formed in the gap.

Abstract: A bipolar semiconductor device includes a collector region that is an n-type low-resistance layer formed in one surface of a semiconductor crystal substrate, an n-type first high-resistance region on the collector region, a p-type base region on the first high-resistance region, an n-type low-resistance emitter region that is formed in another surface of the semiconductor crystal substrate, an n-type second high-resistance region between the emitter region and the base region so as to contact the emitter region, an n-type recombination suppressing region around the second high-resistance region so as to adjoin the second high-resistance region, and a p-type low-resistance base contact region which is provided so as to adjoin the recombination suppressing region, and which contacts the base region. Each of doping concentrations of the second high-resistance region and the recombination suppressing region is equal to or lower than 1×1017 cm?3.

Abstract: A semiconductor component is formed using the following processes: (a) forming a first dielectric layer over the semiconductor substrate; (b) forming a base electrode for the bipolar transistor over the dielectric layer; (c) forming an oxide nitride structure over the base electrode; (d) forming a first spacer adjacent to the oxide nitride structure and the base electrode; (e) removing a top layer of the oxide nitride structure; (f) removing a first portion of the dielectric layer; (g) forming an epitaxial layer over the semiconductor substrate; (h) forming a second spacer over the epitaxial layer; and (i) forming an emitter electrode over the epitaxial layer and adjacent to the second spacer.

Abstract: Provided are a MIT device self-heating preventive-circuit that can solve a self-heating problem of a MIT device and a method of manufacturing a MIT device self-heating preventive-circuit integrated device. The MIT device self-heating preventive-circuit includes a MIT device that generates an abrupt MIT at a temperature equal to or greater than a critical temperature and is connected to a current driving device to control the flow of current in the current driving device, a transistor that is connected to the MIT device to control the self-heating of the MIT device after generating the MIT in the MIT device, and a resistor connected to the MIT device and the transistor.

Abstract: A method of manufacturing a bipolar transistor is compatible with FinFET processing. A collector region (18) is formed and patterned, base contact regions (26) formed on either side, and a gap formed between the base contact region. A base (28), spacers (30) and an emitter (32) are formed in the gap.

Abstract: A bipolar semiconductor device and method are provided. One embodiment provides a bipolar semiconductor device including a first semiconductor region of a first conductivity type having a first doping concentration, a second semiconductor region of a second conductivity type forming a pn-junction with the first semiconductor region, and a plurality of third semiconductor regions of the first conductivity type at least partially arranged in the first semiconductor region and having a doping concentration which is higher than the first doping concentration. Each of the third semiconductor regions is provided with at least one respective junction termination structure.

Abstract: A process for manufacturing an array of bipolar transistors, wherein deep field insulation regions of dielectric material are formed in a semiconductor body, thereby defining a plurality of active areas, insulated from each other and a plurality of bipolar transistors are formed in each active area. In particular, in each active area, a first conduction region is formed at a distance from the surface of the semiconductor body; a control region is formed on the first conduction region; and, in each control region, at least two second conduction regions and at least one control contact region are formed. The control contact region is interposed between the second conduction regions and at least two surface field insulation regions are thermally grown in each active area between the control contact region and the second conduction regions.

Abstract: The invention relates to a method of manufacturing a bipolar transistor on a semiconductor substrate (11) which is provided with a first, a second and a third layer (1,2,3) of a first, second and third semiconductor material respectively, all of a first conductivity type. A first portion of the second layer (2) is transformed into a buried isolation region (15) comprising a first electrically insulating material. A first semiconductor region (6) of the first conductivity type, comprising, for example, a collector region, is formed from a second portion of the second layer (2) adjoining the buried isolation region (15) and a portion of the first layer (1) adjoining the second portion of the second layer (2). Then a base region (7) is formed on the buried isolation region (15) and on the first semiconductor region (6) by transforming the third layer (3) into a second conductivity type, which is opposite to the first conductivity type.

Abstract: In a conventional semiconductor device, part of a dielectric film of a capacitive element is removed when photoresist is peeled off, and this causes problems of variation in capacitance value of the capacitive element and deterioration of breakdown voltage characteristics. In a semiconductor device according to the present invention, a silicon nitride film serving as a dielectric film is formed on the top face of a lower electrode of a capacitive element, and an upper electrode is formed on the top face of the silicon nitride film. The upper electrode is formed of a laminated structure having a silicon film and a polysilicon film protecting the silicon nitride film. This structure prevents part of the silicon nitride film from being removed when, for example, photoresist is peeled off, thereby preventing variation in capacitance value of the capacitive element and deterioration of the breakdown voltage characteristics.

Abstract: Electrostatic discharge (ESD) protection clamps (61, 95) for I/O terminals (22, 23) of integrated circuit (IC) cores (24) comprise a bipolar transistor (25) with an integrated Zener diode (30) coupled between the base (28) and collector (27) of the transistor (25). Prior art variations (311, 312, 313, 314) in clamp voltage in different parts of the same IC chip or wafer caused by prior art deep implant geometric mask shadowing are avoided by using shallow implants (781, 782) and forming the base (28, 68) coupled anode (301, 75) and collector (27, 70, 64) coupled cathode (302, 72) of the Zener (30) using opposed edges (713, 714) of a single relatively thin mask (71, 71?). The anode (301, 75) and cathode (302, 72) are self-aligned and the width (691) of the Zener space charge region (69) therebetween is defined by the opposed edges (713, 714) substantially independent of location and orientation of the ESD clamps (61, 95) on the die or wafer.

Abstract: A bipolar transistor has a base with an epitaxial base layer and a raised base connection region which in a lateral direction in parallel relationship with the substrate surface encloses the emitter which is surrounded by a spacer of insulating material. The epitaxial base layer is raised in a heightwise direction perpendicularly to the substrate surface. An emitter of a T-shaped cross-sectional profile is separated laterally from the outer base portion by a spacer of insulating material. Its vertical bar of the T-shape adjoins with its lower end the inner base portion.

Abstract: An object of the present invention is to provide a semiconductor resistive element having excellent linearity. A semiconductor device according to the present invention includes a HBT which is formed on a GaAs substrate and includes a group III-V compound semiconductor, and a semiconductor resistive element made of at least one layer included in a semiconductor epitaxial layer included in the HBT, and the semiconductor resistive element includes helium impurities.

Abstract: A method of fabricating a hetero-junction bipolar transistor (HBT) is disclosed, where the HBT has a structure incorporating a hetero-junction bipolar structure disposed on a substrate including of silicon crystalline orientation <110>. The hetero-junction bipolar structure may include an emitter, a base and a collector. The substrate may include a shallow-trench-isolation (STI) region and a deep trench region on which the collector is disposed. The substrate may include of a region of silicon crystalline orientation <100> in addition to silicon crystalline orientation <110> to form a composite substrate by using hybrid orientation technology (HOT). The region of crystalline orientation <100> may be disposed on crystalline orientation <110>. Alternatively, the region of silicon crystalline orientation <110> may be disposed on crystalline orientation <100>.

Abstract: In a semiconductor chip in which LDMOSFET elements for power amplifier circuits used for a power amplifier module are formed, a source bump electrode is disposed on an LDMOSFET formation region in which a plurality of source regions, a plurality of drain regions and a plurality of gate electrodes for the LDMOSFET elements are formed. The source bump electrode is formed on a source pad mainly made of aluminum via a source conductor layer which is thicker than the source pad and mainly made of copper. No resin film is interposed between the source bump electrode and the source conductor layer.

Abstract: In one embodiment, a plurality of ESD devices are used to form an integrated semiconductor filter circuit. Additional diodes are formed in parallel with the ESD structures in order to increase the input capacitance.

Abstract: A wafer comprising at least one emitter-up Heterojunction Bipolar Transistor (HBT) and at least one emitter-down HBT on a common InP based semiconductor wafer. Isolation and N-type implants into the device layers differentiate an emitter-down HBT from an emitter-up HBT. The method for preparing a device comprises forming identical layers for all HBTs and performing ion implantation to differentiate an emitter-down HBT from an emitter-up HBT.

Abstract: A wafer comprising at least one high Ft HBT and at least one high BVceo HBT having various collector profiles on a common III-V compound semiconductor based wafer. The N+ implant in the collector varies the collector profiles of individual HBTs on the wafer. The method for preparing the device comprises forming of HBT layers up to and including collector layer on non-silicon based substrate, performing ion implantation, annealing for implant activation, and forming remaining HBT layers.

Abstract: An electrostatic discharge (ESD) protection circuit includes a substrate, and a plurality of unit bipolar transistors formed in the substrate. Each of the plurality of unit bipolar transistors may include a first-conductivity-type buried layer formed in the substrate, a first-conductivity-type well formed over the first-conductivity-type buried layer, a second-conductivity-type well formed in the first-conductivity-type well, a first-conductivity-type vertical doping layer vertically formed from the surface of the substrate to the first-conductivity-type buried layer so as to surround the first-conductivity-type well, and a first-conductivity-type doping layer and a second conductivity-type doping layer formed in the second-conductivity-type well. The first-conductivity-type doping layer of any one of the adjacent unit bipolar transistors and the first-conductivity-type vertical doping layer of another one of the adjacent unit bipolar transistors may be connected to each other.

Abstract: A semiconductor device can be formed without use of an STI process. An insulating layer is formed over a semiconductor body. Portions of the insulating layer are removed to expose the semiconductor body, e.g., to expose bare silicon. A semiconductor material, e.g., silicon, is grown over the exposed semiconductor body. A device, such as a transistor, can then be formed in the grown semiconductor material.

Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well (240) within a substrate (210) and forming a suppression implant (420) within the substrate (210). The method for manufacturing the zener diode may further include forming a cathode (620) and an anode (520) within the substrate (210), wherein the suppression implant (420) is located proximate the doped well (240) and configured to reduce threading dislocations.

Abstract: An electronic circuit includes a filtering circuit implemented with a distributed inductor-and-capacitor (LC) network that includes metal oxide effect (MOS) trenches opened in a semiconductor substrate filled with dielectric material for functioning as capacitors for the distributed LC network. The electronic circuit further includes a transient voltage suppressing (TVS) circuit integrated with the filtering circuit that functions as a low pass filter wherein the TVS circuit includes a bipolar transistor triggered by a diode disposed in the semiconductor substrate. The distributed LC network further includes metal coils to function as inductors disposed on a top surface of the semiconductor electrically contacting the MOS trenches.

Abstract: A method for fabrication of a monolithically integrated SOI substrate capacitor has the steps of: forming an insulating trench, which reaches down to the insulator and surrounds a region of the monocrystalline silicon of a SOI structure, doping the monocrystalline silicon region, forming an insulating, which can be nitride, layer region on a portion of the monocrystalline silicon region, forming a doped silicon layer region on the insulating layer region, and forming an insulating outside sidewall spacer on the monocrystalline silicon region, where the outside sidewall spacer surrounds the doped silicon layer region to provide an isolation between the doped silicon layer region and exposed portions of the monocrystalline silicon region. The monocrystalline silicon region, the insulating layer region, and the doped silicon layer region constitute a lower electrode, a dielectric, and an upper electrode of the capacitor.

Abstract: A heterojunction bipolar transistor is formed in a semiconductor substrate of a first conductivity type including a collector region. A base region is formed on the substrate and an emitter region is formed over the base region. At least one of the collector, base and emitter regions includes a first region doped with an impurity having a first concentration and a second region doped with the impurity having a second concentration. Noise performance and reliability of the heterojunction bipolar transistor is improved without degrading ac performance.

Abstract: A transient voltage-suppressing (TVS) device supported on a semiconductor substrate is applied to protect an electronic device from a transient voltage. The TVS device includes a clamp diode functions with a high-side and a low side diodes for clamping a transient voltage disposed on a top layer of the semiconductor substrate insulated by a insulation layer constituting a TVS on silicon-on-insulator (SOI) device. In an exemplary embodiment, the insulator layer further includes a thick body oxide (BOX) layer having a thickness in the range of 250 Angstroms to 1 micrometer to sustain an application with a breakdown voltage higher than 25 volts. In another exemplary embodiment, the clamp diode further surrounded by a P-well and the P-well is formed on top of a P?/P+ substrate layer disposed above the insulator layer.

Abstract: According to an exemplary embodiment, a method for integrating a high speed bipolar transistor in a high speed transistor region of a substrate with a high voltage transistor in a high voltage transistor region of the substrate includes forming a buried subcollector in the high speed transistor region of the substrate. The method further includes forming a first high energy implant region in the high voltage transistor region of the substrate, where the first high energy implant region extends to a depth greater than a depth of a peak dopant concentration of the buried subcollector, thereby increasing a collector-to-emitter breakdown voltage of the high voltage transistor. The collector-to-emitter breakdown voltage of the high voltage transistor can be greater than approximately 5.0 volts. The high speed bipolar transistor can have a cutoff frequency of greater approximately 200.0 GHz.

Abstract: An electro static discharge device includes a semiconductor body. The semiconductor body includes a first surface, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type arranged on the first semiconductor region and a third semiconductor region of the first conductivity type. The third semiconductor region is isolated from the first semiconductor region by the second semiconductor region. A resistor structure is arranged in the semiconductor body and comprises at least one trench structure. The resistor structure is arranged at least in the second semiconductor region and provides a high-resistance electrical connection between a first portion and a second portion of the second semiconductor region.

Abstract: Disclosed is a method of fabricating a Schottky barrier diode, which comprises the steps of laminating an N? type epitaxial layer having a thickness of 2 to 4 ?m, on an N+ type substrate layer, to form a semiconductor substrate; forming a P+ type guard ring at a given position of epitaxial layer, from the side of a top surface of the semiconductor substrate; dividing a portion of the epitaxial layer surrounded by the guard ring, into a plurality of unit regions each having one side length of 0.1 to 0.

Abstract: A method of forming a heterojunction bipolar transistor (HBT) device is disclosed.

Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well within a substrate and forming a suppression implant within the substrate. The method for manufacturing the zener diode may further include forming a cathode and an anode within the substrate, wherein the suppression implant is located proximate the doped well and configured to reduce threading dislocations.

Abstract: A bipolar transistor is formed in an integrated BiCMOS process. A buried layer is formed in a semiconductor body. An intrinsic dilute mask is formed over the buried layer that covers at least a portion of a selected region of a target deep well region. The intrinsic dilute mask is employed to implant a dopant into the target deep well region to form a deep well region with the selected region having a lowered dopant concentration. The lowered dopant concentration can yield a higher breakdown voltage for the bipolar device. The intrinsic dilute mask mitigates implantation within the selected region.

Abstract: A method for manufacturing a bipolar transistor comprising: forming a device isolation layer in a device isolation region of a semiconductor substrate having therein first and second well regions having a first conductivity; implanting ions of a second conductivity in the first well to form a third well; forming and patterning a conductive layer on the third well region to form a base electrode pattern; forming a spacer on a sidewalls of the base electrode pattern; implanting first conductivity type ions in the semiconductor substrate to form an emitter region adjacent to the base electrode pattern and form a collector region in the second well region; and performing a diffusion process to form a base region adjacent to the emitter region.

Abstract: An electric discharge device includes a bipolar transistor configuration comprising a base, an emitter, and a collector. At least one pinched resistor is formed in a region comprising both the base and emitter so as to produce a pinched resistive area that develops a voltage once the bipolar transistor experiences junction breakdown.

Abstract: A bipolar transistor is provided which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The bipolar transistor further includes an intrinsic base overlying the upper surface of the collector pedestal, a raised extrinsic base conductively connected to the intrinsic base and an emitter overlying the intrinsic base. In a particular embodiment, the emitter is self-aligned to the collector pedestal, having a centerline which is aligned to the centerline of the collector pedestal.

Abstract: An electrostatic discharge (ESD) protection clamp (61) for I/O terminals (22, 23) of integrated circuits (ICs) (24) comprises an NPN bipolar transistor (25) coupled to an integrated Zener diode (30). Variations in the break-down current-voltage characteristics (311, 312, 313, 314) of multiple prior art ESD clamps (31) in different parts of the same IC chip is avoided by forming the anode (301) of the Zener (30) in the shape of a base-coupled P+ annular ring (75) surrounded by a spaced-apart N+ annular collector ring (70) for the cathode (302) of the Zener (30).

Abstract: A process for manufacturing an array of bipolar transistors, wherein deep field insulation regions of dielectric material are formed in a semiconductor body, thereby defining a plurality of active areas, insulated from each other and a plurality of bipolar transistors are formed in each active area. In particular, in each active area, a first conduction region is formed at a distance from the surface of the semiconductor body; a control region is formed on the first conduction region; and, in each control region, at least two second conduction regions and at least one control contact region are formed. The control contact region is interposed between the second conduction regions and at least two surface field insulation regions are thermally grown in each active area between the control contact region and the second conduction regions.

Abstract: An integrated semiconductor structure includes a heterojunction bipolar transistor and a Schottky diode. The structure has a substrate, the heterojunction bipolar transistor overlying and contacting the substrate, wherein the heterojunction bipolar transistor includes a transistor collector layer, and a Schottky diode overlying the substrate and overlying the transistor collector layer. The Schottky diode includes a Schottky diode barrier layer structure that desirably is not of the same material, doping, and thickness as the transistor collector layer.

Abstract: A bipolar transistor structure includes an intrinsic base layer formed over a collector layer, an emitter formed over the intrinsic base layer, and an extrinsic base layer formed over the intrinsic layer and adjacent the emitter. A ring shaped collector implant structure is formed within an upper portion of the collector layer, wherein the ring shaped collector implant structure is disposed so as to be aligned beneath a perimeter portion of the emitter.

Abstract: The invention includes a device displaying differential negative resistance characterized by a current-versus-voltage profile having a peak-to-valley ratio of at least about 9. The invention also includes a semiconductor construction comprising a substrate, and a first layer over the substrate. The first layer comprises Ge and one or more of S, Te and Se. A second layer is over the first layer. The second layer comprises M and A, where M is a transition metal and A is one or more of O, S, Te and Se. A third layer is over the second layer, and comprises Ge and one or more of S, Te and Se. The first, second and third layers are together incorporated into an assembly displaying differential negative resistance. Additionally, the invention includes methodology for forming assemblies displaying differential negative resistance, such as tunnel diode assemblies.

Abstract: A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.

Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.

Abstract: In order to protect a semiconductor component against overvoltages, the steps which are used for production of bipolar transistors and CMOS structures in the semiconductor component are used for integrated parallel production of a zener diode. This has a first and a second n-doped zone, which extend between the surface of a semiconductor substrate and an n-doped buried region. The first n-doped zone is oppositely doped with p-doping in an area adjacent to the surface, and represents a p-doped region. A first contact is provided to the p-doped region, and a contact is on the other hand provided to the second n-doped zone, with the two contents forming the two connections of the zener diode.

Abstract: Methods of forming and structures of a relatively large bipolar transistor is provided. The method includes forming a collector in a semiconductor region. Forming a base contiguous with a portion of the collector. Forming a plurality of emitters contiguous with portions of the base. Forming a common emitter interconnect and forming ballast emitter resistors for select emitters. Each ballast emitter resistor is coupled between an associated emitter and the common emitter interconnect. Each ballast resistor is further formed to have a selected resistance value. The selected resistance value of each ballast resistor is selected so the values of the ballast resistors vary in a two dimensional direction in relation to a working surface of the bipolar transistor.

Abstract: Method for manufacturing integrated circuits having silicon-germanium heterobipolar transistors, wherein a collector semiconductor region is created, an etch stop layer is created on a connection region, an opening is introduced into this etch stop layer, semiconductor material, which is formed as a single crystal at least in the collector semiconductor region above the opening, is applied over the etch stop layer and over the opening. Before etching of the semiconductor material, a masking layer is applied above the collector semiconductor region to the semiconductor material, which protects the collector semiconductor region from the etching. Afterwards the semiconductor material is etched to the depth of the etch stop layer, the etch stop layer acting as an etch stop such that reaching an interface between the semiconductor material and the etch stop layer is detected during the etching and the etching is stopped depending on the detection.

Abstract: A bipolar transistor includes a collector located over a substrate; and a heat conductive path connecting the substrate to the collector. The heat conductive path is filled with a heat conductive material such as metal or polysilicon. In one embodiment the heat conductive path runs through the collector to extract heat from the collector and drain it to the substrate. In alternate embodiments, the transistor can be a vertical or a lateral device. According to another embodiment, an integrated circuit using BiCMOS technology comprises pnp and npn bipolar transistors with heat conduction from collector to substrate and possibly p-channel and n-channel MOSFETS. According to yet another embodiment, a method for making a transistor in an integrated network comprises steps of etching the heat conducting path through the collector and to the substrate and fill with heat conductive material to provide a heat drain for the transistor comprising the collector.

Abstract: A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the first doped region collectively form a parasitic bipolar junction transistor (BJT), and wherein the first well is the collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter of the BJT.

Abstract: A method for manufacturing a bipolar transistor includes: forming a device isolation layer on a semiconductor substrate having first and second well regions of a first conductivity therein; implanting ions of a second conductivity in the first well to form a third well; forming and patterning a conductive layer on the semiconductor substrate; forming an emitter electrode pattern on the third well region, and forming a collector electrode pattern on the second well region; forming spacers at sidewalls of the emitter and collector electrode patterns; performing a diffusion process to form an emitter region of a first conductivity on the third well region and to form a collector region of a first conductivity on the second well region; implanting ions of a second conductivity in the third well region to form a base region; and removing the emitter electrode and collector region patterns.