Gate Programmed, E.g., Different Gate Material Or No Gate (epo) Patents (Class 257/E21.674)
  • Patent number: 8076729
    Abstract: Disclosed is a method for forming a dual gate electrode of a semiconductor device, which may improve manufacturing productivity by simplifying a process of forming gate electrodes in PMOS and NMOS regions, respectively, and may provide improvement in performance by making the two gate electrodes have a different thickness and material state in a manner that one of the two gate electrodes has a single-layer structure and the other one has a two-layer structure.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: December 13, 2011
    Assignee: Dongbu Hitek Co., Ltd
    Inventor: Eun Sang Cho