With Source And Drain On Same Level, E.g., Lateral Channel (epo) Patents (Class 257/E21.668)
  • Patent number: 10043852
    Abstract: According to one embodiment, a magnetoresistive memory device includes first electrodes located in an interlayer insulating film, second electrodes located on the respective first electrodes within the interlayer insulating film, magnetoresistive effect elements on the respective second electrodes, and third electrodes on the respective magnetoresistive effect elements. The first electrodes and the second electrodes are displaced from each other.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: August 7, 2018
    Inventor: Hiroyuki Kanaya
  • Patent number: 9911605
    Abstract: A method of forming fine patterns includes forming pillars arrayed in rows and columns on an underlying layer and forming a spacer layer on the underlying layer to cover the pillars. Portions of the spacer layer respectively covering the pillars arrayed in each row or in each column are in contact with each other to provide first interstitial spaces disposed between the pillars arrayed in a diagonal direction between a row direction and a column direction as well as to provide cleavages at corners of each of the first interstitial spaces in a plan view. A healing layer is formed on the spacer layer to fill the cleavages of the first interstitial spaces. The healing layer is formed to provide second interstitial spaces respectively located in the first interstitial spaces as well as to include a polymer material.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: March 6, 2018
    Assignee: SK Hynix Inc.
    Inventors: Jung Gun Heo, Hong Ik Kim, Keun Do Ban, Cheol Kyu Bok, Young Sik Kim
  • Patent number: 9837272
    Abstract: In a method of manufacturing a semiconductor device, a mask layer and a first layer may be sequentially formed on a substrate. The first layer may be patterned by a photolithography process to form a first pattern. A silicon oxide layer may be formed on the first pattern. A coating pattern including silicon may be formed on the silicon oxide layer. The mask layer may be etched using a second pattern as an etching mask to form a mask pattern, and the second pattern may includes the first pattern, the silicon oxide layer and the coating pattern. The mask pattern may have a uniform size.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: December 5, 2017
    Inventors: Su-Min Park, Su-Min Kim, Hyo-Jin Yun, Hyun-Woo Kim, Kyoung-Seon Kim, Hai-Sub Na, Min-Ju Park, So-Ra Han
  • Patent number: 8658526
    Abstract: A method is provided that includes forming completely distinct first features above a substrate, forming sidewall spacers on the first features, filling spaces between adjacent sidewall spacers with filler features, and removing the sidewall spacers. Numerous other aspects are provided.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: February 25, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Huiwen Xu, Yung-Tin Chen, Steven J. Radigan
  • Patent number: 8575015
    Abstract: One embodiment relates to an integrated circuit that includes a lateral trench MOSFET disposed in a semiconductor body. The lateral trench MOSFET includes source and drain regions having a body region therebetween. A gate electrode region is disposed in a trench that extends beneath the surface of the semiconductor body at least partially between the source and drain. A gate dielectric separates the gate electrode region from the semiconductor body. In addition, a field plate region in the trench is coupled to the gate electrode region, and a field plate dielectric separates the field plate region from the semiconductor body. Other integrated circuits and methods are also disclosed.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: November 5, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Marie Denison
  • Patent number: 8357606
    Abstract: A method of making a semiconductor device includes forming a layer over a substrate, forming a plurality of spaced apart features of imagable material over the layer, forming sidewall spacers on the plurality of features and filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature. The method also includes removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the layer using the first feature, the filler feature and the second feature as a mask.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: January 22, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Yung-Tin Chen, Steven J. Radigan
  • Patent number: 7550344
    Abstract: A semiconductor device includes: a lower hydrogen-barrier film; a capacitor formed on the lower hydrogen-barrier film and including a lower electrode, a capacitive insulating film, and an upper electrode; an interlayer dielectric film formed so as to cover the periphery of the capacitor; and an upper hydrogen-barrier film covering the top and lateral portions of the capacitor. An opening, which exposes the lower hydrogen-barrier film where the lower hydrogen-barrier film is located around the capacitor, and which is tapered and flares upward, is formed in the interlayer dielectric film, and the upper hydrogen-barrier film is formed along the lateral and bottom faces of the opening, and is in contact with the lower hydrogen-barrier film in the opening.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: June 23, 2009
    Assignee: Panasonic Corporation
    Inventors: Toyoji Ito, Eiji Fujii, Kazuo Umeda
  • Patent number: 7402476
    Abstract: An electronic device is formed by forming a first and second layer overlying a plurality of transistor locations. An etch is performed to remove portions of the first and second layers to expose a portion of the plurality of transistor locations, while other portions of the first and second layer remain to protect other transistor locations. Subsequently, source/drain locations of the exposed transistor locations are etched along with the remaining portion of the second layer. The etch is substantially terminated by removing the portion of the second layer using an end-point detection technique involving the first layer. Subsequently an epitaxial layer is formed in the source/drain recesses to provide stress on a channel region of the transistor locations.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: July 22, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Marius K. Orlowski, Brian J. Goolsby
  • Publication number: 20080087935
    Abstract: A semiconductor device includes an element isolation region formed in the surface of a semiconductor substrate, a plurality of memory cell transistors having respective gate electrodes formed in an element forming region and a selective gate transistor located at an end of a row of a predetermined number of the memory cell transistors. The element isolation insulating film formed at a part of the element isolation region adjacent to the selective gate transistor includes a first insulating film comprised of a coating oxide film buried in the trench so as to cover an inner part of the trench from a bottom of the trench to a predetermined depth and a second insulating film which is formed so as to cover the upper side of the first insulating film and the sidewall of the trench and has resistance to a wet etching process.
    Type: Application
    Filed: July 2, 2007
    Publication date: April 17, 2008
    Inventor: Koichi MATSUNO
  • Publication number: 20080084744
    Abstract: A memory device, and method of making and operating the same, including a substrate of semiconductor material of a first conductivity type, first and second spaced apart regions in the substrate of a second conductivity type with a channel region therebetween, an electrically conductive floating gate having a first portion disposed over and insulated from the channel region and a second portion disposed over and insulated from the first region and including a sharpened edge, an electrically conductive P/E gate having a first portion disposed over and insulated from the first region and a second portion extending up and over the floating gate second portion and insulated therefrom by a first layer of insulation material, and an electrically conductive select gate having a first portion disposed laterally adjacent to the floating gate and disposed over and insulated from the channel region.
    Type: Application
    Filed: December 4, 2007
    Publication date: April 10, 2008
    Inventors: Pavel Klinger, Amitay Levi