Floating Gate Layer Used For Peripheral Fet (epo) Patents (Class 257/E21.687)
  • Patent number: 8877585
    Abstract: A method of making a semiconductor structure using a substrate having a non-volatile memory (NVM) portion, a first high voltage portion, a second high voltage portion and a logic portion, includes forming a first conductive layer over an oxide layer on a major surface of the substrate in the NVM portion, the first and second high voltage portions, and logic portion. A memory cell is fabricated in the NVM portion while the first conductive layer remains in the first and second high voltage portions and the logic portion. The first conductive layer is patterned to form transistor gates in the first and second high voltage portions. A protective mask is formed over the NVM portion and the first and second high voltage portions. A transistor gate is formed in the logic portion while the protective mask remains in the NVM portion and the first and second high voltage portions.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: November 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Asanga H. Perera, Cheong Min Hong, Sung-Taeg Kang
  • Patent number: 8786006
    Abstract: A graded composition, high dielectric constant gate insulator is formed between a substrate and floating gate in a flash memory cell transistor. The gate insulator comprises amorphous germanium or a graded composition of germanium carbide and silicon carbide. If the composition of the gate insulator is closer to silicon carbide near the substrate, the electron barrier for hot electron injection will be lower. If the gate insulator is closer to the silicon carbide near the floating gate, the tunnel barrier can be lower at the floating gate.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: July 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Patent number: 8357966
    Abstract: According to one embodiment, a semiconductor device comprises an active area extending in a first direction, a contact plug located on a first portion of the active area, and a transistor located on a second portion adjacent to the first portion of the active area in the first direction. A width of a top surface area of the first portion in a second direction perpendicular to the first direction is smaller than that of a top surface area of the second portion in the second direction.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: January 22, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Aya Minemura, Kenji Sawamura, Mitsuhiro Noguchi
  • Patent number: 8324050
    Abstract: A method of manufacturing a flash memory device comprises forming a gate insulating layer on a semiconductor substrate, forming silicon seed crystals on a surface of the gate insulating layer by reacting a nitrogen or oxygen atmosphere gas and a silicon source gas, forming a first layer for a floating gate over the gate insulating layer and the silicon seed crystals by increasing an amount of the silicon source gas, and forming a second layer for a floating gate on the first layer for a floating gate.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: December 4, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jae Mun Kim
  • Patent number: 8288800
    Abstract: A method of forming a device is disclosed. The method includes providing a substrate having an active area. A gate is formed on the substrate. First and second current paths through the gate are formed. The first current path serves a first purpose and the second current path serves a second purpose. The gate controls selection of the current paths.
    Type: Grant
    Filed: January 4, 2010
    Date of Patent: October 16, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Ming Zhu, Chun Shan Yin, Elgin Quek, Shyue Seng Tan
  • Patent number: 8258569
    Abstract: A plurality of NAND cells are arranged in a cell array. In each of the NAND cells, a pair of selection gate transistors is connected in series to a plurality of memory cell transistors. An inter-gate connection trench is formed in an insulating film between layers of stacked gates of the selection gate transistors. The stacked gates are electrically connected to each other. At an end part of the cell array in the row direction, an STI area is formed, and dummy NAND cells are formed at an end part in the row direction. A dummy selection gate transistor is connected in series to a plurality of dummy memory cell transistors. No inter-gate connection trench is present in an insulating film between layers of stacked gates of the dummy selection gate transistor, and the stacked gates of the dummy selection gate transistor are not electrically connected to each other.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: September 4, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masanori Hatakeyama, Osamu Ikeda
  • Patent number: 8198156
    Abstract: A non-volatile memory device includes a peripheral circuit region and a cell region. A method for fabricating the non-volatile memory device includes forming gate patterns over a substrate, the gate pattern including a tunnel insulation layer, a floating gate electrode, a charge blocking layer and a control gate electrode, and removing the control gate electrode and the charge blocking layer of the gate pattern formed in the peripheral circuit region.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: June 12, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Nam-Jae Lee
  • Patent number: 8163608
    Abstract: Methods of fabricating a nonvolatile memory device include forming a trench mask pattern on a semiconductor substrate including a first region and a second region. Substrate trenches defining active regions are formed in the semiconductor substrate in the first region and the second region using the trench mask pattern as a mask. Device isolation layer patterns are formed on the semiconductor substrate including the trench mask pattern and substrate trenches. The device isolation patterns fill the substrate trenches in the first region and in the second region. First and second openings are formed exposing top surfaces of the corresponding active regions in the first and second regions by removing the trench mask pattern. The second opening has a greater width than the first opening. A first lower conductive pattern is formed in the first opening and has a bottom portion in a lower region of the first opening and an extended portion extending from the bottom portion to an upper region of the first opening.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: April 24, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-Tae Park, Jeong-Hyuk Choi
  • Patent number: 8093631
    Abstract: A non-volatile memory device and a method for fabricating the same are provided. The method includes: forming a gate structure on a substrate, the gate structure including a first insulation layer, a first electrode layer for a floating gate and a second insulation layer; forming a third insulation layer on the gate structure covering predetermined regions of the substrate adjacent to the gate structure; and forming a second electrode layer for a control gate on the third insulation layer disposed on sidewalls of the gate structure and the predetermined regions of the substrate.
    Type: Grant
    Filed: August 11, 2008
    Date of Patent: January 10, 2012
    Assignee: Magnachip Semiconductor, Ltd.
    Inventor: Yong-Sik Jeong
  • Patent number: 8076713
    Abstract: A non-volatile memory device includes a substrate having a first region and a second region. A first gate electrode is disposed on the first region. A multi-layered charge storage layer is interposed between the first gate electrode and the substrate, the multi-layered charge storage including a tunnel insulation, a trap insulation, and a blocking insulation layer which are sequentially stacked. A second gate electrode is placed on the substrate of the second region, the second gate electrode including a lower gate and an upper gate connected to a region of an upper surface of the lower gate. A gate insulation layer is interposed between the second gate electrode and the substrate. The first gate electrode and the upper gate of the second gate electrode comprise a same material.
    Type: Grant
    Filed: April 13, 2009
    Date of Patent: December 13, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Hyun Lee, Kyu-Charn Park
  • Patent number: 8043924
    Abstract: In a method of forming a phase-change memory unit, a conductive layer is formed on a substrate having a trench. The conductive layer is planarized until the substrate is exposed to form a first electrode. A spacer partially covering the first electrode is formed. A phase-change material layer is formed on the first electrode and the second spacer. A second electrode is formed on the phase-change material layer. Reset/set currents of the phase-change memory unit may be reduced and deterioration of the phase-change material layer may be reduced and/or prevented.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: October 25, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Chang Ryoo, Hong-Sik Jeong, Gi-Tae Jeong, Jung-Hoon Park, Yoon-Jong Song
  • Patent number: 7998809
    Abstract: An improved process forming a floating gate region of a semiconductor memory device. The process includes using a ceria slurry for chemical mechanical planarization to provide “stop on polysilicon” capabilities, allowing a thin nitride layer, or in the alternative no nitride layer, to be used and reducing the number of processing steps required to form the floating gate region.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: August 16, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Naga Chandrasekaran
  • Patent number: 7998811
    Abstract: A semiconductor device includes a semiconductor substrate, a memory cell region provided on the semiconductor substrate, a word line provided on the memory cell region, a first gate insulating film provided in the memory cell region beneath the word line, a first floating gate electrode provided on the first gate insulating film, a second gate insulating film provided in the memory cell region beneath the word line, the second gate insulating film being different from the first gate insulating film in thickness, and a second floating gate electrode provided on the second gate insulating film.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: August 16, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinya Takahashi
  • Patent number: 7897456
    Abstract: A non-volatile memory device includes a peripheral circuit region and a cell region. A method for fabricating the non-volatile memory device includes forming gate patterns over a substrate, the gate pattern including a tunnel insulation layer, a floating gate electrode, a charge blocking layer and a control gate electrode, and removing the control gate electrode and the charge blocking layer of the gate pattern formed in the peripheral circuit region.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: March 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Nam-Jae Lee
  • Patent number: 7869279
    Abstract: A memory device including a plurality of memory cells, each with access and program PMOS transistors situated in a common N-Well formed in a P-substrate, and an n-erase pocket formed directly in the P-substrate. Each cell includes a program PMOS including gate, and first and second P+ regions formed in an N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. Each cell further comprises an access PMOS including a gate, and first and second P+ regions formed within the same n-doped well as the first and second P+ regions of the program PMOS, wherein the first P+ region is electrically connected to the second P+ region of the program PMOS, and the gate is electrically connected to a corresponding word line. Each cell further includes an n-doped erase pocket including gate, and first and second N+ regions electrically connected to a corresponding erase line, and the gate is electrically connected to the gate of the program PMOS, forming the floating gate of the cell.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: January 11, 2011
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Kola Nirmal Ratnakumar
  • Patent number: 7863133
    Abstract: Non-volatile memory cell structures are described that are formed by a method including forming a first oxide layer on a horizontal strained substrate, forming at least one first recess through the first oxide layer to the strained substrate, and forming at least one vertical epitaxial structure in the recess. A crystal lattice of the vertical epitaxial structure is aligned with a crystal lattice of the strained substrate.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: January 4, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Lyle Jones
  • Patent number: 7575972
    Abstract: A method of manufacturing a nonvolatile memory device is disclosed. The method includes the steps of forming a tunnel oxide layer, a first conductive layer for a floating gate, and a hard mask layer over a semiconductor substrate, etching a portion of the hard mask layer, the first conductive layer, the tunnel oxide layer and the semiconductor substrate, forming trenches, gap-filling the trenches with an insulating material to form isolation layers, removing the hard mask layer, forming second conductive layer for a floating gate on the entire surface, forming spacers on vertical faces of the second conductive layer, removing the second conductive layer on the isolation layers and between the spacers by means of an etch process using the spacers as etch masks, removing the spacers, and forming a dielectric layer and a third conductive layer on the entire surface including the second conductive layer.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: August 18, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Cha Deok Dong
  • Patent number: 7553726
    Abstract: A method of fabricating nonvolatile memory devices may involve forming separate floating gates on a semiconductor substrate, forming control gates on the semiconductor substrate, conformally forming a buffer film on a surface of the semiconductor substrate, injecting ions into the semiconductor substrate between the pairs of the floating gates to form a common source region partially overlapping each floating gate of the respective pair of the floating gates, depositing an insulating film on the buffer film, etching the buffer film and the insulating film at side walls of the floating gates and the control gates to form spacers at the side walls of the floating gates and the control gates, and forming a drain region in the semiconductor substrate at a side of the control gate other than a side of the control gate where the common source region is formed.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: June 30, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-gu Yoon, Chul-soon Kwon, Jae-won Um, Jung-ho Moon
  • Patent number: 7544989
    Abstract: A first plurality of memory cells is in a first plane in a first column of the array. A second plurality of memory cells is in a second plane in the same column. The second plurality of memory cells are coupled to the first plurality of memory cells through a series connection of their source/drain regions.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: June 9, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Patent number: 7524747
    Abstract: Disclosed herein is a method of forming a floating gate in a non-volatile memory device having a self-aligned shallow trench isolation (SA-STI) structure. First, a tunnel oxide layer is formed on a semiconductor substrate having a SA-STI structure. Next, a first floating gate layer is formed on the tunnel oxide layer at a first temperature of no less than about 530° C. A second floating gate layer is then formed on the first floating gate layer at a second temperature of no more than 580° C. After depositing the first floating gate layer, the second floating gate layer is in-situ deposited to prevent the growth of a native oxide layer on the surface of the first floating gate layer. Thus, gate resistance can be reduced and process time can be shortened.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: April 28, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Sub You, Hun-Hyeoung Leam, Sang-Hoon Lee
  • Patent number: 7456060
    Abstract: A nonvolatile memory device includes a floating gate formed on a tunnel oxide layer that is on a semiconductor substrate. The device also includes a drain region formed in the substrate adjacent to one side of the floating gate, a source region formed adjacent to another side of the floating gate. The source region is apart from the floating gate, and an inter-gate insulating layer formed on a portion of an active region between the source region and the floating gate and on a sidewall of the floating gate directing toward the source region, and on a sidewall of the floating gate directing toward the drain region. The device includes a word line formed over the floating gate and being across the substrate in one direction, and a field oxide layer interposing between the word line and the source region.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: November 25, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Heong Jin Kim
  • Patent number: 7439134
    Abstract: A method for making a semiconductor device having non-volatile memory cell transistors and transistors of another type is provided. In the method, a substrate is provided having an NVM region, a high voltage (HV) region, and a low voltage (LV) region. The method includes forming a gate dielectric layer on the HV and LV regions. A tunnel oxide layer is formed over the substrate in the NVM region and the gate dielectric in the HV and LV regions. A first polysilicon layer is formed over the tunnel dielectric layer and gate dielectric layer. The first polysilicon layer is patterned to form NVM floating gates. An ONO layer is formed over the first polysilicon layer. A single etch removal step is used to form gates for the HV transistors from the first polysilicon layer while removing the first polysilicon layer from the LV region.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: October 21, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Erwin J. Prinz, Mehul D. Shroff
  • Patent number: 7371640
    Abstract: The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method includes providing a semiconductor substrate having a nonvolatile memory region, a first region, and a second region. A triple layer composed of a tunnel oxide layer, a charge storing layer and a first deposited oxide layer on the semiconductor substrate is formed sequentially. The triple layer on the semiconductor substrate except the nonvolatile memory region is then removed. A second deposited oxide layer is formed on an entire surface of the semiconductor substrate including the first and second regions from which the triple layer is removed. The second deposited oxide layer on the second region is removed, and a first thermal oxide layer is formed on the entire surface of the semiconductor substrate including the second region from which the second deposited oxide layer is removed.
    Type: Grant
    Filed: March 17, 2006
    Date of Patent: May 13, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Su Kim, Kwang-Wook Koh, Geum-Jong Bae, Ki-Chul Kim, Sung-Ho Kim, Jin-Hee Kim, In-Wook Cho
  • Patent number: 7223657
    Abstract: Methods of fabricating a floating gate of a flash memory cell are provided in which a first polysilicon layer is formed between first and second isolation layers. An upper region of the first polysilicon layer is then oxidized. The oxidized upper region of the first polysilicon layer is subsequently removed. A second polysilicon layer is formed on the first polysilicon layer. The second polysilicon layer and the first polysilicon layer are patterned to form the floating gate.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: May 29, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Jun Jang, Jung-Hwan Kim, Jai-Dong Lee, Young-sub You, Sang-Hun Lee, Hun-Hyeoung Leam