Including One Type Of Peripheral Fet (epo) Patents (Class 257/E21.684)
  • Patent number: 9793125
    Abstract: A semiconductor device includes a polysilicon substrate, a first oxide layer formed on the polysilicon substrate, an oxygen-rich nitride layer formed on the first oxide layer, a second oxide layer formed on the oxygen-rich nitride layer, and an oxygen-poor nitride layer formed on the second oxide layer.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: October 17, 2017
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Fredrick B. Jenne, Krishnaswamy Ramkumar
  • Patent number: 9748103
    Abstract: A semiconductor device includes a polysilicon substrate, a first oxide layer formed on the polysilicon substrate, an oxygen-rich nitride layer formed on the first oxide layer, a second oxide layer formed on the oxygen-rich nitride layer, and an oxygen-poor nitride layer formed on the second oxide layer.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: August 29, 2017
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Fredrick B. Jenne, Krishnaswamy Ramkumar
  • Patent number: 8877585
    Abstract: A method of making a semiconductor structure using a substrate having a non-volatile memory (NVM) portion, a first high voltage portion, a second high voltage portion and a logic portion, includes forming a first conductive layer over an oxide layer on a major surface of the substrate in the NVM portion, the first and second high voltage portions, and logic portion. A memory cell is fabricated in the NVM portion while the first conductive layer remains in the first and second high voltage portions and the logic portion. The first conductive layer is patterned to form transistor gates in the first and second high voltage portions. A protective mask is formed over the NVM portion and the first and second high voltage portions. A transistor gate is formed in the logic portion while the protective mask remains in the NVM portion and the first and second high voltage portions.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: November 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Asanga H. Perera, Cheong Min Hong, Sung-Taeg Kang
  • Patent number: 8048757
    Abstract: A method for fabricating a capacitor includes forming an isolation layer over a cell region and a peripheral region of a substrate. The isolation layer forms a plurality of open regions in the cell region. Storage nodes are formed on surfaces of the open regions. An upper portion of the isolation layer is etched to expose upper outer walls of the storage nodes. A sacrificial pattern is formed over the isolation layer to enclose the upper outer walls of the storage nodes. The isolation layer in the peripheral region is etched to expose side portions of the resulting structure obtained after forming the sacrificial pattern in the cell region. With the sacrificial pattern supporting the storage nodes, the isolation layer in the cell region is removed. The sacrificial pattern is then removed.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jae-Sung Roh, Kee-Jeung Lee, Han-Sang Song, Seung-Jin Yeom, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim
  • Patent number: 7869279
    Abstract: A memory device including a plurality of memory cells, each with access and program PMOS transistors situated in a common N-Well formed in a P-substrate, and an n-erase pocket formed directly in the P-substrate. Each cell includes a program PMOS including gate, and first and second P+ regions formed in an N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. Each cell further comprises an access PMOS including a gate, and first and second P+ regions formed within the same n-doped well as the first and second P+ regions of the program PMOS, wherein the first P+ region is electrically connected to the second P+ region of the program PMOS, and the gate is electrically connected to a corresponding word line. Each cell further includes an n-doped erase pocket including gate, and first and second N+ regions electrically connected to a corresponding erase line, and the gate is electrically connected to the gate of the program PMOS, forming the floating gate of the cell.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: January 11, 2011
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Kola Nirmal Ratnakumar
  • Patent number: 7560342
    Abstract: Embodiments relate to a method of manufacturing a semiconductor device that may simplify a manufacturing process and may reduce process costs. According to embodiments, the method may include simultaneously forming a first gate of a first device area and a second gate of a second device area, patterning a PMD layer to form a first contact hole exposing the first gate, depositing and planarizing a high dielectric constant material and first and second metallic materials on the semiconductor substrate to expose PMD layer, forming an insulating layer, a metal layer and a third gate in the first contact hole, patterning the PMD layer to form a second contact hole exposing the second gate, and depositing a third metallic material on the semiconductor substrate and planarizing it such that the PMD layer is exposed, thereby forming a contact in the second contact hole.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: July 14, 2009
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Kun Hyuk Lee
  • Patent number: 7491657
    Abstract: Provided is an erasable and programmable read only memory (EPROM) device in which a plasma enhanced oxide (PEOX) film covers an upper surface of a floating gate in a single poly one time programmable (OTP) cell and a method of manufacturing a semiconductor device having the same. The semiconductor device comprises a substrate having an OTP cell region, on which a floating gate is formed for making an OTP cell transistor, and a main chip region, on which a gate of a transistor is formed. A PEOX film is formed on the OTP cell region and the main chip region. The PEOX film covers the floating gate in a close state and covers the gate by a predetermined distance. A silicon oxy nitride (SiON) film Is interposed between the gate and the PEOX film in the main chip region.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: February 17, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Hyung Lee, Seung-Han Yoo
  • Patent number: 7468302
    Abstract: A method of forming a trench type isolation film of a semiconductor device, including the steps of sequentially forming a pad oxide film and a nitride film for a hard mask on a semiconductor substrate in which a cell region and a peri region are defined; patterning the nitride film using an etch process employing a cell array mask; coating a photoresist on the entire structure including the patterned nitride film; patterning the photoresist using a peri ISO mask; sequentially etching the nitride film, the pad oxide film, and the semiconductor substrate using the patterned photoresist as an etch mask, thereby forming first trenches; stripping the photoresist; etching the semiconductor substrate of the cell region and the peri region using the patterned nitride film as an etch mask, thereby forming second trenches in the cell region and third trenches, which are consecutive to the first trenches, in the peri region; and, forming an isolation film within the second and third trenches.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: December 23, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyeon Sang Shin
  • Patent number: 7465630
    Abstract: A method for manufacturing a flash memory device including the steps of forming a gate oxide film for high voltage on the whole surface of a semiconductor substrate on which a cell region, a low voltage region and a high voltage region have been formed, etching the gate oxide film for high voltage formed in the cell region and the low voltage region by a predetermined depth, by forming photoresist patterns to expose the gate oxide film for high voltage formed in the cell region and the low voltage region, and performing a wet etching process using the photoresist patterns as an etching mask, removing the entire gate oxide film for high voltage formed in the cell region and the low voltage region, by performing a cleaning process on the resulting structure, removing the photoresist patterns, forming a floating gate electrode and a control gate electrode, by sequentially forming a tunnel oxide film, a first polysilicon film, a second polysilicon film, a dielectric film, a third polysilicon film and a metal sili
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: December 16, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young Bok Lee
  • Patent number: 7462904
    Abstract: A non-volatile memory device includes an upwardly protruding fin disposed on a substrate and a control gate electrode crossing the fin. A floating gate is interposed between the control gate electrode and the fin and includes a first storage gate and a second storage gate. The first storage gate is disposed on a sidewall of the fin, and the second storage gate is disposed on a top surface of the fin and is connected to the first storage gate. A first insulation layer is interposed between the first storage gate and the sidewall of the fin, and a second insulation layer is interposed between the second storage gate and the top surface of the fin. The second insulation layer is thinner than the first insulation layer. A blocking insulation pattern is interposed between the control gate electrode and the floating gate.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: December 9, 2008
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Seong-Gyun Kim, Ji-Hoon Park, Sang-Woo Kang, Sung-Woo Park
  • Publication number: 20080142860
    Abstract: A system-on-chip semiconductor circuit includes a logic circuit having at least one first transistor with a thin gate dielectric, at least one dynamic random access memory cell coupled with the logic circuit having at least one storage capacitor and at least one thick gate dielectric access transistor, and an analog circuit operable with the logic circuit and the memory cell having at least one thick gate dielectric switched transistor and at least one switched capacitor, wherein the storage capacitors of the memory cell and the switched transistors are of the same type, and wherein the thick gate dielectric switched transistor and the switched capacitor of the analog circuit are made by a process for making the dynamic random access memory cell.
    Type: Application
    Filed: December 13, 2006
    Publication date: June 19, 2008
    Inventors: Kun Lung Chen, Shine Chung
  • Patent number: 7195976
    Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistor can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: March 27, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Tetsuo Adachi, Masataka Kato, Toshiakl Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
  • Patent number: 7166510
    Abstract: A method for manufacturing a flash memory device including the steps of forming a gate oxide film for high voltage on the whole surface of a semiconductor substrate on which a cell region, a low voltage region and a high voltage region have been formed, etching the gate oxide film for high voltage formed in the cell region and the low voltage region by a predetermined depth, by forming photoresist patterns to expose the gate oxide film for high voltage formed in the cell region and the low voltage region, and performing a wet etching process using the photoresist patterns as an etching mask, removing the entire gate oxide film for high voltage formed in the cell region and the low voltage region, by performing a cleaning process on the resulting structure, removing the photoresist patterns, forming a floating gate electrode and a control gate electrode, by sequentially forming a tunnel oxide film, a first polysilicon film, a second polysilicon film, a dielectric film, a third polysilicon film and a metal sili
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: January 23, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young Bok Lee
  • Patent number: 7091091
    Abstract: A first dielectric (120) and a first floating gate layer (130.1) are formed on a semiconductor substrate (110). The first dielectric, the first floating gate layer, and the substrate are etched to form isolation trenches (150). The first dielectric (120) is etched to pull the first dielectric away from the trench edges (150E) and/or the edges of the first floating gate layer (130E). The trench edges and/or the edges of the first floating gate layer are then oxidized. The trenches are filled with a second dielectric (210.2), which is then etched laterally adjacent to the edges of the trench and the first floating gate layer. A second floating gate layer (130.2) is formed to extend into the regions which were occupied by the second dielectric before it was etched.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: August 15, 2006
    Assignee: ProMOS Technologies Inc.
    Inventor: Yi Ding
  • Patent number: 6815762
    Abstract: In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed. Moreover, all insulating films to be deposited over the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed.
    Type: Grant
    Filed: October 13, 1999
    Date of Patent: November 9, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Yoshida, Takahiro Kumauchi, Yoshitaka Tadaki, Kazuhiko Kajigaya, Hideo Aoki, Isamu Asano