Abstract: An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.

Abstract: The present disclosure provides a memory. The memory includes an array of memory cells arranged as a plurality of rows by a plurality of columns. A memory cell is connected to at least one redundant memory cell in series in a same row for storing same data as the memory cell; and a column of memory cells correspond to at least one redundant column of redundant memory cells wherein each redundant memory cell in the at least one redundant column stores same data as the memory cell in a same row.

Abstract: Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors.

Abstract: A method of making a semiconductor structure using a substrate having a non-volatile memory (NVM) portion, a first high voltage portion, a second high voltage portion and a logic portion, includes forming a first conductive layer over an oxide layer on a major surface of the substrate in the NVM portion, the first and second high voltage portions, and logic portion. A memory cell is fabricated in the NVM portion while the first conductive layer remains in the first and second high voltage portions and the logic portion. The first conductive layer is patterned to form transistor gates in the first and second high voltage portions. A protective mask is formed over the NVM portion and the first and second high voltage portions. A transistor gate is formed in the logic portion while the protective mask remains in the NVM portion and the first and second high voltage portions.

Abstract: A graded composition, high dielectric constant gate insulator is formed between a substrate and floating gate in a flash memory cell transistor. The gate insulator comprises amorphous germanium or a graded composition of germanium carbide and silicon carbide. If the composition of the gate insulator is closer to silicon carbide near the substrate, the electron barrier for hot electron injection will be lower. If the gate insulator is closer to the silicon carbide near the floating gate, the tunnel barrier can be lower at the floating gate.

Abstract: A flash memory device wherein the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected amount so as to achieve a desirable coupling between the substrate, the floating gate and the control gate comprising the flash cell.

Abstract: A flash memory device wherein the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected amount so as to achieve a desirable coupling between the substrate, the floating gate and the control gate comprising the flash cell.

Abstract: A semiconductor charge storage device includes a semiconductor substrate having a surface region. The semiconductor substrate is characterized by a first conductivity type. A charge trapping material overlies and is in contact with at least a portion of the surface region of the semiconductor substrate. The charge trapping material is characterized by a first dielectric constant and by a first charge trapping capability. The first dielectric constant is higher than a dielectric constant associated with silicon oxide. A dielectric material overlies and is in contact with at least a portion of the charge trapping material. The dielectric material is formed using a conversion of a portion of the charge trapping material for providing a second charge trapping capability. The device also includes a conductive material overlying the second dielectric. The conductive material is capable of receiving an electrical signal to cause electrical charges being trapped in the semiconductor charge storage device.

Abstract: A semiconductor device including a semiconductor substrate, and a memory cell and a peripheral circuit provided on the semiconductor substrate, the memory cell having a first insulating film, a first electrode layer, a second insulating film, and a second electrode layer provided on the semiconductor substrate in order, and the peripheral circuit having the first insulating film, the first electrode layer, the second insulating film having an opening for the peripheral circuit, and the second electrode layer electrically connected to the first electrode layer through the opening for the peripheral circuit, wherein a thickness of the first electrode layer under the second insulating film of the peripheral circuit is thicker than a thickness of the first electrode layer of the memory cell.

Abstract: A non-volatile memory device includes a peripheral circuit region and a cell region. A method for fabricating the non-volatile memory device includes forming gate patterns over a substrate, the gate pattern including a tunnel insulation layer, a floating gate electrode, a charge blocking layer and a control gate electrode, and removing the control gate electrode and the charge blocking layer of the gate pattern formed in the peripheral circuit region.

Abstract: A non-volatile memory device and a method for fabricating the same are provided. The method includes: forming a gate structure on a substrate, the gate structure including a first insulation layer, a first electrode layer for a floating gate and a second insulation layer; forming a third insulation layer on the gate structure covering predetermined regions of the substrate adjacent to the gate structure; and forming a second electrode layer for a control gate on the third insulation layer disposed on sidewalls of the gate structure and the predetermined regions of the substrate.

Abstract: A non-volatile memory device includes a substrate having a first region and a second region. A first gate electrode is disposed on the first region. A multi-layered charge storage layer is interposed between the first gate electrode and the substrate, the multi-layered charge storage including a tunnel insulation, a trap insulation, and a blocking insulation layer which are sequentially stacked. A second gate electrode is placed on the substrate of the second region, the second gate electrode including a lower gate and an upper gate connected to a region of an upper surface of the lower gate. A gate insulation layer is interposed between the second gate electrode and the substrate. The first gate electrode and the upper gate of the second gate electrode comprise a same material.

Abstract: In a method of forming a phase-change memory unit, a conductive layer is formed on a substrate having a trench. The conductive layer is planarized until the substrate is exposed to form a first electrode. A spacer partially covering the first electrode is formed. A phase-change material layer is formed on the first electrode and the second spacer. A second electrode is formed on the phase-change material layer. Reset/set currents of the phase-change memory unit may be reduced and deterioration of the phase-change material layer may be reduced and/or prevented.

Abstract: An improved process forming a floating gate region of a semiconductor memory device. The process includes using a ceria slurry for chemical mechanical planarization to provide “stop on polysilicon” capabilities, allowing a thin nitride layer, or in the alternative no nitride layer, to be used and reducing the number of processing steps required to form the floating gate region.

Abstract: A non-volatile memory device includes a peripheral circuit region and a cell region. A method for fabricating the non-volatile memory device includes forming gate patterns over a substrate, the gate pattern including a tunnel insulation layer, a floating gate electrode, a charge blocking layer and a control gate electrode, and removing the control gate electrode and the charge blocking layer of the gate pattern formed in the peripheral circuit region.

Abstract: Non-volatile memory cell structures are described that are formed by a method including forming a first oxide layer on a horizontal strained substrate, forming at least one first recess through the first oxide layer to the strained substrate, and forming at least one vertical epitaxial structure in the recess. A crystal lattice of the vertical epitaxial structure is aligned with a crystal lattice of the strained substrate.

Abstract: Methods of forming a semiconductor device may include forming a tunnel oxide layer on a semiconductor substrate, forming a gate structure on the tunnel oxide layer, forming a leakage barrier oxide, and forming an insulating spacer. More particularly, the tunnel oxide layer may be between the gate structure and the substrate, and the gate structure may include a first gate electrode on the tunnel oxide layer, an inter-gate dielectric on the first gate electrode, and a second gate electrode on the inter-gate dielectric with the inter-gate dielectric between the first and second gate electrodes. The leakage barrier oxide may be formed on sidewalls of the second gate electrode. The insulating spacer may be formed on the leakage barrier oxide with the leakage barrier oxide between the insulating spacer and the sidewalls of the second gate electrode. In addition, the insulating spacer and the leakage barrier oxide may include different materials. Related structures are also discussed.

Abstract: A method of fabricating nonvolatile memory devices may involve forming separate floating gates on a semiconductor substrate, forming control gates on the semiconductor substrate, conformally forming a buffer film on a surface of the semiconductor substrate, injecting ions into the semiconductor substrate between the pairs of the floating gates to form a common source region partially overlapping each floating gate of the respective pair of the floating gates, depositing an insulating film on the buffer film, etching the buffer film and the insulating film at side walls of the floating gates and the control gates to form spacers at the side walls of the floating gates and the control gates, and forming a drain region in the semiconductor substrate at a side of the control gate other than a side of the control gate where the common source region is formed.

Abstract: A method for making a semiconductor device having non-volatile memory cell transistors and transistors of another type is provided. In the method, a substrate is provided having an NVM region, a high voltage (HV) region, and a low voltage (LV) region. The method includes forming a gate dielectric layer on the HV and LV regions. A tunnel oxide layer is formed over the substrate in the NVM region and the gate dielectric in the HV and LV regions. A first polysilicon layer is formed over the tunnel dielectric layer and gate dielectric layer. The first polysilicon layer is patterned to form NVM floating gates. An ONO layer is formed over the first polysilicon layer. A single etch removal step is used to form gates for the HV transistors from the first polysilicon layer while removing the first polysilicon layer from the LV region.

Abstract: A One Time Programming (OTP) cell structure, a method of fabricating an OTP structure, and a method of programming a OTP cell structure. The OTP structure comprises a semiconductor substrate; an n Metal-Oxide-Semiconductor (nMOS) programming structure formed on the substrate; wherein respective electrical contacts to a source of the nMOS programming structure and to a p-bulk of the substrate are separated for individual biasing of the source and the p-bulk of the substrate.

Abstract: A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit portion and memory cell portion, a step of forming a first insulating film above at least the memory cell portion, and a step of annealing the semiconductor substrate into which the impurity has been introduced. The first gate electrode has a first gate length. The second gate electrode has a second gate length shorter than the first gate length.

Abstract: A method of fabricating a memory device is described. During the process of forming the memory cell area and the periphery area of a semiconductor device a photoresist layer is formed on the memory cell area before the spacers are formed on the sidewalls of the gates. Therefore, the memory cell area is prevented from being damaged to mitigate the leakage current problem during the process of forming spacers in the periphery circuit area.

Abstract: A method for manufacturing a flash memory device including the steps of forming a gate oxide film for high voltage on the whole surface of a semiconductor substrate on which a cell region, a low voltage region and a high voltage region have been formed, etching the gate oxide film for high voltage formed in the cell region and the low voltage region by a predetermined depth, by forming photoresist patterns to expose the gate oxide film for high voltage formed in the cell region and the low voltage region, and performing a wet etching process using the photoresist patterns as an etching mask, removing the entire gate oxide film for high voltage formed in the cell region and the low voltage region, by performing a cleaning process on the resulting structure, removing the photoresist patterns, forming a floating gate electrode and a control gate electrode, by sequentially forming a tunnel oxide film, a first polysilicon film, a second polysilicon film, a dielectric film, a third polysilicon film and a metal sili

Abstract: Method of manufacturing a semiconductor device, including a first baseline technology electronic circuit (1) and a second option technology electronic circuit (2) as functional parts of a system-on-chip, by: manufacturing the first electronic circuit (1) with a first conductive layer (6; 6) that is patterned by subjecting an exposed layer portion thereof to Reactive Ion Etching (RIE); manufacturing the second electronic circuit (2) with a second conductive layer (6; 8) that is patterned by subjecting an exposed layer portion thereof to RIE; providing a tile structure (25; 26); providing the tile structure (25; 26) with at least one dummy conductive layer (6; 8) produced in the same processing step as the second conductive layer (6; 8); and exposing the dummy conductive layer (6; 8), at least partially, to obtain an exposed dummy layer portion, and RIE-etching of that exposed portion too when the second (6; 8) conductive layer is subjected to RIE.