Abstract: A first circuit is disposed on the semiconductor substrate, operates synchronously with a first clock signal, and outputs a first output signal delayed by a first delay time from the first clock signal. A first measuring circuit measures indirectly a first increase and a first decrease of the first delay time. A setting circuit operates synchronously with the first clock signal, outputs a second clock signal delayed from the first clock signal by a second delay time adding the first increase and subtracting the first decrease. A second circuit inputs the first output signal and operates synchronously with the second clock signal.

Abstract: A method and circuit configuration for synchronous resetting of an multiple clock domain circuit such as an Application Specific Integrated Circuit (ASIC) combine an asynchronous reset signal with a functional signal using a clocked reset tree of synchronous logic elements.

Abstract: According to an aspect of the invention, there is provided a phase synchronous circuit generating an output signal synchronized with an input signal. The phase synchronous circuit comprises an output circuit putting out an output signal according to an input clock signal, a selection circuit selecting a clock signal applied to the output circuit from multiphase clock signals such that the output circuit puts out an output signal synchronized with the input signal. The internal delay in a phase synchronous circuit using a multiphase clock signal can be efficiently compensated and an output signal synchronized with the reference signal can be generated.

Abstract: Systems of and methods for processing data for communication between a sender and a receiver are described. In one embodiment, the phase of a first clock is used to select between first and second portions of data from the sender. The selected data is then synchronized, for communication to the receiver, to a second clock having a frequency which is an integer multiple of that of the first clock, wherein the integer multiple is two or more. The first and second portions of the data may be provided to the same output pins in this embodiment for communication to the receiver. In a second embodiment, first and second portions of data from the sender are clocked in using first and second edges, respectively, of a first clock. The first and second edges have a first polarity if a first pre-determined mode is in effect, and have a second polarity if a second pre-determined mode is in effect. Data derived from the clocked in data is then synchronized, for communication to the receiver, to a second clock.

Abstract: A clock synchronization circuit for synchronizing a first clock signal and a second clock signal for data transfer from a first function block, which is clocked by the first clock signal, to a second function block which is clocked by the second clock signal, where the clock synchronization circuit has a sampling unit for sampling the second clock signal using the first clock signal in order to generate samples and edge detection values of the sampled second clock signal, a logic circuit for outputting the generated edge detection values as a reconstructed clock signal and generating an Edge-too-Early signal and an Edge-too-Late signal; and a signal delay circuit, which delays the reconstructed second clock signal on the bases of the Edge-too-Early signal or the Edge-too-Late signal.

Abstract: An apparatus for synchronizing a clock using a source synchronous clock is disclosed. The apparatus includes: channel receivers for receiving a source synchronous channel; divider for dividing the source synchronous clock to a low frequency clock; selectors for selecting one of the divided source synchronous clock and a system clock as a reference clock; detectors for generating a phase difference signal; phase difference signal selectors for selecting a phase difference signal from the detectors and a phase difference signal from an internal logic; and voltage oscillators for transmitting a clock synchronized to a source synchronous channel to the external optical transmission system by generating a predetermined synchronous frequency according to the selected phase difference signal.

Abstract: A distributed multi-axis motion control system comprises a multicast communications network having several node components. Each of the node components includes a clock and an actuator. The actuators are part of a motor system and a pattern profile table of the motor system is generated. The pattern profile table is translated into a separate single-direction-of-motion pattern table to separately direct the motion of each of the actuators of the node components. A grandmaster clock generates synchronization signals which are transmitted through the network at a sync interval and which synchronize the clocks. Time-bombs are generated at an interval which is a whole number multiple of the sync interval. The time-bombs cause concurrent execution of the first and subsequent steps from the single-direction-of-motion pattern tables to produce synchronized multi-axis motion of the motor system.

Abstract: An integrated circuit is provided comprising a processor, an onboard system clock having a ring oscillator for generating a clock signal, a memory, and clock trim circuitry. The processor is arranged to, in response to receiving an external signal, determine the number of cycles of the clock signal during a predetermined number of cycles of the external signal or the number of cycles of the external signal during a predetermined number of cycles of the clock signal and to output the determined number of cycles to an external circuit. The processor is also arranged to, in response to receiving a trim value based on the determined number of cycles from the external circuit, store the trim value in the memory and control the clock trim circuitry to trim the frequency of the clock signal generated by the ring oscillator using the trim value.

Abstract: A method and a device for testing an embedded phase-locked loop (PLL) circuit are disclosed. A first clock signal of a first frequency is provided to an embedded phase-locked loop (PLL) circuit to be tested by a tester, so as to generate a PLL clock signal by the embedded PLL circuit in response to the first clock signal of the first frequency. The PLL clock signal is inputted to a test circuit along with a second clock signal of a second frequency. Then, the PLL clock signal is sampled with the second clock signal of the second frequency to generate a first sampled signal. The second frequency has a first correlation with the first frequency. Whether the embedded PLL circuit is in a normal operation condition is determined according to the first sampled signal.

Abstract: A high-density DDR-1/DDR-2 compatible SDRAM chip with a reduced output circuit area is provided. When the SDRAM is a DDR1 SDRAM, an output signal output from an output circuit (14) is output to an output terminal (17) as a main output signal. When the SDRAM is a DDR2 SDRAM, an output signal output from an output circuit (15) is output to the output terminal (17) as the main output signal and, at the same time, the output signal output from the output circuit (14) is output as a sub-output signal to perform operation for adjusting the slew rate or the amount of output current of the main output signal or for adjusting the impedance of the output terminal as viewed from an external point.

Abstract: A synchronization interface transfers multi-bit digital data or signal between multiple clocked logic domains while maintaining data or signal integrity. When deployed in a processor-based system, in one embodiment, a plurality of data units may be received at a source location in a first clocked domain. To control writing of the plurality of data units from the source location to a target location in a second clocked domain, an enable signal may be detected. This enable signal may be synchronized with respect to the second clocked domain. Finally, in response to the synchronized enable signal, the plurality of data units may be transferred from the first clocked domain to the target location in the second clocked domain. The synchronization interface may comprise a data path to capture the multi-bit digital data or signal based on a control logic implementing a mechanism (e.g.

Abstract: A charge pump and loop filter circuit of a phase locked loop includes a resistor, a capacitor, first and second input current sources for supplying first and second currents to the circuit, a first output current source for outputting the first current from the circuit, and a second output current source for receiving the second current from the circuit. The charge pump also contains a plurality of up pulse switches and down pulse switches for controlling current flow through the circuit such that only a fraction of the current that flows through the resistor flows into and out of the capacitor for charging and discharging the capacitor. The size of the capacitor can be reduced accordingly based on the amount of current used to charge and discharge the capacitor.

Abstract: A delay locked loop circuit (200) in which multiple outputs are produced. A single delay line (24) is shared among multiple tap selection circuits (256A, 265B, 265C). Fixed phase shifts (412) can be introduced between multiple outputs. A modulating signal can be used in the tap selection processing to produce digital amplitude, frequency and/or phase modulation.

Abstract: A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: A motion control system and method that includes a central controller configured to generate first and second demand control signals to be used to define actuation motion of respective first and second actuators. The central controller is in communication with first and second nodes by way of a data network, each node including at least a respective actuator configured to implement at an actuator time a motion or force-related effort based upon the respective demand control signal. Each node also includes a memory configured to store at least one respective propagation delay parameter related to a signal propagation delay between the central controller and the node. A timing mechanism establishes timing at each node based on the respective propagation delay parameter so that the actuator time at the nodes occurs simultaneously. Strictly cyclic and/or full-duplex high-speed communication can be supported. The network can be wired in a ring or as a tree and with twisted pair cabling or fiber.

Abstract: There is disclosed a data recovery (DR) circuit including an over sampling (OS) circuit, a transition detection (TD) circuit and a sample selection/data alignment (SSDA) circuit. A multiphase clock generating circuit delivering n phases is coupled to each of these circuits. The OS circuit over samples the received digital data stream and produces n sampled signals at each clock period. The TD circuit is configured to detect a data transition (if any) and to generate n select signals, only one of which is active and represents a determined delay with respect to the transition position, indicating thereby which over sampled signal is the best to be retained. The SSDA circuit is configured to generate the recovered (retimed) data signal that is aligned with a predefined phase of the multiphase clock signal. The data recovery circuit is well adapted to high speed serial data communications between integrated circuits/systems on digital networks.

Abstract: A system and method for measuring the timing requirements of a sequential logic element of a programmable logic device. The sequential logic element has a first data terminal, an output terminal, and a clock terminal. A first synchronous element is coupled to the data terminal through a first delay element. The first synchronous element is clocked by a clock signal and receives an alternating test signal. A second synchronous element is coupled to the clock terminal through a second delay element of an input-output block. The second synchronous element is also clocked by the clock signal and receives the alternating test signal. The output terminal of the sequential logic element is monitored by a tester or by logic configured in the fabric of the programmable logic device to determine when the logic state changes as the delay of the first or second delay element is selectively varied.

Abstract: A clock resynchronizer includes a write circuit and a read circuit. The write circuit stores input data in accordance with a first clock associated with the input data. The read circuit outputs data to be output out of the data stored in the write circuit, in accordance with a second clock. The read circuit also outputs a signal acquisition permitting signal indicating that the data to be output is valid. The read circuit outputs no signal acquisition permitting signal when the data to be output is not output.

Abstract: The four types of the zero idle time Z-state circuits are presented with an improvement in productivity, cost, chip area, power consumption, and design time. The zero idle time Z-state circuits basically include a sensing gate, two stacked PMOS transistors, and a feedback line. The sensing gate senses a voltage at its input assuming no feedback is applied. Again, the corresponding output of two stacked PMOS transistors is assumed to be connected to the sensing input. Two stacked PMOS transistors generate a high impedance Z-state at its output according to the corresponding output of the sensing gate. Therefore, the feedback line keeps sampling the output and feeding back the output voltage to the sensing input. Consequently, the feedback configuration provides the initial output voltage, which is the midpoint voltage decided by the device aspect ratios of the sensing gate before normal operation starts in all three systems such as all kinds of phase-locked loops, delay-locked loops, and switching regulators.

Abstract: A logic circuit includes an input for one or several input operands, an output for a result and an inverted result, a first circuit branch with a first logic assembly, which is coupled to the input and the output, to calculate the result, as well as a second circuit branch with a second logic assembly, which is coupled to the input and the output, to calculate the inverted result, wherein the first logic assembly and the second logic assembly have different run times for calculating the result and the inverted result, respectively. Further, a delay circuit and a compensation circuit, respectively, are provided in the first and/or second circuit branch to reduce a difference of the run times and the power consumptions, respectively, of the first and the second circuit branch.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: An IC including skew-programmable clock buffers, fixed skew logic circuit, an external interface and a skew controller. Each skew-programmable clock buffer receives a distributed clock signal and provides a corresponding local clock signal having a programmed skew. The fixed logic circuit enables permanent programming of static skew values and the external interface enables programming of dynamic skew values. The skew controller selects between the static and dynamic skew values and programs the skew-programmable clock buffers based on selected skew values. In one embodiment, the skew controller is operative to detect a skew over-ride command upon reset of the IC and to select between the static and dynamic skew values based on the skew over-ride command. The programmable memory may be integrated on the IC or externally coupled via the external interface. The fixed skew logic circuit is implemented as any type of permanent programmable block, such as laser-blown fuses, an EPROM, etc.

Abstract: A clock recovery method is disclosed wherein the FIFO delay of data words and the phase difference between a data word and a receiver clock are used to time data transmissions from a transmitter. The phase difference between the data word and the receiver clock is determined by the offset of a word relative to a desired position in a storage buffer. The FIFO delay is determined either by measuring the difference between a read pointer and a write pointer in the FIFO or, alternatively, by calculating the difference between a timestamp of the time a data word entered the FIFO and the current time as the data word is read from the FIFO.

Abstract: In a PLL circuit including a voltage-controlled oscillator, a phase detector and a final control element, the final control element contains two separate channels, between the phase detector and the voltage controlled oscillator, wherein one channel processes the useful signal components and the other channel processes the disturbance signal components of the synchronization pulses. Each channel has two tracks, for generation of a potential difference, wherein each track is connected to a capacitor plate.

Abstract: A synchronous clock phase control circuit includes a T/8 step phase clock generation unit, a phase selection unit, and four synchronous clock generation units. The T/8 step phase clock generation unit generates eight clocks previously delayed in phase by T/8 from an input clock. The phase selection unit selects four control clocks from the eight clocks generated by the phase clock generation unit based on four phase control signals, respectively. The four synchronous clock generation units synchronize the selected clocks with an externally input trigger signal TR using the input clock as a reference, and output the selected clocks when synchronization is established, respectively.

Abstract: Circuits and methods are provided for clock adjustment. A method for clock adjustment includes receiving feedback clocks from independent ASIC modules. The method includes comparing the feedback clocks to a reference clock to generate phase measurement values. A common delay is removed from the phase measurement values to form normalized correction values. Target phase values and clock select values are selected using the normalized correction values. And, clock signals to independent ASIC modules are adjusted based on the target phase values and clock select values.

Abstract: The rising edge triggered flip-flops and falling edge triggered flip-flops in one or more clock domains of a target system can be simultaneously initialized to predetermined logic states by activating the flip-flop set/clear inputs, freezing the flip-flop clock signals high or low, subsequently deactivating the flip-flop set/clear inputs, and then re-enabling the clock signals.

Abstract: A clock/data recovery circuit used in a receiving apparatus is provided in the circuit including: a voltage control oscillator for generating a clock signal of a frequency of 1/K of a bit rate of an input data signal; a delay circuit; a demultiplexer for demultiplexing the input data signal; a multiplexer for multiplexing the demultiplexed signals; a phase comparator for comparing phases of an output signal of the delay circuit and an output signal of the multiplexer; a lowpass filter; wherein the clock/data recovery circuit outputs the clock signal generated by the voltage control oscillator as a recovery divided clock signal, and outputs the demultiplexed signals output as recovery parallel data signals.

Abstract: An integrated circuit, comprising a processor, an onboard system clock for generating a clock signal, and clock trim circuitry, the integrated circuit being configured to: (a) receive an external signal; (b) determine either the number of cycles of the clock signal during a predetermined number of cycles of the external signal, or the number of cycles of the external signal during a predetermined number of cycles of the clock signal; (c) store a trim value in the integrated circuit, the trim value having been determined on the basis of the determined number of cycles; and (d) use the trim value to control the internal clock frequency.

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock condition following the initialization. The second adjustable delay line is adjusted after synchronization is achieved with the first adjustable delay line, or when the first adjustable delay line reaches a maximum adjustable delay. The first adjustable delay line is reset when a lock condition is initially obtained, and the second adjustable delay line is adjusted to compensate for the resetting of the first adjustable delay line.

Abstract: An apparatus, a method, and a computer program product are provided for producing a synchronous divider reset signal. A notorious concern with multiple non-integer frequency ratio synchronous source clocks has been the time of edge alignment between the respective clocks. To address this concern, a number of latches can be utilized in order to detect alignment of the edges of these clocks. Specifically, the latches are employed to assist in the production of a synchronous divider reset signal for downstream dividers that are utilized in many microprocessors today. Hence, all of the downstream dividers can be properly synchronized to alleviate any errors that can occur between respective macros of a microprocessor chip resulting from misalignment of clock edges.

Abstract: A timing domain crossing apparatus and method of transferring signals between timing domains are disclosed. A receiver samples a data signal with a sample clock in a first timing domain. The sampled data signal is expanded to a plurality of expansion signals, which are held valid for a plurality of consecutive active clock cycles. A data order adjuster may re-order the plurality of expansion signals to a predetermined order. A timing generator samples a command signal with an internal clock in a second timing domain to generate a re-timing strobe. The re-timing strobe may be temporally positioned to be within the expansion data window and used to sample the plurality of expansion signals in the second timing domain. The timing domain crossing apparatus and method of signal sampling may be incorporated in a semiconductor device, which may be fabricated on a semiconductor wafer and included in an electronic system.

Abstract: A semiconductor integrated circuit comprises therein a plurality of logic circuits synchronously designed to operate in synchronization with a clock signal, a first power supply wire for supplying a high-potential side power supply voltage from a first input terminal to each logic circuit, a second power supply wire for supplying the high-potential side power supply voltage from a second input terminal to each logic circuit and a third power supply wire for supplying the high-potential side power supply voltage from a third input terminal to each logic circuit. The logic circuit (DFF circuit) includes two stages of latch circuits and a clock signal inversion circuit. Only the clock signal inversion circuit is connected with the first power supply wire, while the second power supply wire is connected with the remaining latch circuits.

Abstract: A bit timing signal is regenerated from an encoded digital signal in a receiver using a predetermined sample rate Fs. An input pulse signal is generated in response to predetermined transitions of the encoded digital signal. A clock count signal is generated having a variable clock period according to cyclical counting of the clock count signal up to a count value S at the predetermined sample rate, the count value alternating between an upper value Su and a lower value Sl so that the variable clock period has an average length substantially equal to a data bit period of the encoded digital signal. The clock count signal is synchronized with the encoded digital signal by 1) counting the input pulse signals to generate a pulse count, 2) counting sampling periods between successive input pulse signals to generate a sample count, and 3) generating a sync signal if the pulse count is greater than a pulse threshold and the sample count is greater than a sample threshold.

Abstract: A time interleaved ADC system includes a delay circuit that has a dynamically adjusted speed to achieve uniformly spaced sampling intervals. The adjustment control circuit monitors the sampling pulses associated with sampling time instant for each ADC, and provides one or more control signals to the delay circuit. In one example, the adjustment control circuit employs a phase detector circuit, an integrator circuit, and a dynamic biasing circuit. In this example, the phase detector circuit evaluates the sampling pulses to generate control signals for the integrator circuit, which generates signals that are utilized by the dynamic biasing circuit to adjust the delays associated with the delay circuit. The relative positions of the sampling pulses are controlled by adjusting the delay in the delay circuit.

Abstract: Method and apparatus for reducing power consumption within a logic device is described. A logic device comprises a clock gate and a flip-flop. The clock gate includes a clock enable terminal and a clock terminal. The flip-flop includes an input terminal, an output terminal, and a configuration terminal. The flip-flop is coupled to the clock gate. The flip-flop is configurable to trigger on at least one of a rising edge and a falling edge of a clock signal. The clock gate controllably gates the clock signal coupled to the clock terminal.

Abstract: Decoders process a digital input word to derive thermometer-coded signals for controlling one cell of an array of cells, commencing operation at the rising edge of a first clock signal. Each cell has a first latch clocked by a second clock signal, delayed by a preselected delay time ?1 relative to the first clock signal, and a second, transparent latch clocked by a third clock signal whose rising edge coincides with the rising edge of the first clock signal and whose falling edge coincides with the rising edge of the second clock signal. The rising edge of the third clock signal is not affected by jitter associated with a delay element used to delay the first clock signal by ?1. The falling edge is affected by such jitter, but is prevented from feeding through to final outputs because the second latch is non-transparent at that falling edge.

Abstract: It is difficult to optimize the timing of the forward and reverse direction for high frequency bi-directional digital signals. Therefore, a digital system is provided that improves the adjustability of the timing by the emission of an additional clock pulse, together with the output clock pulse for the receiver and the feedback clock pulse for the PLL. The additional clock pulse is re-circulated using a delay line and is used to set the clock pulse of the reverse direction signals.

Abstract: The clock switch device of the present invention includes: a clock detector for receiving a plurality of clocks and clock selection data designating a clock to be selected, detecting whether or not the clock designated by the clock selection data among the plurality of clocks changes in signal level, and outputting the result as a detection signal; a control register for holding and outputting the clock selection data when the detection signal indicates that the clock designated by the clock selection data changes in signal level; and a selector for receiving the plurality of clocks and selecting a clock corresponding to the output of the control register among the plurality of clocks.

Abstract: A clock tree distribution network for a field programmable gate array comprises an interface with a root signal chosen from at least one of an external clock signal, an internal clock signal, a plurality of phase lock loop cell output signals and programmable elements. The FPGA includes a logic array with programmable elements coupling the logic array to a programmable routing architecture and the interface. A routed clock network selects a signal from a clock signal from the interface, a local signal from the logic array through the routing architecture, Vcc or ground, and routes the selected signal to the logic array through the clock tree distribution network. A hardwired clock network selects a signal from a clock signal from the interface or a local signal from the routing architecture, and routes the selected signal to a plurality of flip-flops in the logic array through the clock tree distribution network.

Abstract: A digital-to-phase or digital-to-time-shift converter (100) includes a delay line (106), a multiplexor (108) and synchronization circuit (110). In the converter (100) the clock edges of a reference signal are shifted in response to the value of a multi-bit digital word, IN (104). The synchronization circuit (110) gates the output of the multiplexor (108) such that a pulse appears at the synchronization circuit's (110) output port (114) only when the circuit is gated by a signal at input TRIG (112). The synchronization circuit (110) creates a time aperture for the multiplexor output.

Abstract: A synchronizer circuit which synchronizes an input clock signal to a sampling clock to generate a synchronized signal. In an embodiment, an adaptive module detects the occurrence of a positive edge in an input clock signal after a logic low corresponding to a prior negative edge is propagated to as a synchronized signal, and provides a logic high as an input to a sampling module. The sampling module propagates the signal led at the input as the synchronized signal. The adaptive module causing the input to remain at logic high at least until the synchronization module provides logic level as the synchronized signal. The negative edges in the input signal may also be processed similarly.

Abstract: Orthogonal frequency division multiplexing (OFDM) receiver embodiments of the invention provide data demodulator synchronization by finding the end of the short preamble in an IEEE-802.11a burst transmission. This method exploits the fact that there are certain symmetries in the long-preamble that can be used to determine synchronization. The long-preamble sequence is composed of a guard interval (GI) and two long-preamble symbols; the GI is the last 32 samples of the long-preamble symbol. The 32nd sample of the long-preamble acts as a “pilot” or “anchor” sample in that the previous N and subsequent N samples are complex conjugates, or conjugate “mirror” vectors. Due to the periodicities of the long-preamble, this property repeats every 32 samples. No other samples in the long preamble exhibit this property. Coherent combining is used in one embodiment for robustness.

Abstract: Enabling pulse clocks are configurably generated for a selected one of a first and a second signaling mode, employing a configurable enabling pulse clock generator configurable to so generate the enabling pulse clocks.

Abstract: A digital system aligns a set of serial data receiver demultiplex circuits, thereby aligning the bits in the data words, while maintaining separate and optimally aligned data recovery clocks for each channel. The digital system generates a reference clock signal and one or more slave clock signals. Phase circuitry receives the slave clock signal and outputs a plurality of clock phase signals. A phase selection circuit receives the plurality of clock phase signals and selects an adjusted clock signal in response to a phase selection signal. A clock correlation circuit determines a phase difference between the reference clock signal and the adjusted clock signal and provides the phase selection signal to minimize the phase difference. The clock correlation circuit provides the phase selection signal from a counter.

Abstract: In a dual loop PLL having a frequency comparison loop and a phase comparison loop, when an input control circuit 30 of an up/down counter 8 receives an UP signal from a frequency comparator 7, the input control circuit 30 outputs a positive value of a ½ of a previous addition/subtraction result value. When the input control circuit 30 receives a DOWN signal from the frequency comparator 7, the input control circuit 30 outputs a negative value of a ½ of the previous addition/subtraction result value. A register 33 stores a count value. The adder 31 adds the output of the input control circuit 30 to the output of the register 33. Thus, the up/down counter 8 increments or decrements by a ½ value of the previous addition/subtraction result value, and the dual loop PLL performs a frequency comparison based on a dichotomizing search method. Therefore, even when the output frequency is high, the frequency comparison is efficiently performed, and the lock up time is reduced.

Abstract: A circuit for glitch-free changing of clocks having different phases. The circuit comprises a phase detector for receiving a data stream and a system clock, and generating a phase-up signal and a phase-down signal; a flag signal generator for receiving the phase-up signal and the phase-down signal, and then generating M flag signals, wherein the select signal corresponding to the enabled flag signal is enabled; an output stage for receiving the M select signals and the M clocks, and then outputting the system clock.

Abstract: A system and method for synchronizing a local clock to a reference clock using a linear model of the clock error between the local clock and the reference clock is disclosed. In one embodiment, a double-exponential smoothing process is used in conjunction with the linear model to estimate a frequency offset by which the frequency of an oscillator of the local clock is adjusted. Also disclosed herein is a phased-lock loop (PLL) adapted to synchronize a local clock with a reference clock using the double-exponential smoothing process, as well as a system implementing the PLL for timing the playout of data received from a transmitter.

Abstract: An object of the invention is to provide a bit synchronizing circuit of high quality comprising a bit synchronizing circuit used in a reception circuit for serial communication having a polyphase clock generation circuit for generating a plurality of clocks which are out of phase with each other by a substantially regular interval, based on an input clock and a detection circuit for detecting which clock has a phase shift of an integral multiple of a clock cycle among the clocks generated by the polyphase clock generation circuit with respect to the input clock.

Abstract: Tone signal detection circuit for a receiving circuit for detecting at least one tone signal of predetermined tone signal frequency (fE) which is contained in a received analog input signal, comprising a reference signal generator (41) for generating an analog converter reference signal which consists of a reference DC (VrefDC) and a periodic reference AC (VrefAC) having a variable fundamental frequency (fG), which is superimposed on the reference DC, an analog/digital converter (11) for converting the analog input signal into a digital data stream in dependence on the analog converter reference signal (Vref); and comprising a digital control circuit (20) which adjusts the variable fundamental frequency (fG) of the reference signal (Vref) generated by the reference signal generator (42) in accordance with the predetermined tone signal frequencies (fG) of the tone signals to be detected and evaluates the digital data stream output by the digital analog/digital converter (11) for detecting a data pattern corres