Abstract: A method of self-synchronizing clocks in a multiple chip system, by assigning one chip as the master chip and the other chips as slave chips. A training signal is sent from master chip to the slave chips to determine the latency from the master chip to a slave chip, and then a synchronization signal is sent out to synchronize the “time zero” of the chips.

Abstract: A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: An asynchronous data transmitting apparatus includes data signal transmission lines; two control transmission lines having a minimum delay and maximum delay respectively; a transmitter; and a receiver. The transmitter includes a data transmitting unit that transmits a data signal through the data signal transmission lines, depending on a transmit clock; and control transmitting units that transmit control signals through the control transmission lines, depending on the transmit clock. The receiver includes a receive clock generator that generates a read clock from the control signals; and a data receiving unit that receives the data signal through the data signal transmission line, depending on the read clock.

Abstract: A clock tree distribution network for a field programmable gate array comprises an interface with a root signal chosen from at least one of an external clock signal, an internal clock signal, a plurality of phase lock loop cell output signals and programmable elements. The FPGA includes a logic array with programmable elements coupling the logic array to a programmable routing architecture and the interface. A routed clock network selects a signal from a clock signal from the interface, a local signal from the logic array through the routing architecture, Vcc or ground, and routes the selected signal to the logic array through the clock tree distribution network. A hardwired clock network selects a signal from a clock signal from the interface or a local signal from the routing architecture, and routes the selected signal to a plurality of flip-flops in the logic array through the clock tree distribution network.

Abstract: A timing domain crossing apparatus and method of transferring signals between timing domains are disclosed. A receiver samples a data signal with a sample clock in a first timing domain. The sampled data signal is expanded to a plurality of expansion signals, which are held valid for a plurality of consecutive active clock cycles. A data order adjuster may re-order the plurality of expansion signals to a predetermined order. A timing generator samples a command signal with an internal clock in a second timing domain to generate a re-timing strobe. The re-timing strobe may be temporally positioned to be within the expansion data window and used to sample the plurality of expansion signals in the second timing domain. The timing domain crossing apparatus and method of signal sampling may be incorporated in a semiconductor device, which may be fabricated on a semiconductor wafer and included in an electronic system.

Abstract: Some embodiments of the invention provide a biased tracking loop that may include encoded information. Embodiments may comprise a training pattern, utilized in a non-interfering way that allows for clock recovery, embedded information transmission and/or header alignment. Therefore, embodiments may comprise a tracking loop training pattern that comprises data.

Abstract: A technique is described for simultaneously and synchronously transmitting digital data and a clock signal in a digital integrated circuit, circuit board, or system. The technique is based on the phase shift keying (PSK) modulation of an RF high frequency carrier which is distributed on low impedance interconnection transmission lines. The PSK modulation contains the digital data while the carrier itself constitutes the clock signal, and the clock signal and digital data are transmitted in a synchronous manner. The carrier frequency may be near fT, the maximum operation frequency of the transistors. Since the digital data and clock signal are simultaneously transmitted on the same interconnection, the digital data never becomes skewed with respect to the clock signal, or vice versa.

Abstract: An IC incorporating a multiphase voltage converter with synchronized phase shift including a phase shift pin, a frequency select pin, a master clock pin, and a voltage regulator. The phase shift pin is coupled to a first voltage for a master mode or a first resistor for a slave mode. The frequency select pin is coupled to one of a second voltage and a second resistor. The master clock pin provides a master clock signal or receives an external clock signal. The IC provides the master clock signal at a frequency determined by the second resistor or otherwise at a default frequency. The voltage regulator operates in the slave mode at a phase shift relative to the external clock signal based on the first resistor and the second resistor or based on the first resistor and a default resistance if the second voltage is coupled.

Abstract: An electronic device having first circuitry operating in a first clock environment and second circuitry operating in a second clock environment, the first circuitry being arranged to generate a soft reset signal for resetting the second circuitry, the integrated circuit further including: a soft reset hold circuit clocked in the first clock environment connected to receive the soft reset signal and to generate an output reset signal in an asserted state; and a synchronizer clocked in the second clock environment connected to receive the output reset signal and to generate a retimed reset signal in an asserted state after a predetermined period, wherein the retimed reset signal is fed back to the soft reset hold circuit to cause the output reset signal to adopt a deasserted state at the end of said predetermined period.

Abstract: A apparatus and method are disclosed for generating one or more clock signals. A clock signal is generated based on pattern signals and a reference clock signal. When the reference clock signal transitions high, the state of a first pattern signal is output, and when the reference clock signal transitions low, the state of a second pattern signal is output. Successive states of the first and second pattern signals, selected according to the reference clock signal, provide the generated clock signal.

Abstract: A multiplicity of electronic devices is provided to generate triangular wave signals variable between an upper and lower limit voltages by charging or discharging capacitors. One of the triangular wave signals serves as a master triangular wave signal for controlling the phases of the remaining (or slave) triangular wave signals. A detection signal is generated every time the master triangular wave signal reaches predetermined threshold levels. In response to the detection signal, a capacitor associated with one slave triangular signal is promptly discharged to bring the slave triangular signal to the lower limit voltage, whereby the respective slave triangular wave signals are synchronized to be offset in phase relative to the master triangular wave signal by respective predetermined phase angles.

Abstract: An oversampling delay is provided between clock and data signals by steering a current between first and second nodes. The first node is coupled to an input differential pair of a clock interpolator and a delayed differential pair of a data interpolator. The second node is coupled to an input differential pair of the data interpolator and a delayed differential pair of the clock interpolator. First clock and data signals are provided to a first data sampling element and, respectively, to the clock and data interpolators. Second clock and data signals, respectively output from the clock and data interpolators, are provided to a second data sampling element. Additional data sampling elements may be linked to form a longer chain of data sampling elements.

Abstract: A method of interfacing circuits operating in different voltage domains includes receiving a first signal with a first circuit operating in a first voltage domain and generating a second signal with a second circuit operating in a second voltage domain. The second signal is level shifted between the first and second voltage domains with a level shifter and synchronized with the first signal with a third circuit operating in the first voltage domain.

Abstract: A circuit generates a qualified data read strobe signal from a start burst signal and a bidirectional data strobe signal in a DDR memory control module. The circuit includes a delay module that receives the start burst signal and that generates a delayed start burst signal. An enable signal generator receives the delayed start burst signal and generates an enable signal. A first circuit generates the qualified data read strobe signal based on the enable signal and the bidirectional data strobe signal.

Abstract: A synchronization detection circuit includes: a matched filter 105 for outputting a correlation value, between a spreading code and data that is obtained by sampling a code spread signal 101, using a sampling clock for one chip cycle; a sampling clock generator 102 for generating the sampling clock, so that, for each cycle of a code spreading signal, a phase delay for the basic clock of one chip cycle is increased by a value obtained by dividing one chip cycle by an integer; and a synchronization determination unit 107 for determining the timing whereat the maximum correlation value is attained and for performing synchronization detection.

Abstract: A method is presented for enabling application-level software to normalize processor clock values within a multiprocessor data processing system. A first processor number associated with a first processor is obtained such that the first processor executes one or more instructions for obtaining the first processor number. Subsequent to obtaining the first processor number, a processor clock value is obtained such that the processor clock value is associated with a processor that executes one or more instructions for obtaining the processor clock value. Subsequent to obtaining the processor clock value, a second processor number associated with a second processor is obtained such that the second processor executes one or more instructions for obtaining the second processor number. If the first processor number and the second processor number are equal, then the first processor number is used to retrieve a compensation value for a normalization operation on the processor clock value.

Abstract: Phase correction circuits and methods for reducing phase skew between multiphase clock signals and a semiconductor device including the circuit are provided. The semiconductor device includes a phase correction circuit and an output buffer. The phase correction circuit corrects phase skew between multiphase clock signals and generates skew-corrected clock signals. The output buffer outputs data in synchronization with the skew-corrected clock signals. The phase correction circuit includes a phase corrector, a replication output buffer, a phase detector, and a controller. The phase corrector corrects a duty cycle of a first clock signal, a duty cycle of a second clock signal, and phase skew between the first and second clock signals and generates skew-corrected first and second clock signals. The replication output buffer has the same structure as a data output buffer and outputs replication data in synchronization with the skew-corrected first and second clock signals.

Abstract: A system, method, and article of manufacture for synchronizing first and second time-of-day clocks on first and second computers, respectively, are provided. The first and second computers have first and second network interface cards with third and fourth clocks, respectively, thereon. The system utilizes time stamp values generated by the third and fourth clocks to synchronize the first and second time-of-day clocks.

Abstract: An apparatus, a method, and a computer program are provided for the generation of constant incremental increases while changing core clock frequencies. In computer systems, oftentimes frequency changes are useful. Maintaining the clocking ability of the computer system, though, can be a difficult task. To maintain the time keeping ability, time base logic is utilized with the free-running clock, which can be frequency limited. However, a plurality of communication channels in conjunction with an adder system is employed to effectively adjust for an ever increasing frequency to allow for a effective timekeeping regardless of the core frequency.

Abstract: An oscillator circuit is disclosed that includes a first oscillation part configured to output a first oscillation output by charging and discharging a first capacitor, and a second oscillation part configured to output a second oscillation output by charging and discharging a second capacitor. The second oscillation part includes a phase difference detection part configured to detect the phase difference between the first oscillation output and the second oscillation output, and a charging current and discharge current control part configured to control the charging current and the discharge current of the second capacitor in accordance with the phase difference detected by the phase difference detection part so that the second oscillation output synchronizes with the first oscillation output.

Abstract: In the data recovery circuit of the invention, a first group of sampling clock pulses is used for sampling approximately the central portions of the data bits in an incoming data stream to produce a first sampled data stream, while a second group of sampling clock pulses is used for sampling approximately the transition portions between every two adjacent data bits in the incoming data stream to produce a second sampled data stream. By detecting the resemblance of each bit in the second sampled data stream to the corresponding two adjacent bits in the first sampled data stream, a phase detection and correction circuit determines an early condition or a late condition for the phases of the sampling clocks and produces a signal to correct the phases of the sampling clocks by shifting the phases backwards or forwards. According to the invention, sampling clocks with lower frequencies can be used for sampling, and the phase error can be corrected to obtain the correct data recovery.

Abstract: A duty cycle corrector includes a first controllable delay, a second controllable delay, a phase detector, and a compensation circuit. The first controllable delay is configured to delay a first signal to provide a second signal. The second controllable delay is configured to delay the second signal to provide a third signal. The phase detector is configured to adjust the first controllable delay and the second controllable delay to phase lock the third signal to the first signal. The compensation circuit is configured to compensate for a mismatch between the first controllable delay and the second controllable delay to provide a fourth signal in response to the first signal and a fifth signal approximately 180 degrees out of phase with the fourth signal in response to the second signal.

Abstract: An off-chip driver circuit including a plurality of delay circuits, at least two of which have different delay times, in which the delay circuits receive a data signal and generate delayed data signals, respectively. The circuit also includes a plurality of off-chip drivers for respectively receiving the delayed data signals from the respective delay circuits and generating respective output signals in response to respective control signals, wherein the total number of the off-chip drivers to be activated at the same time is changed by the respective control signals which are generated in response to a desired drivability, and the activated off-chip drivers sequentially generate the output signals in response to the delay times, thereby increasing a total drivability of the off-chip driver circuit.

Abstract: Circuits and methods for aligning two or more signals including a first and second signal. In one embodiment, a shift register generates two or more shifted copies of the second signal, and each of a plurality of phase detectors receives the first signal and one of the shifted copies of the second signal, each phase detector providing an output indicating whether the first signal is substantially aligned with the shifted copy of the second signal. A multiplexer may also be provided for receiving each of the shifted copies of the second signal, the multiplexer having a plurality of select lines coupled with the output signals of the phase detectors. Some embodiments may include a power saving mode.

Abstract: A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.

Abstract: A 40-Gb/s clock and data recovery (CDR) circuit incorporates a quarter-rate phase detector and a multi-phase voltage controlled oscillator to re-time and de-multiplex a 40-Gb/s input data signal into four 10-Gb/s output data signals. The circuit is fabricated in 0.18 ?m CMOS technology.

Abstract: In one embodiment, a method for balancing clock signals in a clock tree includes, at a register, receiving a divided input clock signal and a non-divided input clock signal and generating a first output clock signal based on the received divided input clock signal and the received non-divided input clock signal, the first output signal being associated with a first delay. The method further includes, at a delay line, receiving the non-divided input signal, delaying the non-divided input signal for a time substantially equivalent to the first delay, and generating a second output clock signal associated with a second delay substantially equal to the first delay.

Abstract: Method and apparatus for data recapture from a source synchronous interface. A data signal is obtained via the source synchronous interface. A timing signal is obtained via the source synchronous interface, where the data signal and the timing signal are provided in association with one another. The timing signal is frequency divided by frequency divider to provide an enable signal. Data of the data signal is captured responsive to the timing signal and the enable signal, where the data captured is in a time domain of the timing signal. A data valid signal is generated from the enable signal and an internal clock signal, where the data valid signal is internally timed without having to determine a system level delay. The data is recaptured responsive to the internal clock signal and the data valid signal, where the recaptured data is in a time domain of the internal clock signal.

Abstract: Measure-controlled delay (MCD) circuits include a measure circuit and sample circuit for synchronizing an output clock to an input clock. In response to triggering of the measure circuit, sample circuits sample outputs of a measure delay array. Sample reset logic prevents output of the output clock when any of a predetermined one or more of the samples correspond to a particular logic value (i.e., logic “1” or “0”). For example, sample reset logic may prevent an MCD circuit from providing the output clock when a sample taken from the earliest sampling point of the measure delay array corresponds to logic “1.” The MCD circuit may then provide the output clock in response to a subsequent triggering for which a sample taken from the earliest sampling point is logic “0.” Phase error of the output clock is thereby reduced. MCD circuits improve response to process, voltage and temperature (PVT) variations.

Abstract: One embodiment of the invention is directed to a method, comprising acts of generating a plurality of delay signals, and processing at least first and second delay signals of the plurality of delay signals to generate a first timing signal. Another embodiment of the invention is directed to a timing signal generator to generate a plurality of timing signals. The circuit comprises a delay signal generator to generate a plurality of delay signals, and a clock synthesizer to generate the timing signals based on selected ones of the delay signals.

Abstract: A clock signal regeneration system and method to adjust the phase of a frequency-locked clock signal is provided. The system includes a numerically controlled oscillator, a clock source, and an adder. In one embodiment, additional components are included in the system to ensure that underflow or overflow of the numerically controlled oscillator is prevented. In another embodiment, additional components are included to ensure that output pulses from the numerically controlled oscillator do not occur within a minimum time interval. The method includes deriving a phase adjustment factor, adding the phase adjustment factor to a frequency control word, providing the modified frequency control word to a numerically controlled oscillator and generating a phase shifted, frequency-locked output signal.

Abstract: Methods and circuitry for implementing high speed loss-of-signal detectors for use in Gb/s telecommunication applications. The invention measures bit error rate (BER) of the incoming data by comparing the phase of the clock signal extracted from the incoming data with that of a delayed version of the incoming data. The results of this comparison are averaged over time to arrive at the BER. The measured BER is compared to a predetermined threshold value to detect a loss-of-signal condition. The invention adjusts the amount of delay of the incoming data in such a manner as to minimize the capacitive loading on the data line and clock line introduced by the loss-of-signal circuitry.

Abstract: The apparatus measures timing variations, such as the jitter or wander in a timing signal (100) of a telecommunications network. A recovered clock signal is sampled and digitized to produce a series of digital clock samples which are then processed (135) with reference to a local digital reference signal to produce digital baseband frequency in-phase (I) and quadrature (Q) components (165, 170) these being further processed (145) to produce the digital phase information of said clock signal to determine (175) the required parameters of the network. The step of digitally processing said clock samples with reference to a local reference signal can be conveniently and cheaply implemented using a digital signal down-converter IC (135), for example of a type existing for digital radio receiver implementations. For jitter measurement, the local reference signal may be generated by a phase-locked loop (as in FIG. 2). For wander measurements an external reference clock is used (as in FIG. 3).

Abstract: In a semiconductor device of the present invention, a clock is not changed instantaneously but it is changed over maximum N+1/M clocks (N: integer not less than 2) by shifting delay cells in a step by step manner to make the phase state of a previous reference signal and the phase state of a present reference signal coincide with each other, whereby the clock is synchronized with the reference signal with accuracy, and the duty of the output clock is kept constant. With this semiconductor device, it is possible to prevent the duty of the clock from being discontinuous when a signal whose reference signal does not coincide with the clock is inputted and reset is made to a rising edge of this reference signal.

Abstract: A phase alignment circuit having a phase selection circuit, a synchronizer, and a counter form a feedback loop for aligning a local clock signal with a received reference clock of a synchronous communications system. The phase selection circuit is configured for outputting the local clock signal as a phase-adjusted local clock having a selected phase based on a phase selection value specified by the counter. The synchronizer is configured for digitally sampling the received reference clock relative to the phase-adjusted local clock, and outputting a digital phase bit identifying whether the phase-adjusted local clock has a later phase relative to the received reference clock. The counter selectively increments or decrements a counted value based on the digital phase bit, and outputs to the phase selection circuit a prescribed number of most significant bits from the counted value as the phase selection value.

Abstract: A method for adjusting a clock and an electronic device with clock adjusting function are provided. In the method of adjusting the clock, the electronics device is driven with a first clock when the electronic device is during the reset-inactive state. Then, the electronic device is driven with a second clock when the electronic device receives a reset signal. Wherein, the cycle of the second clock is larger than that of the first clock.

Abstract: There is a clock recovery circuit to correct the timing relationship between a data signal and clock signal. The clock recovery circuit comprises a phase detector having an input for receiving a clock signal having a period, an input for receiving a data signal, and an input for receiving a window signal. The window signal has a period equal to the period of the clock signal and phase difference of ?90° with respect to the clock signal. The phase detector generates an up output and a down output while maintaining a phase relationship of the up output and the down output in response to the phase relationship between the clock signal and the data signal.

Abstract: In a method for measuring jitter, a signal under test is inputted to generate signal transition locations. A signal transition location is latched using a sampling clock signal, and the signal transition location is converted to a delay value. The delay value is converted to an edge position output, and a value of the edge position output is detected.

Abstract: A delay-locked loop (DLL) acquires correct lock when the delay line on the DLL delays a reference signal by one clock period. False lock occurs when the delay line delays the reference signal by more than one clock period. False lock may be detected by a false lock detector. The false lock detector may include (1) flip-flops to take samples of the delay line outputs and (2) combinational logic for detecting patterns in the samples that may indicate false lock. Once false lock has been detected, a hold circuit may ensure that false lock persists for at least the amount of time required by the DLL to acquire lock (i.e., to prevent reset of the DLL before it has acquired lock). After this determination is made, a reset generator may produce a reset signal for resetting the DLL.

Abstract: A multiplicity of electronic devices is provided to generate triangular wave signals variable between an upper and lower limit voltages by charging or discharging capacitors. One of the triangular wave signals serves as a master triangular wave signal for controlling the phases of the remaining (or slave) triangular wave signals. A detection signal is generated every time the master triangular wave signal reaches predetermined threshold levels. In response to the detection signal, a capacitor associated with one slave triangular signal is promptly discharged to bring the slave triangular signal to the lower limit voltage, whereby the respective slave triangular wave signals are synchronized to be offset in phase relative to the master triangular wave signal by respective predetermined phase angles.

Abstract: An interface circuit which outputs a clock signal and data to a data register that serially reads in the data synchronously with the clock signal, in response to a control signal changing from one level to the other level, for outputting the clock signal and the data. The interface circuit comprises a clock output circuit that, responding to the level of the clock signal when the control signal changes from the one level to the other level, outputs clocks of the clock signal that are the same in number as bits of the data to the data register.

Abstract: A clock generation system for generating a first-, a second-, and a third-reference frequency clocks having respective frequencies having predetermined ratios to the reference frequency of a reference clock, using PL circuits in such a way that the clocks have sufficient S/N ratios in spite of the S/N ratio limitation by the noise floor. A first reference frequency clock is supplied to a first PLL circuit to generate an intermediate-frequency clock having an intermediate frequency having a predetermined ratio to the reference clock. The intermediate-frequency clock is supplied to a second and a third PLL circuits to generate a second and a third reference frequency clocks having frequencies respectively having a second and a third ratios to the intermediate frequency, respectively.

Abstract: Measure-controlled delay (MCD) circuits are provided for synchronizing an output clock to an input clock. In response to triggering of a measure circuit, sample circuits sample outputs of a measure delay array. Sample reset logic prevents output of the output clock when any of a predetermined one or more of the samples correspond to a particular logic value (i.e., logic “1” or “0”). For example, sample reset logic may prevent an MCD circuit from providing the output clock when a sample taken from the earliest sampling point of the measure delay array corresponds to logic “1.” The MCD circuit may then provide the output clock in response to a subsequent triggering for which a sample taken from the earliest sampling point is logic “0.” Phase error of the output clock is thereby reduced. Clock synchronization circuits with improved response to process, voltage and temperature (PVT) variations are also provided.

Abstract: An arrangement for generating a clock signal. Embodiments provide a method, apparatus, system, and machine-readable medium to interpolate phases of a reference clock signal to output an interpolated clock signal. Some embodiments may output the clock signal as a recovered clock signal for a phase interpolator-based clock recovery system. Many embodiments may interpolate a changing phase of an interpolated clock signal with substantially analog transitions.

Abstract: In a method and system for controlling a device coupled to an information handling system, an object is defined to include a hardware and software component having a corresponding hardware operating state and a software operating state. The hardware component is operable to receive at least one hardware input, which is indicative of a target hardware operating state. The software component is operable to receive at least one software input, which is indicative of a target software operating state. A coordination component is included in the software component to receive the hardware and software inputs, and control the operating state of the device in response to the target hardware operating state and the target software operating state.

Abstract: A dual-edge synchronized sampler having an efficient implementation for high speed and high performance operation is described. The sampler receives a data input signal and a clock input signal and uses an asynchronous level mode state machine to sample the data input signal responsive to level changes in the clock input signal. In some embodiments, the sampler includes at least one differential logic block for implementing the asynchronous level mode state machine. The sampler has symmetric clock-to-Q propagation delays for both rising and falling edges of the clock input signal. The sampler may include toggle functionality, and may include edge control logic for configuring the sampler as one of a rising edge and falling edge sampler.

Abstract: A technique is described for simultaneously and synchronously transmitting digital data and a clock signal in a digital integrated circuit, circuit board, or system. The technique is based on the phase shift keying (PSK) modulation of an RF high frequency carrier which is distributed on low impedance interconnection transmission lines. The PSK modulation contains the digital data while the carrier itself constitutes the clock signal, and the clock signal and digital data are transmitted in a synchronous manner. The carrier frequency may be near fT, the maximum operation frequency of the transistors. Since the digital data and clock signal are simultaneously transmitted on the same interconnection, the digital data never becomes skewed with respect to the clock signal, or vice versa.

Abstract: Clock signal control circuitry including a selector for selecting between a first clock signal and an inverse of the first clock signal and a phase detector for determining a phase relationship between the first clock signal and the second clock signal and in response causing the selector to select between the first clock signal and the inverse of the first clock signal.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: In a transmitting apparatus 101, there are provided PLL circuit 601 for generating high-speed clock signals up to 2m times (m being a positive integer) from a basic clock signal, and a clock generating circuit 600 for generating a communication clock signal (S-CLOCK) and a reception timing signal (S-LATCH*) as independent clocks of any time length with using the generated high-speed clock signal as the smallest unit.