Abstract: The present invention provides a system for providing high-resolution calibration of a programmable semiconductor component (518). The system calibrates the programmable semiconductor component, within a desired accuracy, to a goal value (802). The system provides a primary DAC function (510) and a supplemental DAC function (512), as well as a control function (506). The control function is utilized to determine a first bit step (806) of the primary DAC function that corresponds to the goal value. The control function then determines a second bit step (810) of the supplemental DAC function that corresponds to the goal value. The bit codes of the first and second bit steps are combined by a summing function (514), to provide a programming control word for the programmable semiconductor component.

Abstract: Single line synchronization enables two or more oscillators to be synchronized with each other by using only a single control line. The synchronization can be accomplished without any external components. A single external component can be used to lower the frequency of an oscillator as in a master/slave-synchronized system. The use of the single control line (which can be embodied using a single integrated circuit pin) reduces the die area in which synchronization circuitry is situated. The single pin interface and reduced die area are advantageous for many applications that require small packages with a limited number of pins.

Abstract: A FIFO design interfaces a sender subsystem and a receiver subsystem operating on different time domains. The sender subsystem and the receiver subsystem may be synchronous or asynchronous. The FIFO circuit includes a put interface configured to operate in accordance with the sender time domain and get interface configured to operate in accordance with the receiver time domain. The FIFO circuit includes an array of cells having a register and state controller indicative of the state of the cell. Each cell also has a put component part configured to operate according to the sender time domain including a put token passing circuit and put controller circuit. Each cell has get component part configured to operate according to the receiver time domain including a get token passing circuit and a get controller circuit. A mixed-clock relay station design interfaces a sender subsystem and a receiver subsystem working at different time domains, and where the latency between sender and receiver is large.

Abstract: Circuits and methods are provided for clock adjustment. A method for clock adjustment includes receiving feedback clocks from independent ASIC modules. The method includes comparing the feedback clocks to a reference clock to generate phase measurement values. A common delay is removed from the phase measurement values to form normalized correction values. Target phase values and clock select values are selected using the normalized correction values. And, clock signals to independent ASIC modules are adjusted based on the target phase values and clock select values.

Abstract: A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal.

Abstract: A clock non-synchronous type circuit performs data read operation on the basis of a read control signal. After a lapse of a predetermined delay time, read data is read out from the clock non-synchronous type circuit. The read data is latched in selected one of N latch circuits. A latch circuit is selected on the basis of a control signal instead of a clock signal. The control signal represents that read data is output from the clock non-synchronous type circuit, and hence a latch circuit is always selected after read data is output.

Abstract: Delay-locked loops, signal locking methods and devices and system incorporating delay-locked loops are described. A delay-locked loop includes a forward delay path, a feedback delay path, a phase detector and a timer circuit. The forward delay path alternatively couples to an external clock signal and to an internal test signal. The phase detector adjusts a delay line based upon the phase differences of a feedback signal and the external clock signal. The timer circuit switches the test signal into the forward delay path and measures the time of traversal of the test signal around the forward delay path and the feedback delay path and generates a time constant for configuring the phase detector's update period. The phase detector is thereafter able to stabilize at an improved rate.

Abstract: A DLL circuit includes a delay circuit, a phase comparing circuit and a delay control circuit. The delay circuit is connected to first and second nodes, and delays an original clock signal supplied to the first node based on a delay control signal and generates first to n-th (n is an integer more than 1) internal clock signals. The first internal clock signal is outputted from the second node. Also, the internal clock signals other than the first internal clock signal are outputted from the delay circuit without passing through the second node, and lead the first internal clock signal in phase. The phase comparing circuit compares the original clock signal supplied from the first node and the first internal clock signal supplied from the second node, and outputs a phase difference of the original clock signal and the first internal clock signal. The delay control circuit outputs the delay control signal to the delay circuit based on the phase difference outputted from the phase comparing circuit.

Abstract: The invention provides an improved differential output structure with minimal skew and introduces less process variations. According to one embodiment of the invention, a differential output structure is provided and comprises an input line, an output driver and a sync circuit. The input line includes first and second paths. The first path has an input end for receiving input signals. The first path also has an output end and includes at least one driving element. The second path has an input end operably coupled to the input end of the first path for receiving the input signals. The second path also has an output end. The output driver is operably coupled to the output ends of the first and second paths and is configured to provide differential outputs. The sync circuit is operably coupled between the first and second paths and is configured to synchronize the speed of signals traveling on the two paths.

Abstract: A programmable skew clock signal generator has a frequency generator circuit (104) consistent with the invention produces an output signal F&phgr;0 from a reference signal Fref A frequency accumulator (132, 152) is preloaded with a preload value PK1 and receives one reference signal cycle as a clock signal, receives a constant K1 as an input thereto, with the frequency accumulator (132, 152) having a maximum count KMAX and producing an overflow output. A phase accumulator (136, 156) is preloaded with a preload value PC1 and receives one overflow cycle output from the frequency accumulator (132, 152) as a clock signal and receives a phase offset constant C1 as an input thereto. The phase accumulator (136, 156) has a maximum count CMAX and produces a phase accumulator (136, 156) output. A delay line (320) is clocked by the reference signal Fref and produces a plurality of delayed reference clock signals at a plurality of tap outputs.

Abstract: A clock signal generator providing an output clock signal synchronized with an input clock signal having an input clock frequency including a frequency dependent variable delay line to accommodate a wide range of operating frequencies. A clock signal synchronized with an input clock signal propagated through an input time delay and an output time delay is generated by delaying an input buffered clock signal by a first time delay based on the frequency of the input buffered clock signal, and further delaying the delayed input buffered clock signal by a second time delay to compensate for timing skew introduced by the input time delay, the output time delay and the process of delaying the input buffered clock signal.

Abstract: A clock shaping device is provided that includes: a first clock signal selection portion that receives an input of a reception clock signal and an input of a back-up clock signal from the outside, and selects either of the clock signals; a quartz crystal oscillation circuit that oscillates at a predetermined frequency; a second clock signal selection portion that receives an input of a clock signal from the first clock signal selection portion and an input of a clock signal from the quartz crystal oscillation circuit, and selects either of the clock signals; a voltage controlled oscillation circuit whose frequency varies with a control voltage being supplied and generates and outputs a feedback loop output signal; a phase comparison portion that generates a phase difference signal based on a result of comparing the feedback loop output signal from the voltage controlled oscillation circuit and a clock signal outputted from the second clock signal selection portion; and a loop filter that smoothes the phase di

Abstract: The invention relates to a process for generating a synchronizer pulse, in particular a clock pulse, as well as a synchronizer signal generator device, which is connected to an electronic system, and which emits a synchronizer signal of a particular frequency, which is transferred to at least one device of the electronic system, whereby at least one device is provided with its impedance selected so that a resonance oscillatory circuit—of which the resonance essentially coincides with the frequency of the synchronizer signal—is created for the synchronizer signal generator device.

Abstract: A clock tree distribution network for a field programmable gate array comprises an interface that has a root signal chosen from at least one of an external clock signal, an internal clock signal, a plurality of phase lock loop cell output signals and programmable elements. The FPGA includes a logic array that has programmable elements coupling the logic array to a programmable routing architecture and the interface. A routed clock network selects a signal from between a clock signal from the interface, a local signal from the logic array through the routing architecture, Vcc or ground, and routes the selected signal to the logic array through the clock tree distribution network. A hardwired clock network that selects a signal from between a clock signal from the interface and a local signal from the routing architecture, and routes the selected signal to a plurality of flip-flops in the logic array through the clock tree distribution network.

Abstract: A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. A reference clock signal is propagated along a source path and a return path, both of which pass near the registers. At each register, an averaged clock signal is generated, based on the phases of the reference clock signal on the source and return paths. Individual component clock signals are then adjusted separately to minimize differences between the component clock signals and the respective averaged clock signals at each of the registers.

Abstract: A delay-locked loop adjusts a delay of a clock signal that is generated in response to an external clock signal. The clock signal is applied to an output buffer to clock the buffer so that data or clock signals from the buffer are synchronized with the external clock signal. The output buffer operates in a full-drive and reduced-drive mode in response to an output drive strength bit having first and second logic states, respectively. The delay-locked loop adjusts the delay of the clock signal in response to the state of the output drive strength bit to keep the data or clock signals from the buffer synchronized during both modes of operation.

Abstract: A power reduction device which includes a first clocking device for generating a first clocking signal, a second clocking device for generating a second clocking signal, a synchronizer device for receiving the first and second clocking signals and being responsive to a first select signal and to a second control signal wherein upon receipt of either of the select or control signals, the synchronizing device generating a synchronized signal without a glitch therefrom wherein the synchronized signal corresponding to either the first or second clocking signals.

Abstract: A semiconductor integrated circuit having a system bus divided into stages and configured to transfer signals, stage elements configured to connect the stages in series and operate in a divided mode transferring signals from a stage on an input side to a stage on an output side in synchronization with a clock signal and in a through mode that always passes signals from the stage on the input side to the stage on the output side, and a plurality of function modules connected to the different stages.

Abstract: The present invention includes an integrated circuit that can use a high-frequency timing reference generator from a high-speed serial interface to provide the clocking and timing requirements for the integrated circuit. The timing mechanism in the present invention obviates the need for phase locked loop (PLL) macrocells to provide timing reference and timing signals in the IC. The ICs of the present invention are preferably used as disk drive integrated circuits that include DSP, memory, data path controllers, data interfaces, custom macrocells, and DSP peripherals. The high-speed serial interface is preferably a Serial ATA (SATA), Universal Serial Bus (USB), Fiber Channel, or Serial Attached SCSI (SAS), among others.

Abstract: Group-wise testing of the clocks arriving at a switching office is undertaken by multiplexing the clocks onto a single line and developing a signal therefrom that is indicative of a problem, if it exists, in any of the component signals that were multiplexed. In one embodiment, the developed signal is a gated portion of the multiplexed signal. That signal is integrated over an integration frame and compared to the integrated signal of another integration frame. A difference between the two compared signals indicates that at least one of the clocks is out of frequency synch. Subsequent tests identify the offending clock, or clocks.

Abstract: A synchronous clocking method and apparatus is disclosed for clocking a plurality of processing units. Each of the plurality of processing units is connected to at least another one using an interblock synchronization signal. Upon receipt of the interblock synchronization signal, data is provided between at least two processing units.

Abstract: A semiconductor integrated circuit, comprises a first reference voltage line; a second reference voltage line; a plurality of single logic circuits each including a plurality of transistors; a first switch having a first transistor provided between said first reference voltage line and said logic circuits, said first transistor having a higher threshold voltage than that of transistors in the logic circuits; and a second switch having a second transistor provided a between said second transistor having a higher threshold voltage than that of transistors in the logic circuits, said first and second switches being turned on when at least one of said single logic circuits is in operation, while said first and second switches being turned off when all of said single logic circuits are in standby state.

Abstract: A method and apparatus adjusts a propagation delay through a receiver circuit. A transmission apparatus is arranged to generate a control signal where an impedance of a driver circuit is dependent on the control signal. A bias generator is operatively connected to the transmission apparatus and is dependent on the control signal. A receiver circuit is operatively connected to the bias generator where the bias generator is arranged to operatively adjust a propagation delay through the receiver circuit.

Abstract: The present invention provides a clock signal feeding circuit that suppresses performance degradation under the worst operating conditions. A clock signal CLK is fed, via a delay buffer with a capacitor as a delay element, to a FF disposed in the upstream of a logic circuit block having the longest processing time, and a clock signal CLK is fed, via a delay buffer with a transistor as a delay element, to a FF disposed in the downstream of the logic circuit block having the longest processing time. If the processing time of the logic circuit block increases due to factors such as variations in operating environment, and thus outputting of data representing the operation result delays, the timing of the clock signals fed to the FFs also delays due to the same factors.

Abstract: A phase locked loop that includes a receiver that is adjustable to substantially match delay of a system clock and a feedback clock at an input of the phase locked loop is provided. The receiver employs system clock path circuitry to input the system clock and feedback clock path circuitry to input the feedback clock, where current flow and load resistances associated with the system clock path circuitry and current flow and load resistances associated with the feedback clock path circuitry are responsive to one or more bias signals that are adjustable using one or more adjustment circuits that are operatively connected to the receiver. The control of the one or more bias signals via the one or more adjustment circuits facilitates the generation of substantially delay matched system and feedback clocks.

Abstract: A system and method for providing synchronous clocking allows for precise control of the phase relationship of the clocking signals to thereby provide accurate duty cycles for proper system operation. A digital logic circuit, such as a D-type flip-flop, is provided with a phase signal and clock signal having a frequency relationship. The output of the digital logic circuit is a function of the phase signal and clock signal. The synchronous output may be provided to multiple locations within a system to allow for a synchronous local clock in each of the locations.

Abstract: A clock synchronization circuit includes a first delay circuit for delaying a clock signal and outputting the delayed clock signal, first and second bidirectional delay circuit strings, a first pre-stage delay circuit and a first post-stage delay circuit of variable delay time type, arranged in a pre-stage and a post-stage of the first bidirectional delay circuit string (BDDA), a second pre-stage delay circuit and a second post-stage delay circuit of variable delay time type, arranged in a pre-stage and a post-stage of the second bidirectional delay circuit string (BDDB), and a multiplexer, supplied with and multiplexing outputs of the first and second post-stage delay circuits to output the resulting signals. An output signal of the first delay circuit is supplied in common to the first and second pre-stage delay circuits.

Abstract: A semiconductor integrated circuit comprises therein a plurality of logic circuits synchronously designed to operate in synchronization with a clock signal, a first power supply wire for supplying a high-potential side power supply voltage from a first input terminal to each logic circuit, a second power supply wire for supplying the high-potential side power supply voltage from a second input terminal to each logic circuit and a third power supply wire for supplying the high-potential side power supply voltage from a third input terminal to each logic circuit. The logic circuit (DFF circuit) includes two stages of latch circuits and a clock signal inversion circuit. Only the clock signal inversion circuit is connected with the first power supply wire, while the second power supply wire is connected with the remaining latch circuits.

Abstract: A semiconductor device includes a clock input terminal to which external clocks are supplied; a PLL circuit, which is supplied with the external clocks and generate first internal clocks; a logic circuit, which operates in synchronization with the internal clocks; and an internal counter, which counts the first internal clocks when the PLL circuit is tested. The internal counter is provided with an output terminal from which an output signal thereof is supplied to an external circuit.

Abstract: The present invention provides a method and apparatus, for integrated circuits, that is able to generate clock signals at different destination points with little or no clock signal delay or skew. A slow rising input clock signal is propagated across a low loss transmission line. The slow rising input signal creates a region of substantially no clock signal delay between the signal at the beginning of the low loss transmission line and the signal at the end of the low loss transmission line. Comparators are used to compare the signals at the beginning and end of the low loss transmission lines and compare them to a reference signal. The compared signals are sampled during the region of substantially no clock signal delay or skew. The sampled clock signals with substantially no delay are sent to local destination points or other low loss transmission lines within the integrated circuit to transmit the signal to remote destination points.

Abstract: A method and apparatus for synchronizing a synchronizing clock is disclosed for use in synchronizing a high-speed memory bus with a second, heritage memory bus. This method and apparatus includes generating an initial synchronizing clock from a reference clock of the high-speed memory bus. It then includes receiving a synchronizing packet on the high-speed memory bus utilizing the initial synchronizing clock. Finally, it includes delaying a clock transition of the initial synchronizing clock in response to the received data of the synchronizing packet.

Abstract: A synchronizer eliminates metastability due to violation of either the setup time or the hold time of a circuit. The input of a first flip-flop (12a) is tied to a constant logic level (VDD or ground). The first flip-flop receives an asynchronous signal into the reset (preset or clear) input of the flip-flop. No violation of the setup or hold times of the flip-flop can occur. The second flip-flop (12c) receives the output of the first flip-flop as its clock input. The second flip-flop (12c) is configured as a toggler. The second flip-flop produces a synchronized partial signal (18a) of the original asynchronous signal (10a). Third and fourth flip-flops (12b,12d) may similarly be configured to produce a second synchronized partial signal (18b) of the asynchronous signal recovery and may prevent runt pulses from being received by the flip-flops.

Abstract: One embodiment of the present invention provides a system that matches speeds of asynchronous operation between a local chip and a neighboring chip. The system derives an internal frequency signal from an internal oscillator on the local chip, and receives an external frequency signal from a neighboring chip. The system then compares the internal frequency signal with the external frequency signal to generate a control signal, which is applied to the local chip to adjust the operating speed of the local chip, and applied to the internal oscillator to adjust the frequency of the internal oscillator.

Abstract: The invention relates to an interconnect, and to interconnect architecture, for communicating between processing elements and memory modules in a computer system comprising on-chip parallel computation, in order to reduce the tight synchrony that is required by important components of most present computers.

Abstract: In an integrated circuit receiving multiple serial data streams in parallel, a local clock is generated from each data stream and is synchronised with the data stream. Sometimes a data stream may have no transitions making it difficult to keep the clock synchronised with its data. A clock channel is provided, which always has edges. A circuit is provided for each data stream which measures the time elapsed since the data stream had an edge. After a certain period, the phase of the local clock is nudged towards that of the clock channel. Thereafter, the longer there are no edges on the data stream the more frequently nudges towards the phase of the clock channel are made.

Abstract: An integrated circuit has a synchronous circuit and an asynchronous circuit. A clock-controlled input register circuit and an output register circuit for storing data are each connected to the synchronous circuit and the asynchronous circuit. Data are transferred from the synchronous circuit into the input register circuit, from where they are transferred into the asynchronous circuit and processed in the asynchronous circuit. Processed data are transferred into the output register circuit. A sequence controller generates a respective control clock signal for the register circuits in a manner dependent on the data processing duration of the asynchronous circuit. This enables a high data throughput between the synchronous circuit and the asynchronous circuit independently of a clock frequency of the synchronous circuit.

Abstract: A source synchronous bus system is provided with a bus; a first device connected to the bus, having a driver to drive data and strobe signals, via the bus; and a second device connected to the bus, having a receiver to receive data and the strobe signals from the bus, and to select one of rising and falling edges of the strobe signals to latch a corresponding one of rising and falling edges of the data received from the bus, for subsequent data processing functions in order to compensate for systematic differences between rising and falling edges of the data received, via the bus.

Abstract: Methods and Apparatuses for generating and distributing a clock signal between components within a semiconductor chip. According to one embodiment of the invention, a clock generator, distributed over an integrated circuit, includes a plurality of cells each coupled to multiple adjacent ones of the plurality of cells by different clock wires; wherein, for each of the plurality of clock wires, the cell on one end generates the rising edge and the cell on the other end generates the falling edge. According to another embodiment of the invention, an integrated circuit includes a distributed clock generator and a plurality of sets of synchronous logic. The distributed clock generator includes a plurality of cells and a plurality of clock wires. The plurality of clock wires each couple together two of said plurality of cells such that said plurality of cells are coupled together in grid.

Abstract: The present invention discloses a spike free circuit, which comprises a first flip-flop stage, a time shift means, a group of logic gates and a second flip-flop stage. The first flip-flop stage is triggered by a first edge of a clock signal. The time shift means is electrically connected to the first flip-flop stage and triggered by a second edge opposite to the first edge of the clock signal. The time shift means shifts input signals, which change logic level within the first to the second edges of the clock signal one half cycle for preventing spike occurring. The group of logic gates is connected to the time shift means. The second flip-flop stage is electrically connected to the group of logic gates and triggered by the first edge of the clock signal.

Abstract: The invention relates to a method and circuit for synchronizing two signals triggered by clocks of different frequencies, which samples the lower frequency write-enable signal at both positive and negative edges of the higher frequency clock. If the sampling result at the positive or negative edge of the higher frequency clock is “1”, the state is recorded to be a “lock state” and no sampling is taken from the next opposite edge. If the sampling result at the positive or negative edge is “0”, the state is recorded to be a “sampling state” and the next opposite edge will be sampled. Finally, the sampling results taken at the positive and negative edges are joined to output a synchronized write-enable signal.

Abstract: A programmable current reference circuit is described. The programmable current reference circuit includes a programmable resistance, where the programmable resistance is programmable to provide one of a plurality of resistances, where each of the plurality of resistances corresponds to one of a plurality of programmable current reference circuit outputs. In one embodiment, the programmable current reference circuit includes a current source coupled to the programmable resistance. In one embodiment, the plurality of programmable current reference circuit outputs includes a plurality of reference currents. A phase locked loop including the programmable current reference circuit is also described.

Abstract: Methods and structure for improving accuracy of a master delay line associated with slave delay lines wherein the master delay line is design utilizing a higher clock frequency then the clock frequency applied to associated slave delay lines. The higher clock frequency applied to the master delay line in accordance with the present invention permits the master delay line to be comprised of fewer delay elements than would be the case for a master delay line using the same basic clock frequency as associated slave delay lines. The lower number of delay elements comprising the master delay line (i.e., the shorter length of the master delay line) helps reduce static phase errors associated with the master delay line inherent in the design, layout and fabrication of a longer delay line.

Abstract: A synchronization circuit comprises a state detection circuit for outputting a control signal according to the temporal relationship between a transition point of an input signal and an edge of a synchronization clock; a delay selection circuit for adding a delay to the input signal on the basis of the control signal; and a latch circuit for synchronizing the signal outputted from the delay selection circuit with the synchronization clock. Therefore, synchronization of the input signal can be carried out without adding latency to the input signal.

Abstract: A clock controller and clock generating method are provided for AC self-test timing analysis of a logic system. The controller includes latch circuitry which receives a DC input signal at a data input, and a pair of continuous out-of-phase clock signals at capture and launch clock inputs thereof. The latch circuitry outputs two overlapping pulses responsive to the DC input signal going high. The two overlapping pulses are provided to waveform shaper circuitry which produces therefrom two non-overlapping pulses at clock speed of the logic system to be tested. The two non-overlapping pulses are a single pair of clock pulses which facilitate AC self-test timing analysis of the logic system.

Abstract: An input circuit according to the present invention has a data input means for the input of input data; a data latch means for latching the input data; a reset means for resetting the data latch means; a clock synchronization means for synchronizing the input of the input data to the data input means; and a latch enhancement means for blocking feedthrough current by functioning complementarily to the reset means, and enhancing the latching operation of the data latch means.

Abstract: A data input circuit for use in a semiconductor device, the data input circuit reducing a load difference between a fetch signal and a plurality of groups of data. The data input circuit includes first through Nth latching units for latching each one of N groups of data in response to a reference clock, respectively (N is a natural number greater than 2), and a bus for transmitting the reference clock and the N groups of data to the first through Nth latching units. Each of the first through Nth latching units includes a clock buffer for buffering the reference clock; a data buffer for buffering a corresponding group of data of the N groups of data; N−1 dummy elements for respectively receiving each one of the N groups of data, except for the group of data input to the data buffer; and latches for latching data output from the data buffer in synchronization with a signal output from the clock buffer.

Abstract: A synchronization variable intended for a second clock signal is generated from a first clock signal and a phase variation signal. A first approximation of the second clock signal is determined, and other approximations close to the first approximation are also determined. An error is calculated for each of the approximations, and the best approximation is taken as the second clock signal.

Abstract: An impedance adjustment circuit generates an internal impedance adjustment signal and an impedance adjustment entry signal based on an externally applied impedance control signal. A data processing circuit decodes the internal impedance adjustment signal in synchronization with an internal clock signal to generate an output buffer drive signal of 5 bits. When the output buffer drive signal is applied to an output circuit of the succeeding stage as well as to an output replica circuit in a DLL circuit, the impedance of the output replica circuit is adjusted following adjustment of the output impedance.

Abstract: An electronic package and method for spatially distributing a clock signal is presented. The electronic package includes a low-loss structure, a semiconductor die, clocking vias, and clock receivers on the die. The low-loss structure is constructed and arranged to be driven by a clock signal and to produce standing waves. The clocking vias are constructed and arranged to connect the low-loss structure to the die and to conduct the standing waves to the die. The clock receivers generate respective synchronous on-chip clock signals based at least in part on the conducted standing waves.

Abstract: A frequency divider divides a frequency of a DLL clock CLK_P into two, to generate ZCLK_PD0 and ZCLK_PD1. A delay circuit generates ZCLK_PDD0, ZCLK_PDD1 obtained by delaying ZCLK_PD0, ZCLK_PD1 respectively by Tc (=a backward amount of CLK_P with respect to an external clock+a delay amount of an internal clock with respect to the external clock). A frequency division select instruction circuit generates ZSEL0, ZSEL1 based on an internal clock CLK, and ZCLK_PDD0, PDD1. A ZSEL0 shifter circuit generates ZSEL1_D2 including a clock pulse of ZSEL1. A ZCLK_P #2 select circuit selects a clock pulse of ZCLK_PD0 using ZSEL1_D2.