Abstract: Clock signals of the same phase are formed even when signal delays occur in clock signals transmitted on a clock line. In a clock synchronizing circuit which synchronizes circuit elements using clock signals taken from a common clock line, the clock line is bent midway into a pair of clock lines, and a center phase signal generating means generates a clock signal having a phase which is in the center of two clock signals of differing phase obtained from arbitrary points on the pair of clock lines which are at equal distances from the point at which the clock line is bent over. By using pairs of clock signals of differing phases taken at equal distances from the bend over point, three clock signals all having equal phase are obtained.

Abstract: A synchronizing means is provided for synchronizing an asynchronous interrupt signal to a synchronous clock signal for a computer system or the like. The synchronizing means includes a plurality of latch subsystems, where each of the latch subsystems has a sample input terminal for receiving a synchronous clock signal and a hold terminal for receiving a complementary synchronous clock signal. Set logic means are provided for generating a set output signal in response to certain predetermined output signals of the synchronizing means having a predetermined relationship therebetween, which occurs when an input interrupt signal has a duration greater than 1.5 periods of the synchronous clock signal. The set logic means includes AND gates and OR gates. Reset logic means are provided for generating a reset output signal. The reset logic means includes AND gates and OR gates.

Abstract: A clock phase and frequency distribution system is disclosed which uses a standing sine wave and provides substantially simultaneous significant crossing instances everywhere in the system while using low power and not requiring bus termination or precise control of transmission path characteristics (Z.sub.0). The system is particularly advantageous in high frequency applications such as digital, linear (non-branched), backplane applications, but is also applicable to other topographies such as stars, rings, and meshes. The system includes a sine wave generating and driving circuit, a clock bus, and clock receivers. The clock receivers present a high impedance interface to the clock bus.

Abstract: Circuitry for switching between a first and second clock signal is provided having a first local clock circuit 202, a first synchronizing circuit 200 connected to said first clock circuit 202, a first delay circuit 206a-d connected to said first synchronizing circuit 200 and said first clock circuit 202, a second delay circuit 206e, 210, connected to said first delay circuit 206a-d and said first clock circuit 202, a first logic circuit 220 connected to said first 206a-d and second 206e, 210 delay circuits and said first synchronizing circuit 200, a second local clock circuit 102, a second synchronizing circuit 100 connected to said second clock circuit 102, a third delay circuit 106, 108, 110, connected to said second synchronizing circuit 100 and said second clock circuit 102, a second logic circuit 104 connected to said second clock circuit 102 and a portion of said third delay circuit 106, 108, 110, a third logic circuit 120 connected to said third delay circuit 106, 108, 110, and said second clock circui

Abstract: A synchronized clocking circuit receives a clock signal and, in accordance with the received clock signal, provides a divided-down clock signal having a known phase relationship with respect to the received clock signal upon reset. In order to provide the known phase relationship, and therefore to synchronize the received clock signal and the divided-down clock signal, a cycle of the divided down clock signal is selectably skipped. A reset signal is conditioned and applied to an active going edge detector. The cycle of the divided down clock is selectably skipped according to the active going edge detector.

Abstract: A method and apparatus for performing frequency detection in an all digital phase lock loop (10). Frequency detection is accomplished using a frequency detector (11), coupled to an digitally controlled oscillator (DCO 16). The frequency detector (11) forces phase alignment of a reference clock signal to the DCO (16) output and then counts the number the DCO (16) output pulses occurring during a reference clock period. The reference clock signal enables the DCO (16) on one signal transition and detects the presence of an oscillator counter (52) output on the same reference clock signal transition, but one reference clock period later. A synchronizer (49) is used to pass the counter (52) output to ensure no metastability. The DCO (16) is then disabled to allow frequency adjustments to occur via other circuitry.

Abstract: An up/down counter within a phase locked loop is gated to count high frequency clock pulses during the first cycle of the input signal. Upon detection of a transition in the input signal indicating the end of the first cycle, the direction of the count is reversed until the count is reduced to zero, thereby assuring equal widths for the first and second half cycles of each output cycle. The system may be implemented with or without a voltage controlled oscillator. In the latter implementation, the count in the up/down counter at the time of a reversal in the count direction is compared with the count in a preset counter. A difference counter compares the differences in a count in the two counters and adjusts the count in the preset counter to match that in the up/down counter at the time of transition. The widths of the successive cycles, rather than half cycles, may be made by doubling the output frequency relative to the input frequency.

Abstract: Adjustment of the output frequency of a frequency synthesizer can be optimized in the following manner. Once a frequency adjustment request is detected, which indicates a selected frequency, a frequency difference is calculated between the selected frequency and the present frequency. A frequency scaling factor is then determined. Once the frequency difference and the frequency scaling factor are determined, a frequency adjustment time is calculated based on a proportional relationship between the frequency difference and the frequency scaling factor. The bandwidth of a multi-bandwidth filter is adjusted to a second bandwidth for the duration of the calculated frequency adjustment time. The output frequency of the frequency synthesizer is adjusted from the present frequency to the selected frequency prior to the expiration of the frequency adjustment time. Upon expiration of the frequency adjustment time, the bandwidth of the multi-bandwidth filter is adjusted from the second bandwidth to the first bandwidth.

Abstract: A low power clocking apparatus and method is used to reduce power consumption by an electronic system or an integrated circuit that is coupled to an external system via a system bus which is configured to selectively transmit or receive signals from the electronic system or integrated circuit. The electronic system or integrated circuit includes a plurality of sub-circuits. Each sub-circuit is configured to operate under control of a clock signal and further includes an apparatus for keeping or rejecting the clock signal. Once each sub-circuit within the electronic system or integrated circuit rejects the clock signal, an integral arbiter circuit disables the clock signal to all the sub-circuits. The arbiter circuit continuously monitors the system bus. Upon detecting that the sub-circuits will require the clock signal, the arbiter will re-enable the clock signal to all of the sub-circuits.

Abstract: A frequency synchronous circuit has a first selection unit, a first counter unit, a second counter unit, a storage/average unit, and a comparison unit. The first selection unit is used to select one sampling signal from a first sampling signal having a first sampling time and a second sampling signal having a second sampling time shorter than the first sampling time. The first counter unit is used to count a reference signal supplied from outside the frequency synchronous circuit during the sampling time of the selected one sampling signal, and the second counter unit is used to count a synchronous clock signal to be output from the frequency synchronous circuit during the sampling time of the selected one sampling signal. The storage/average unit, which is operatively connected to the first counter unit, is used to store and average an output signal of the first counter unit.

Abstract: A simple digital method is disclosed for controlling the digital signals sent out from a pluralities of identical signal processors (i.e, signal generators) so as to achieve synchronization. The method comprises the steps of: (a) obtaining a gate array logic circuit containing a plurality of pairs of comparison terminals and reference terminals, each of the comparison terminals is connected to a respective signal processor and the reference terminals are respectively connected to at least two different signal processors; (b) performing a gate array logic circuit operation, which comprises the following sub-steps: (i) performing a waiting procedure for each pair of comparison terminal and reference terminal until it is received that the comparison terminal is "1" and the reference terminal is "0", then moving to a gate procedure; otherwise, continuing the waiting procedure (i.e., no disable signal is sent out); (ii) performing a gate procedure by continuously sending out a "1" gate signal, i.e.

Abstract: A clock synchronization system is constituted by first and second clock generating sections. The first and second clock generating units are alternately set in current and spare use modes. The apparatus clock from one clock generating section in the current use mode is supplied to an external circuit. In each clock generating section, a state signal generating section receives a first state signal representing one of the modes, and outputs a second state signal representing a set mode opposite to the mode represented by the first state signal to the other clock generating section. A clock generating section generates a clock synchronized with the network sync signal.

Abstract: There is disclosed a synchronizing pulse generating circuit wherein a synchronization lack correcting portion (600) processes a synchronizing signal (S601) to provide a corrected synchronizing signal (S600), and a synchronizing clock generating portion (700) generates a synchronizing clock (S700) accurately synchronized with the corrected synchronizing signal (S600), and then a synchronizing pulse generating portion (800) counts the synchronizing clock (S700) to provide a synchronizing signal (S800) accurately synchronized with the synchronizing signal S601, whereby the synchronizing pulse generating circuit generates high-accuracy synchronizing pulses without exteriorly attached parts and is adapted for generation of HD pulses for use in a deflecting system of a multi-synchronization type display monitor.

Abstract: A frequency synchronous circuit has a first counter unit, a second counter unit, a storage/average unit, and a comparison unit. The first counter unit is used to count a reference signal supplied from outside the frequency synchronous circuit during a sampling time which is defined by a sampling signal, and the second counter unit is used to count a synchronous clock signal to be output from the frequency synchronous circuit during the sampling time of the sampling signal. The storage/average unit, which is operatively connected to the first counter unit, is used to store and average an output signal of the first counter unit. The comparison unit, which is connected to the storage/average unit and the second counter unit, is used to compare an output signal of the storage/average unit with an output signal of the second counter unit, and the frequency synchronous circuit outputs the synchronous clock signal whose frequency is synchronized in accordance with an output signal of the comparison unit.

Abstract: A multi-level superposed amplitude-modulated baseband signal processor which has simple hardware structure and a filtering effect for bandwidth and power efficiency in a digital transmission system includes a data delayer, a signal level converter, an operator, two pulse generators, two adders and two amplifiers, thereby eliminating the need for conventionally required pulse waveforms and simplifying circuit structure. Specifically, when the number of the multi-levels is desired to be changed, the relevant multi-level superposed amplitude-modulated baseband signal can be provided by a simple change of the processor.

Abstract: A phase-locked loop circuit which utilizes multiple reference signals is formed with control circuitry to minimize time interval error. The phase-locked loop (PLL) comprises a switching device, phase detector, loop filter governable oscillator, frequency divider, signal sensing circuit and a TIE reduction control circuit. The PLL maintains a substantially constant .pi./2 radians between a first reference signal and its phase-locked output. Upon loss of the first reference signal, the signal sensing circuit causes the switching device to switch to a second reference signal. The second reference signal is of the same frequency but unknown phase relationship with the interrupted first reference signal. Upon switch over, the TIE reduction control circuit causes the frequency divider output to be interrupted and forced high for a quarter-cycle of the period of the reference signals to force the PLL to phase-lock on the second reference signal with minimal TIE.

Abstract: A timing generator contains an oscillator section (10) formed with a plural number of stages (S.sub.1 -S.sub.N) for respectively producing a like number of stage signals (V.sub.S1 -V.sub.SN) that sequentially change signal values at a basic oscillator frequency (f.sub.O). The oscillator section is typically implemented as a ring oscillator. In response to the stage signals, a timing-signal generating section (14) generates one or more timing signals (V.sub.T1 -V.sub.TM), each having at least two transitions corresponding to transitions of two or more of the stage signals. A control section (12), preferably arranged in a phase-locked loop, causes the oscillator frequency and a reference frequency (f.sub.R) to have a substantially fixed relationship.

Abstract: An information processing system comprises a sub-circuits, each performing a part of the processing of the information or data. The operation of the sub-circuits is synchronized by means of clock signals applied to clock inputs of the sub-circuits. The clock signals are derived from a system clock and are transferred to each sub-circuit via the sub-circuit or sub-circuits preceding that sub-circuit in the data processing chain. To avoid deterioration of the clock pulses while they are transferred between the sub-circuits, clock regeneration circuitry is arranged in the chain of sub-circuits. The clock regeneration circuitry is preferably integrated together with the data-processing sub-circuits.

Abstract: A system and method for estimating input phase for bit cells recovered from run length limited code where the bits cells have a nominal duration allows use of sampling rate as low as the nominal data rate in an all digital phase-locked loop. For the all digital phase-locked loop, a clock generates sample cells of a fixed duration. The sample cell phase contribution corresponding to a proportion of the fixed duration to the nominal duration is calculated and added to an accumulated phase value with each successive sample cell. For each sample cell, an input phase estimate is made from the accumulated phase value and timing information for any bit cell event occurring within the sample cell. Finally the input phase estimate information is used to adjust an accumulated phase value for the next sample cell.

Abstract: A perishable good integrity indicator includes a first oscillator for outputting a first clock signal which does not substantially vary in response to temperature. A second oscillator outputs a second clock temperature which varies as a function of temperature. A counter counts the pulses of the second clock signal during a time period determined by the first clock and outputs a count value. A data table receives the count value, translates the count value into a time temperature value representing the relationship of time and temperature during the time period and outputs the time temperature value to an adder. The adder adds the time temperature values output by the data table over time and outputs a cumulative time temperature value corresponding to shelf life for a product.

Abstract: A sensor circuit is disclosed for use with a clock circuit providing a periodic timing signal to a clock output, wherein a timing reference for the periodic timing signal is provided by a crystal connected between a crystal input and a crystal output of the clock circuit, or alternatively provided by an external periodic logic signal coupled to the crystal input. The sensor circuit provides a sensor output in a first state, thereby indicating the presence of an external periodic logic signal timing reference, in response to at least a given number of large-signal voltage transitions on the crystal input within a certain period of time, and otherwise provides a second state on the sensor output, typically to indicate the presence of a crystal timing reference. Also disclosed is a clock circuit including a sensor circuit, and further including means for disabling a feedback resistor necessary for crystal operation when the timing reference is determined to be provided by an external periodic logic signal.

Abstract: An integrated circuit charge pump circuit including a plurality of stages, each stage including a first N type field effect switching transistor device having source and drain terminals connected in series with the source and drain terminals of all other stages, a second N type field effect control transistor device having drain and source terminals connecting the drain terminal and the gate terminal of the first switching transistor device, and a storage capacitor joined to the source terminal of the first device; a source of voltage to be pumped is connected to the drain terminal of the first device of the first stage.

Abstract: A configuration generates a clock signal from a digital signal by evaluating signal edges of the digital signal. A first device generates a pulse at a signal edge oriented in a first direction, and a second device generates a pulse at a signal edge oriented in a second direction being opposite the first direction. Each of the devices has one terminal for receiving a digital signal and one output. A voltage-controlled, triggerable oscillator device has at least two trigger inputs, one control input and one output. Each of the trigger inputs is connected to the output of a respective one of the first and second devices, and the output of the oscillator device is an output for the clock signal. An integration device has an input connected to the output of the oscillator device and has an output connected to the control input of the oscillator device.

Abstract: The disclosure concerns asynchronous to synchronous synchronizers and particularly a technique which involves level shifting of a metastable voltage either within a synchronizer stage or between synchronizer stages. In a particular implementation of the invention, this level shifting is achieved by altering the relative proportions of at least one complementary pair of devices in a synchronizer or inserting diodes in order to shift the level of a metastable voltage outside the range of a fatal voltage window possessed or exhibited by an adjacent or following part or stage of the synchronizer. By this means, although the occurrence of a metastable condition cannot be avoided, the likelihood of propagation of the metastable condition throughout the synchronizer may be very significantly reduced.

Abstract: Each of the remote high speed circuits of a digital system is provided with a sync pulse generation circuit for generating periodic sync pulses with a predetermined periodicity using a control value. Additionally, each of the remote high speed circuits is further provided with a sampling circuit for sampling the sync pulse generation control value, a comparison circuit for determining whether each of the sampled sync pulse generation control values are consistent, and an adjustment circuit for adjusting the sync pulse generation control value of the particular remote high speed circuit. Furthermore, a sync pulse generation coordinator comprising a clock selection circuit, a delay line, a delayed clock selection circuit, and a coordination pulse generation circuit is provided to the digital system for generating periodic coordination pulses. The periodic coordination pulses are used to control the sampling and comparison.

Abstract: This invention provides an apparatus in which a time difference between an eternal clock signal and an internal clock signal is eliminated, and in which a high operation speed even at a high operation frequency is accomplished without causing erroneous circuit operations. A semiconductor integrated circuit device is equipped with a signal generator for generating an internal clock signal for determining an operation timing of an internal circuit from an external clock signal. The semiconductor integrated circuit device includes a delay unit for bringing an edge of the external clock signal into conformity with the edge of the internal clock signal by delaying the output of the signal generator by the time obtained by subtracting a time corresponding to a circuit delay of the signal generator from a time corresponding to some integral multiple of a 1/2 cycle of the external clock signal.

Abstract: An adaptive data separator for detecting systematic differences between the arrivals of the rising and falling edges of a digital signal and for compensating for the difference. Data packets from a transmission source are prefixed with two data bits of known values. The data separator is also supplied with four clock signals per bit, one corresponding to an ideal rising edge and three following every 5 nanoseconds. The two prefix bits preceding a data packet are then sampled at each of the clock signals. Since all information in a given data packet undergoes the same systematic distortion, the logic of the adaptive data separator can determine the optimum clock signal to use in sampling each bit of data for the packet. Through several multiplexers the incoming data is then clocked to the optimal clock signal for sampling.

Abstract: In an integrated circuit for synthesizing a 50% duty cycle internal clock, the internal clock is synchronized with zero phase difference with respect to an external reference clock having a frequency that is equal to, or is a submultiple of, the synthesized internal clock. The duty cycle of the synthesized waveform is fixed and invariant with respect to the reference clock duty cycle. Synchronization of the two clocks is achieved by a delay-line-loop using a voltage controlled delay line with a nominal half period delay of the synthesized clock. The 50% duty cycle is achieved by a second control loop that has as its input both the reference and the inverted synthesized clock. This second loop drives the voltage controlled delay line with the synthesized internal clock signal. The integrated circuit clock synthesizer is intended to operate as an integral part of a microprocessor or a peripheral unit operating in a system having a common external reference clock.

Abstract: A digital frequency generating device is comprised of a first digital frequency generator which generates a first output signal at a first frequency and a second digital frequency generator which generates a second output signal at a second frequency independent of the first frequency. Both the first and the second frequency generators run continuously and either can be connected to the generating device output by means of a multiplexer. Apparatus is provided to synchronize the two generators so that a continuous phase transition is maintained when the generating device output switches from the first output signal to the second output signal. This arrangement allows the device output to be shifted from a first frequency to a second frequency and then return to the first frequency output while maintaining the phase position of the first frequency output and is particularly useful in nuclear magnetic resonance applications.

Abstract: A radio receiver (100) for receiving a radio frequency signal includes a receiver (110) for generating from the received signal a data signal having alternating first and second edges and a clock (135) for generating a clock signal having a clock period. Adjustment circuitry (400, 145) adjusts the clock period only on the first edges of the data signal when it is determined that adjustments of the clock period on the second edges would contradict adjustments of the clock period on the first edges. Conversely, the adjustment circuitry (400, 145) adjusts the clock period on both the first and the second edges of the data signal when it is determined that the adjustments of the clock period on the second edges would not contradict the adjustments of the clock period on the first edges.

Abstract: A technique for generating gated clock signals for use in enabling various operating gating units in a data processing system in which an internal reference clock signal is used to generate both processor clock signals and the gated clock signals such that the latter signals are substantially synchronous with the processor clock signals. D-flip-flop circuitry together with a delay unit having an adjustable time delay are used to generate a gated clock signal. The overall time delay, from the time of which the circuitry is enabled until the gated clock signal is produced, is appropriately set by selecting the required time delay so that the overall time delay is essentially the same as the time delay required to generate the processor clock signals. Accordingly, the edges of the gated clock signals can be made to coincide with the edges of the processor clock signals.

Abstract: Generation of clock waveforms which have a frequency, phase offset, and duty cycle that is relative to a periodic reference signal. The outputs of a voltage controlled ring oscillator are directly applied to drive the inputs of a programmable AND, fixed OR array (PAL) to produce pulses of varied and phase offset and duty cycle. The phase offset has a resolution of one nanosecond. Additionally, the pulses generated can be ORed together within the PAL to produce clock waveforms that are multiples of the input frequency.

Abstract: A multiple phase clock distribution system for allowing a circuit load to be clocked on predetermined phases of a single clock signal is provided. A single phase clock is the triggering signal for each circuit load in the system, and enable signals are provided to each circuit load to allow the single phase clock to be recognized at only upon an active logic level of the chosen enable signal at a particular circuit load. The enable signals are of duration equal to one period of the single phase clock, and are activated nearly one period of the single phase clock before the triggering edge of the clock to provide as long of an enable signal stabilization period as possible before the single phase clock transitions to its active logic level. Enable signal combination circuitry exists to combine individual enable signals so that varying-frequency enable signals can be produced, and can therefore emulate a multiple phase clock regardless of the number of phases desired.

Abstract: A pulse width modulation circuit apparatus comprises delay gates, delay circuits and an A/D converter. The delay gates are connected in cascade fashion and delay an input clock signal by the same delay time with each delay gate. The delay circuits are furnished interposingly between the delay gates and derive as their common output the delayed clock signal from the delay gates. Because the number of delay gates through which the input clock signal passes is proportional to the delay time acquired, these components constitute a delay circuit arrangement that offers high levels of linearity. With the delay circuit arrangement in use, any one of the delay circuits constituting part of that arrangement is supplied selectively with an operating current as per the digital output from the A/D converter. This provides a delayed clock signal whose delay time matches the level of the input analog signal.

Abstract: Each data sending high speed circuit generating and sending a stream of data slices and a stream of clock pulses is provided with a sync pulse generation circuit for synchronously generating and sending an accompanying stream of periodic sync pulses. The various streams of data slices, clock pulses, and periodic sync pulses incur varying amount of delays as they travel from the data sending high speed circuits to a data acquisition circuit. The data acquisition high speed circuit is provided with a plurality of circular buffer chains of appropriate length for independently buffering the skewed data slices until all corresponding data slices have been received and buffered, and then concurrently reading the buffered corresponding data slices out of the circular buffer chains.

Abstract: A circuit and method for providing phase synchronization between an ECL output signal and a TTL or CMOS output signal has been provided. The circuit includes phase locked loops (20, 24) to make the difference of delays through an ECL-TTL/CMOS translation path with that of a straight ECL path irrelevant. As a result, in order to achieve phase synchronization between an ECL signal and a TTL/CMOS signal, one only needs to match the propagation delay of a delay component (22) to that of a TTL/CMOS-ECL translator (26) as opposed to a delay component and an ECL-TTL/CMOS translator.

Abstract: In a sequential logic design having two domains, each having opposing clock edge for its flip-flops, an inter-domain latch is provided for establishing a controllable and observable boundary point for the two domains. The inter-domain latch comprises three multiplexors and three latches. The first multiplexor, the first latch, the second multiplexor, the second latch, the third latch and the third multiplexor are coupled serially. Additionally, the output of the first latch is by-passed to the third multiplexor. The latches either open when the clock pulse is low or when the clock pulse is high. The first and third latches are driven by the same clock pulses, and the second latch is driven by an inverted clock pulse. Scan vectors for the first and second domains are scanned in through the first and second multiplexors respectively. The outputs of the first and second domains are observed at the second latch and the third multiplexor respectively.

Abstract: A finite state machine connected to a plurality of units which enables to manage the execution of M asynchronous signals to select one of these M asynchronous signals which may become a user clock at a moment which is independent from the pulse of the state machine clock within a minimum of time. The state machine comprises a combinational logic circuit (1) receiving a set of primary input signals (3) which contains N asynchronous input signals and outputting state variable output signals (6) to a state variable register (2). The register (2) is driven by a clock signal (7) which is the clock signal of the state machine and provides M state variable register output signals (51, 52) to M additional latches (10, 20) which delay the signal until they receive a timing pulse (71 or 72) from the combinational circuit.

Abstract: This variable clock dividing circuit is provided with a plurality of dividers coupled in succession. A first of the dividers divides the basic clock by a predetermined dividing ratio and provides an output clock signal to the next divider in succession, while the last divider receives an output clock signal from the next to last divider. The dividing circuit selectively outputs one of the output block signals from the dividers using a switching circuit. A phase synchronization circuit synchronizes the phase of the clock input to the plurality of dividers based on the basic clock. The phase synchronization circuit further comprises a buffer to delay the basic clock before inputting it to the first divider, and a plurality of AND gates. Each of the AND gates corresponds corresponds to the second to last dividers and receives the basic clock and the outputs from all the preceding dividers.

Abstract: An interface between a central processing unit (CPU) and a peripheral device is provided which ensures compatibility between existing software for the peripheral device and a CPU of any speed. The interface waveshapes read or write strobe signals in a transfer cycle between the peripheral device and the CPU in order to ensure timing parameters of the peripheral device are not violated by fast CPUs. If the waveshaping causes a change in the timing between first and second consecutive read or write strobe signals, the interface provides a wait signal to the CPU for the purpose of instructing it to extend the transfer cycle of the second strobe signal. In the illustrated embodiment, an interface according to the invention is part of a video interface connecting a microprocessor unit (MPU) and a video digital-to-analog converter (video DAC). Writing or reading color data to or from the video DAC occurs by way of the interface of the invention.

Abstract: A two- to four-cycle handshake protocol conversion circuit suitable for on-chip implementation uses an exclusive-OR Gate and an AND Gate with one inverted input together with a latching circuit to generate the two-cycle handshake protocol acknowledge signal, A2, as a clocked version of the two-cycle handshake protocol request signal, R2, using the rising edge of the four-cycle handshake protocol acknowledge signal, A4, as the clocking input. The four-cycle handshake protocol request signal R4 is provided as the ANDed output of the complement of A4 combined with the output of the exclusive-OR Gate, the inputs of which are provided by R2 and A2. The latching network may be provided by a simple D flip-flop.

Abstract: A method and apparatus is disclosed for providing salphasic distributions of synchronization signals to physically separated entities typically composing a system. Salphasic behavior is a fundamental property of standing waves in any physical situation governed by the wave equation and where the signal is isophasic, i.e., its phase remains constant, over extended regions and abruptly jumps by 180.degree. between adjacent regions. This behavior is used to minimize the phase shifts due to propagation path lengths. A sinusoidal signal is generated and impressed on a distribution medium which is in turn connected to receivers at the various entities to be synchronized. The medium and loads due to the receivers are composed to cause the synchronizing signal to form nearly pure standing waves in the medium. This enables all the entities to receive the synchronizing signal substantially in the same phase to within an ambiguity of exactly 180.degree.

Abstract: A memory has at least one decoder responsive to a synchronizing pulse for providing a selection signal to the memory cells coincident with the partial selection signal for thereby selecting a group of memory cells for an operation. The decoder has a variable time delay characteristic between the synchronizing pulse and the selection signal. The pulse generator has a mimicking circuit responsive to the synchronizing pulse for providing the partial selection signal to the group of memory cells. The mimicking circuit provides a time delay characteristic between the receipt of the synchronizing pulse and the partial selection signal which mimics the variable delay characteristic of the at least one decoder.

Abstract: A selectable timing delay system which provides for delaying an input signal a specified length of time within a specified tolerance wherein the range and resolution of the selectable timing delay system are so specified that the selected delay within the selected tolerance is obtainable regardless of the relative speed of the integrated circuit chips used in forming the selectable timing delay system.

Abstract: A method and apparatus for generating two phase-coherent first and second signals with arbitrary frequency ratio includes programming a first numerically controlled oscillator (NCO) with a first frequency word to produce a first NCO output. The first NCO output is processed to produce the first signal. The first frequency word is multiplied in a multiplier to produce a second frequency word which is corrected in phase relative to the first frequency word. A second NCO is programmed with the corrected second frequency word to produce a second NCO output. The second NCO output is processed to produce the second signal.

Abstract: For testing of a device under test, an AC measurement voltable application circuit is provided wherein voltages to be applied to the device can be switched during measurement operation without using a separate circuit for a high voltage generation. Data for voltages to be applied to the device are written in respective addresses of a memory in a pattern synchronizing control circuit. This pattern synchronizing control circuit is synchronized with a signal generator and, by inputting mode register setting signal depending on whether the measurement is AC or DC measurement, a relay control circuit for a pin driver circuit is controlled and the application value data in the memory are inputted into a DC measurement unit so as to apply a voltage to the device.

Abstract: A delay matching circuit has a first node (48), a second node (50), a first loading circuit (54, 56), a second loading circuit (58, 60), a third loading circuit (64) and a buffer circuit (62). The first loading circuit couples a first logic state to the first node responsive to a first state of a control signal. The second loading circuit couples a second logic state to the first node responsive to a second state of the control signal. The buffer circuit electrically couples the first and second nodes. The first loading circuit, second loading circuit and buffer circuit are characterized by a first, a second and a third predetermined electrical impedance, respectively. The third loading circuit is coupled to the second node and is characterized by a fourth predetermined electrical impedance. The disclosed delay matching circuit propagates a clock signal input with a delay equal to the Clock-to-Q delay associated with a flip-flop constructed with similar circuit elements.

Abstract: Method and apparatus for synchronizing a clock of a telecommunication switching system. The clock of the telecommunication switching system is supplied, at least at times, with reference clock signals from a plurality of external reference clock sources. Every external reference clock source has a predetermined priority allocated to it. The supplied reference clock signals are checked for clock errors to which individual errors are allocated. For synchronization, the clock accepts an external reference clock signal dependent on the priorities allocated to the reference clock sources and dependent on the clock-error-associated error values. In an initialization, initial error values are allocated to the reference clock sources. In a re-initialization of the system, the synchronization procedure is continued from the current error values that are present at the time of the system outage.

Abstract: A method of synchronizing to a signal includes first performing a rough synchronization and then a fine synchronization to a sync word. The fine synchronization includes comparing a stored portion of the sync word to a received portion. By adjusting the timing and then performing additional correlations, the timing for the best correlation can be obtained. The bit clock is then adjusted so that subsequent data samples can be taken as close to bit center as possible.

Abstract: A remote delay regulator circuit measures the effects of intrinsic propagation delays experienced by a system clock signal propagating through an extended clock distribution path that encompasses a clock repeater chip, a module transmission network and a clock distribution network of an integrated circuit (IC) chip associated with a clock repeater chip. Circuits of the remote delay regulator are contained on the repeater chip and on the associated IC chip. Delay measurement of the remote IC clock distribution network is provided by sensing the clock signal at the beginning of the network using a BEFORE sense tap and at the end of the network using an AFTER sense tap. The BEFORE and AFTER sense taps are routed to a signal generation circuit on the repeater chip where measurement signals are generated that define the beginning and end of a measurement cycle.