Abstract: This invention relates to an automatic detection method and apparatus for tuning the frequency and phase of displaying clock of a display to match the frequency and phase of pixel clock of a PC's display interface card. Based on the synchronized displaying clock, the image shown by digital display will be stable and bright in color. The automatic detection apparatus of invention includes a clock generation unit, a sampling unit, a data processing unit, an accumulation unit, and a decision unit. The clock generation unit creates a plurality of sampling clocks and according to these sampling packet sequences, the sampling unit samples and holds the pixel signals of image frames based on the pixel clock of display interface card, and then stores these data in its registers.

Abstract: A method for generating a synchronous clock signal and a circuit (10) for implementing the method described. To generate the positive-going transition of the clock signal, the method generates a synchronization pulse train using a synchronization signal input. The method generates a second pulse train, having pulses offset in time from and later than those of the synchronization pulse train, to generate the negative-going transition of the clock signal. Because there is little loss in duty cycle, when the synchronous clock signal is input to a power factor correction (“PFC”) and pulse width modulation (“PWM”) controller circuit, the PFC and PWM controller is able to operate normally.

Abstract: In systems embodying the invention a voltage responsive circuit is used to generate a number of different clock signals having the same frequency, with each clock signal being delayed relative to any other clock signal by a certain delay which is a function of the amplitude of a control voltage applied to the voltage responsive circuit. The clock signals are multiplexed to enable any one of the different clock signals to be selected and to then be compared with a reference frequency signal for producing a gradually varying control voltage which is applied to the voltage responsive circuit. The different clock signals are suited for use in applications such as clock recovery and frequency synthesizer systems, where very little jitter is desired.

Abstract: A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.

Abstract: A device for synchronizing a reference event of an analog signal, which includes an analog-to-digital converter receiving an input signal, a register receiving the converter output, a phase-locked loop including an oscillator generating several phase-shifted clock signals of same period, a first clock signal clocking the register, a multiplexer receiving the other clock signals on respective inputs, the output of which clocks said converter, and an analysis circuit connected to control the multiplexer according to successive values of the register output.

Abstract: A method of generating and distributing clock signals is described. The method provides synchronous clock signals in as many phases as a designer of a given circuit finds useful. The method acknowledges timing constraints of the controlled system, and adjusts the clock phases appropriately to meet the needs of the local data circuits using the clock signals. The method uses stages of clock signal generators which are coupled to appropriate portions of the datapath and to each other for controlling the datapath and to provide information about clock signal timing to each other. By adding delay elements, the method can also be used to test the design of the given circuit.

Abstract: A circuit for glitch-free changing of clock having different phases. The circuit comprises a phase detector for receiving a data stream and a system clock, and generating a phase-up signal and a phase-down signal; a flag signal generator for receiving the phase-up signal and the phase-down signal, and then generating M flag signals, wherein the select signal corresponding to the enabled flag signal is enabled; an output stage for receiving the M select signals and the M clocks, and then outputting the system clock.

Abstract: A signature generator circuit is provided for generating a signature word relating to a plurality of words. The signature generator circuit includes a logic gate that receives the plurality of words in series at one input, and a shift register that has a data input, a clock input, and a register output. The clock input receives a clock signal that sets the rate of the plurality of words, the data input is coupled to the output of the logic gate, and the register output is coupled to another input of the logic gate. In a preferred embodiment, the shift register also has a parallel output for outputting the contents of the shift register. Also provided is a method for generating a signature relating to a plurality of words using a logic gate and a shift register. The contents of the shift register are reset. One of the words is supplied in series to the logic gate, at least one of the bits in the shift register is also supplied to the logic gate, and the output of the logic gate is stored in the shift register.

Abstract: In the semiconductor integrated circuit of the present invention, an n-channel MOS transistor and a p-channel MOS transistor, which are a plurality of circuit components that have been designed beforehand, are connected by means of wiring as a portion of a configuration content. Both a power supply potential wiring layer for supplying a power supply potential to circuit components and a ground potential wiring layer for supplying a ground potential to the circuit components are provided between the wiring used to connect together nodes inside the circuit components and the wiring between circuit components so as to generally cover the circuit components.

Abstract: A bit synchronization circuit extracts the central phase of an eye opening irrespective of a jitter distribution of input data to maintain an optimum timing adjustment margin. The bit synchronization circuit has a data edge detector for comparing the phases of an edge of the input data and m-phase clock signals divided from a reference clock. Data edge phase information from the data edge detector is accumulated by a phase accumulation register, which stores the jitter distribution of the input data as accumulated phase information. Based on the accumulated phase information, an eye center phase calculator decodes the negative and positive ends of a jitter range as negative jitter range information and positive jitter range information, and calculates a phase control direction in relation to an extracted phase value which represents a presently selected clock phase.

Abstract: There is provided a transmission circuit which can certainly perform transmission of data of digital form between two circuits operating in synchronization with two clock signals having t he same frequency even if phase shift is generated between the two clock signals. According to a phase difference between a clock signal CK1 and a clock signal CK2, the transmission circuit performs either one of an operation of outputting pre-transmission digital data inputted to the transmission circuit as it is or after it is inverted, and an operation of sampling it in synchronization with the clock signal CK2 and outputting it as it is or after it is inverted.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: A digital phase synthesizer includes a source of successive phase data signals. An interpolator generates successive edge placement data signals in response to each of the successive phase data signals. A phase modulator generates an output clock signal having edges placed at times determined by the successive edge placement data signals. Similarly, a digital phase analyzer includes a source of an serial binary input signal having edges. A phase demodulator generates successive data signals representing the location of each edge of the serial binary input signal. A decimator generates phase data signals at a lower rate than the edges of the serial binary input signal.

Abstract: A semiconductor integrated circuit comprises therein a plurality of logic circuits synchronously designed to operate in synchronization with a clock signal, a first power supply wire for supplying a high-potential side power supply voltage from a first input terminal to each logic circuit, a second power supply wire for supplying the high-potential side power supply voltage from a second input terminal to each logic circuit and a third power supply wire for supplying the high-potential side power supply voltage from a third input terminal to each logic circuit. The logic circuit (DFF circuit) includes two stages of latch circuits and a clock signal inversion circuit. Only the clock signal inversion circuit is connected with the first power supply wire, while the second power supply wire is connected with the remaining latch circuits.

Abstract: A synchronous data sampling circuit and method are provided by which it is possible to sample four data items during one cycle of a clock signal. In the synchronous data sampling circuit a first pulse signal generator receives the clock signal and generates a first pulse signal during a logic “low” interval of the clock signal. A second pulse signal generator receives the clock signal and generates a second pulse signal during a logic “high” interval of the clock signal. A first sampling unit samples first data input through the input port and outputs the sampled first data to the output port in response to the falling edge of the clock signal. A second sampling unit samples second data input through the input port and outputs the sampled second data to the output port in response to a rising or falling edge of the first pulse signal.

Abstract: A shift register comprising a digital filter samples an input signal inputted from an external terminal based on a clock signal and inputs output signals a to d of the shift register constituting the results of the sampling to a gate circuit also comprising the digital filter. The voltage level of the output signal of the gate circuit makes a transition from an L level to an H level when at least three voltage levels of the output signals a to d are H levels. A sense circuit then detects changes in the voltage level of the gate circuit and outputs a signal instructing for the data outputted from the counter to be stored in the register.

Abstract: In a method of synchronizing a local oscillator to a main oscillator signal in a network, the local oscillator signal has a phase shift relative to and upon appearance of the main oscillator signal. The phase shift is used as a reference phase shift between the local oscillator signal and the main oscillator signal to synchronize the local oscillator signal. Initially the reference phase shift is fixed.

Abstract: Circuits for the restoration of a drooped signal are disclosed. In the asynchronous mode circuit, the drooped signal can be restored by detecting the peak of the positive amplitude and the peak of the negative amplitude and take the difference between the two peaks. This difference signal is fed back the equalizer. In the synchronous mode circuit, the drooped signal is sliced and passed to a regeneration circuit. The regeneration circuit uses reference voltage signals and phase information from the slicer to generate a regenerated signal. The regenerated signal is compared with the equalized signal to generate a difference signal, again fed back to the equalizer. The sliced signal is also fed to a clock recovery circuit which recovers the clock signal embedded in the received signal. The two circuits can be combined to provide an optimal circuit for the restoration of a drooped signal.

Abstract: A clock stretching circuit (110) mites between a synchronous bus (112) and a microcontroller (124) which is asleep most of the time to save electrical power. The bus is of a type in which a slow bus device can cause the sender of data to “hold” the data until the slow device is up to speed. The stretching circuit (110) is of small component count and low power consumption, and there is no requirement for a continuous clock. In one embodiment is comprised of a triple analog switch (120, 121, 122) and a very small number of additional components. In another embodiment a dual four-position multiplexer (162, 163) is employed. In still another embodiment, four transistors (210, 212, 213, 215) are used with handful of additional components. A level shifter (220, 221, 222, 223) including an MOSFET and a large-value resistor help to minimize power drain within the bus device.

Abstract: One aspect of the present invention is characterized in that an input buffer circuit constitutes either 2 sets, or a plurality of sets relative to 1 input signal, either a pair of complementary internal clocks, or a plurality of internal clocks are generated by frequency-dividing a supplied clock inside the integrated circuit device, and input signals are received and latched either in synchronization with a pair of complementary clocks, or in synchronization with a plurality of clocks in accordance with an input buffer of either 2 sets or a plurality of sets. The output of input buffers of either 2 sets or a plurality of sets are combined by a combining circuit, and supplied internally. An H level or an L level period is set for the internally-generated internal clock so that outputs from the various input buffers are not in contention with one another.

Abstract: A signal comparison system determines whether a data signal is transitioning close to transitions of its clock signal, thereby causing possible errors in the sampling of the data signal. The signal comparison system includes a plurality of latches that receive a first signal and a second signal and that transmit a respective value of the first signal in response to a transition of the second signal. Delay mechanisms delay the transition of the second signal before the transition is received by latches so that the transition is delayed different amounts relative to each of the latches. A feedback mechanism receives the values transmitted by the latches and determines whether these values are logically equivalent. The feedback mechanism then transmits a feedback signal in response to a determination that one of the values is logically different than another of the values.

Abstract: A semiconductor integrated circuit device is dislosed for self-monitoring presence/absence of a data flow and transmitting the data on the basis of the result of the monitoring. The semiconductor integrated circuit device comprises a plurality of data paths each further comprising at least two logic-circuit blocks. One of the data paths have data-arrival detector for detecting arrival of data and components on the other data paths operate synchronously with those on the data path having the data-arrival detector.

Abstract: A system and method with a self-reset circuit for synchronizing an input data path with a timing control path. The self-resetting circuit includes a normal-mode input detect circuit which detects an arrival of data from the input data path into the self-reset circuit and generates a normal-mode control signal in response thereto. The self-resetting circuit also includes a delay-mode input detect circuit for detecting the arrival of the data from the input data path and which generates a delay-mode control signal in response thereto. A toggle circuit is provided for disabling the normal-mode input detect circuit while simultaneously enabling the delay-mode input detect circuit. In response to the toggle circuit disabling the normal-mode input detect circuit, the delay-mode control signal propagates through a delay gate, such that said delay-mode control signal synchronizes said timing control path with respect to said data input path.

Abstract: An integrated circuit which generates a plurality of local clock signals with substantially no phase difference from an internal clock signal and a stable internal clock generating circuit that generates an internal clock having with reduced sensitivity to variations in a manufacturing process, temperature, supply voltage and noise are provided. The local clock signal generating circuit includes a plurality of phase blenders, each which receives the signals at two points on a clock signal line which transmits the internal clock signals, blends the received signals, and generates a local clock signal having a phase intermediate the phases of the signals at the two points. The internal clock signal generating circuit includes a feedback circuit and a delay lock loop (DLL) circuit.

Abstract: A first latching circuit transferring an input signal from the input terminal to the output terminal for a predetermined period in response to a level transition timing of one direction of a clock signal input to the clock terminal, and maintaining a signal condition of the output terminal in the remaining period, and a second latching circuit transferring an input signal from the input terminal to the output terminal for a predetermined period in response to a level transition timing of the other direction of the clock signal input to the clock terminal, and maintaining a signal condition of the output terminal in the remaining period, are provided. A desired logic circuit is connected between the first and second latching circuits. By synchronously operating the first and second latching circuits by supplying a common clock signal, a clock synchronization circuit not influenced by fluctuation of the device, fluctuation of temperature or power source can be formed.

Abstract: A semiconductor integrated circuit device capable of carrying out reliable reset operation is provided. This semiconductor integrated circuit device comprises a first circuit which is reset on the basis of reset signal SR and serves to generate clock signal fi, a delay circuit adapted to receive the reset signal to output a delayed reset signal SDR, and a second circuit including a flip-flop operative in synchronism with the generated clock signal fi and serving to take thereinto the delayed reset signal SDR in synchronism with the generated clock signal fi.

Abstract: A data/strobe output buffer performs data output according to an outputting internal dock signal DLLCLK from a DLL (Delayed Locked Loop) circuit and an output enable signal. During a time period for a data reading operation including a time period in which the output enable signal is in an active state, a control circuit suspends a phase adjusting operation of the clock signal DLLCLK in the DLL circuit. Thus, occurrence of edge-to-edge jitter in the internal clock signal defining the timing of data output can be suppressed.

Abstract: A 2/N mode dock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

Abstract: Apparatus for clock signals distribution with continuous switching capability between the outputs of a Clock Distribution Unit (CDU) and of a redundant CDU. Switching is transparent to load circuits which utilize these clock signals, by continuously keeping the output clock signals in the CDU and the redundant CDU frequency and phase coherent, by generating each output clock signal from a reference signal, using an adaptive PLL circuitry at each CDU, and pre-adjusting the phase of each output clock signal of the redundant CDU to the corresponding output clock signal of the CDU. In the event of a failure in the CDU, the output is taken from the redundant CDU immediately after failure detection. The phase of the reference frequency output clock signal of the standby CDU module is adjusted to the phase of the active CDU module by adding or subtracting an input signal to the phase error signal, which is generated in a PLL circuitry of the redundant CDU module.

Abstract: A clock gating circuit is provided for a logic device that reduces device resource requirements, eliminates the need for users to define their own clock gating circuit, and eliminates undesirable clock signal disturbances, such as glitches and runt pulses. In one embodiment, the clock gating circuit includes an input terminal for receiving an input clock signal; an input terminal for receiving a clock enable signal; a storage latch coupled to receive the input clock signal and the clock enable signal, and in response, provide a clock gate control signal; and a logic gate coupled to receive the input clock signal and the clock gate control signal. The logic gate selectively routes the input clock signal in response to the clock gate control signal, thereby providing an output clock signal.

Abstract: Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock.

Abstract: A state machine operates in synchronization with a reference clock signal (110) to switch between n numbers of states and maintain any one of these states. Every time a condition for transition to each of the n numbers of states is satisfied, a signal output circuit (100) makes one of n numbers of transition condition satisfying signals (111W, 111Z, 111Y . . . ) active and outputs it. One of a plurality of D-type flip-flops (101-1, 101-2, 101-k . . . ) makes active any one of nu numbers of state signals (W, Z, Y . . . ) indicating the corresponding n numbers of states, and holds the corresponding one state. A synchronization pulse generation circuit (102) generates a one-shot synchronization pulse signal (112) in synchronization with the reference clock signal (110), when a transition condition for transition to one state is satisfied.

Abstract: A test signal retiming circuit that captures an input signal to produce a first output signal and generates a second output signal in response to the first output signal and a predetermined reference signal. The second output signal is resistant to an input signal timing variation. A verification is performed to insure the second output signal conforms to timing of a predetermined output signal. The input signal produces the first output signal by acquiring the input signal in a first buffer in response to a first signal and transferring the acquired input signal from the first buffer to a second buffer in response to the first signal. The first output signal is transferred from the second buffer to a third buffer in response to a second signal to produce a second output signal. The second output signal is resistant to a plurality of clock and data skews.

Abstract: The present invention omits a variable delay circuit (10 in FIG. 1) inside a DLL circuit, and instead, creates a timing synchronization circuit, which generates a second reference clock. The timing synchronization circuit shifts the phase of a first reference clock generated by a frequency divider to the timing of a timing signal generated from the other variable delay circuit so that the second reference clock matches to the timing signal. Then, a phase comparator compares the divided first reference clock to a variable clock that delays the second reference clock, and controls the delay time of the variable delay circuit so that both clocks are in phase. As a result, one variable delay circuit can be omitted, and a DLL circuit that uses a divided clock can be configured.

Abstract: An input circuit for use in a semiconductor integrated circuit decreases a phase lag between a clock signal and an input signal. The input circuit includes a first amplifier that receives an external clock signal at a first input and a reference voltage signal at a second input, and generates an amplified clock signal, and a second amplifier that receives an external input signal at a first input and the reference voltage at a second input, and generates an amplified input signal. A latch circuit is connected to the first and second amplifiers and receives the amplified clock signal at its clock input and the amplified input signal at its data input. The first and second amplifiers receive a high voltage supply signal from a common a high potential power supply and a low voltage supply signal from a common low potential power supply.

Abstract: A frequency-providing circuit is disclosed for providing an output signal at a frequency fout. The circuit comprises a frequency-generating unit, a frequency-changing circuit, and a synchronizing circuit. The frequency-generating unit receives a frequency-selecting control signal and provides a frequency output at a frequency fosc, whereby the frequency-generating unit is switchable between different frequencies substantially without a settling time. The frequency-changing circuit receives the frequency output and a frequency-changing control signal and derives the output signal therefrom, whereby the frequency fout of the output signal can be changed, with respect to the frequency fosc, in accordance with the setting of the frequency-changing control signal. The synchronizing circuit synchronizes the frequency-selecting control signal and the frequency-changing control signal.

Abstract: An integrated circuit includes a master circuit operating at a first frequency for controlling slave circuits operating at a second frequency. The integrated circuit uses registers for eliminating difficulties arising from different and independent frequencies of the master and slave circuits.

Abstract: A method and an apparatus for reading a given digital pulse signal of variable length in the domain of a first clock frequency and creating a pulse output signal that is synchronized in the domain of a second clock. The number of cycles the input pulse signal is active, in terms of the first clock, is the same number of cycles as the resulting output signal is active, where for the output signal the number of cycles is measured by the second clock.

Abstract: A first latch circuit latches output data in response to a leading edge of a clock signal. A second latch circuit latches the output data in response to a trailing edge of the clock signal. When the first latch circuit latches a low level, an n-channel MOS transistor is turned to an on-state in order to supply the transmission path to the low level. When the first latch circuit latches a high level, a p-channel MOS transistor is turned to an on-state during a period during which the second latch circuit latches the low level. The transmission path is supplied to thq high level.

Abstract: A synchronization element for converting an asynchronous pulse signal into a synchronous pulse signal with reference to a clock signal according to the invention. The synchronization element has four flip-flops consisting of a first flip-flop, a second flip-flop, a third flip-flop and a fourth flip-flop, two AND gates, an NAND gate and an inverter. The first flip-flop can capture the rising edges of an input signal. The second and third flip-flops can generate a pulse signal synchronous to the reference clock signal according to whether or not the first flip-flop is latched. The fourth flip-flop is used to reset the other flip-flops. The NAND and One of the two AND gates can generate appropriate control signals to control corresponding signals.

Abstract: A first clock and a second clock are provided. The first and second clocks operate at first and second frequencies, respectively. The phase difference between the first clock and the second clock is accumulated to generate a control signal. In response to the control signal, the phase of the second clock is controlled so as to synchronize with the first clock. Preferably, the phase of the second clock is shifted from the normal timing, when the accumulated value reaches a cycle of the first clock.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: A control block clock distribution network includes a logic circuit, one or more nth-level buffers, and a (n-1)th-level buffer that drives the one or more nth-level buffers. The logic circuit includes a predefined area containing substantially only clocked logic elements. The number of clocked logic elements in the predefined area is constrained to be less than or equal to a predetermined maximum number. The one or more nth-level buffers are located within the predefined area, whereas the (n-1)th-level buffer is located outside of the predefined area. Each nth-level buffer receives the clock signal outputted by the (n-1)th-level buffer and provides a clock signal to a predetermined number of the clocked logic elements within the predefined area Because the predefined area has known dimensions, the length of the clock line from the (n-1)th buffer to the nth-level buffers is known to within a range.

Abstract: A clock synchronization circuit for synchronizing a first communications device and a second communications device to enable digital communication between the devices. The clock synchronization circuit includes an oscillator circuit adapted to generate a base clock signal. A first frequency divider is coupled to the oscillator circuit. The first frequency divider generates a first divider clock signal from the base clock signal. A phase comparison circuit is coupled to receive the first divider clock signal. Additionally, the phase comparison circuit is also coupled to the oscillator circuit to control the frequency of the base clock signal. The phase comparison circuit receives a reference clock signal from a first communications device and adjusts the base clock frequency to correct a phase difference between the first divider clock signal and the reference clock signal. The clock synchronization circuit further includes a second frequency divider coupled to the oscillator circuit.

Abstract: A computer system with a semi-differential bus-signaling scheme is described. The computer system includes a transmitter coupled to a common bus. The transmitter sends clock signals and a data signal to logic-comparing devices within a receiver. The logic-comparing devices compare the data signal to a reference voltage while comparing the clock signals to each other. After the comparison, the clock signals can be used to capture the data into a retiming circuit.

Abstract: A digital communication receiver (10) includes a magnitude-based symbol synchronizer (38) which separates complex phase attributes from magnitude attributes. The phase attributes are processed by a phase processor (78) which identifies clock adjustment opportunities. The magnitude attributes are processed by a magnitude processor (76) that generates a phase error estimate signal (82), which in turn drives a clock generator (24) in a phase locked loop (54) to achieve symbol synchronization in a non-data-directed manner. An additional adjustment feedback loop (114, 128) includes a phase error offset generator (52) and operates in conjunction with the phase locked loop (54) to allow the phase locked loop (54) to achieve lock and a robust operating point in spite of distortion in a received input analog signal (12).

Abstract: An internal clock generator including a switching controller interposed between a digital delay locked loop and an externally generated clock signal. The switching controller reduces current consumptions starting from a next cycle when an external clock and an internal clock are in phase. Further, when the external clock and the internal clock are in phase, driving of the unnecessary elements is suppressed, thereby reducing the current consumption in the internal clock generator.

Abstract: A serial bus speed-up circuit includes a data pattern detecting unit for detecting whether or not the data output from one of the devices to the serial bus consecutively takes the same value, and a clock frequency varying unit for increasing a frequency of the clock output to the serial bus when the data pattern detecting unit detects that the data consecutively takes the same value. By utilizing the fact that the valid delay time and the transition time of the data can be omitted in a case where there is no change in the data value, it is possible to increase the clock frequency and accordingly, increase the data transfer rate.

Abstract: A digital phase locked loop includes a digital phase detector which provides a magnitude control signal to adjust the step size of up and down adjustments in the phase/frequency of a digitally controlled oscillator, resulting in shorter lock-in or acquisition time and smaller jitter as compared to conventional digital phase locked loop devices. In the disclosed embodiments, the digital phase detector includes multiple bit shift registers in both the up and down directions to count or measure a number of up or down minimum width pulses and provide a pulse magnitude control based on the value of the shift registers to the digitally controlled oscillator. The digitally controlled oscillator includes a charge pump and voltage controlled oscillator. In one embodiment, the charge pump provides programmable control over its output current pulses to a capacitor which controls the output frequency of the voltage controlled oscillator.

Abstract: A synchronization system synchronizes a first signal with a second signal. Data values of the first signal are stored in a first-in, first-out (FIFO) device in response to strobe signals that latch the first signal. The output of the FIFO device is clocked by clocks of the second signal. Therefore, the signal output by the FIFO device is synchronized with respect to the second signal. If the frequencies of the first signal and the second signal differ, then multiple FIFO devices are used to successively store the data of the first signal. In this regard, the signal output by the plurality FIFO devices has the same frequency as the second signal and has a bit length larger than the first signal.