Abstract: A serial bus speed-up circuit includes a data pattern detecting unit for detecting whether or not the data output from one of the devices to the serial bus consecutively takes the same value, and a clock frequency varying unit for increasing a frequency of the clock output to the serial bus when the data pattern detecting unit detects that the data consecutively takes the same value. By utilizing the fact that the valid delay time and the transition time of the data can be omitted in a case where there is no change in the data value, it is possible to increase the clock frequency and accordingly, increase the data transfer rate.

Abstract: An apparatus and method for synchronizing a derived bit clock with a transmit bit clock of a transmitted data signal is disclosed. The present invention uses a divide-only direct digital synthesizer and a fixed local oscillator. The synthesizer generates a derived bit clock by dividing the fixed, high frequency local oscillator. A transition detector identifies valid bit transitions in the unsynchronized data signal. At each valid transition, a control algorithm determines whether to adjust the frequency and/or phase of the derived data clock in order to maintain synchronization between the derived bit clock and the transmit bit clock. The unsynchronized data signal and the derived bit clock are processed by a reclock latch to generate a synchronized data signal.

Abstract: A synchronization system synchronizes a first signal with a second signal. Data values of the first signal are stored in a first-in, first-out (FIFO) device in response to strobe signals that latch the first signal. The output of the FIFO device is clocked by clocks of the second signal. Therefore, the signal output by the FIFO device is synchronized with respect to the second signal. If the frequencies of the first signal and the second signal differ, then multiple FIFO devices are used to successively store the data of the first signal. In this regard, the signal output by the plurality FIFO devices has the same frequency as the second signal and has a bit length larger than the first signal.

Abstract: A multiphase clock generating circuit having: a clock generating section for generating N-phase clock signals of number N which have a frequency nearly equal to that of input clock signal and whose phases are sequentially shifted by 360 degrees/N; an input side M-division circuit that divides the frequency of the input clock signal by M, outputting a reset signal to the clock generating section; an output side M-division circuit that is fed with a delayed reset signal that the reset signal output from the clock generating section is accompanied with a predetermined delay, and, synchronized with the delayed reset signal, divides the frequency of output clock signal output from the clock generating section by M; and a controller for comparing the input side M-division clock and the output side M-division clock, and controlling a delay amount of the clock generating section based on the comparison result.

Abstract: Disclosed is an apparatus and a method for generating decoding clock signals in response to a period of write and read clock signals for decoding transmission data, which is suppressed in a form of punctured code at a code rate. The apparatus according to the present invention comprises a) a clock generator receiving a control signal and a code rate from a transmission part, for rearranging a suppressed data; b) a controller receiving a write clock signal from an external circuit and a read clock signal from the clock generator, for controlling a period of a read clock signal wherein the period of the read clock signal is correspondent to the number of data stored in the memory; c) a decoding clock generator receiving a system clock signal from an external circuit and the control clock signal from the controller, for outputting a decoding clock signal.

Abstract: Delay-locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a set of delay-producing elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry.

Abstract: A semiconductor integrated circuit includes: a phase difference reduction circuit for reducing a first phase difference between a clock signal and a data signal; and a circuit for receiving the data signal with a reduced first phase difference between the clock signal and the data signal.

Abstract: The present invention includes a circuit assembly and method of synchronizing plural circuits. According to one aspect of the present invention, a circuit includes: an oscillator configured to generate a reference clock signal; a first circuit including: a first divider configured to generate a first internal clock signal responsive to the reference clock signal; and reset generation circuitry configured to receive an external reset signal and generate a reset second circuit signal synchronized with a predefined position of the first divider, with the reference clock signal and with the external reset signal; and a second circuit including: reset detection circuitry configured to generate a reset detection signal synchronized with the reset second circuit signal and the reference clock signal; and a second divider configured to set to a predefined position responsive to the reception of the reset detection signal and generate a second internal clock signal synchronized with the first internal clock signal.

Abstract: In the case of sending the sampled clock of transmission coded data together with the coded data and regenerating a clock synchronized with this sampled clock on the receiver side, the drawing-in is speeded up on the received side for the clock information items SCRn sent at unequal intervals. In the case of generating a control voltage of the VCXO in accordance with the received SCRn and the SCCn by the counter, the CPU calculates the amount of frequency fluctuation per unit time and generates a control voltage in accordance with this amount of fluctuation. Thereby, even if SCRn are received at unequal intervals, a rapid follow-up control of the PLL loop including the VCXO becomes possible.

Abstract: A scanner circuit for digital signals with high data rate includes an arrangement for timing pulse recovery formed by a scanner stage for scanning a digital signal and an edge discriminator that evaluates at least one edge of the scanned digital signal and that controls a digital oscillator that generates a data timing signal.

Abstract: The invention relates to a wave form shaping circuit, etc. which outputs signals after shaping the input signal to a duty 50% wave form regardless of whether or not input signals are of duty 50%, wherein a duty determination circuit is provided, which determines and instructs the timing position of duty 50% of clock signals to be outputted, upon receiving a timing signal prepared by a timing generation circuit 2.

Abstract: A transaction control circuit includes an initiate control circuit and a busy control circuit which are coupled between an initiate input, an initiate output, a busy input and busy output. The initiate control circuit sets the initiate output to an active state when the initiate input transitions from an inactive state to an active state and holds the initiate output in the active state until the initiate control circuit senses a transition in the busy input from an inactive state to an active state. The busy control circuit sets the busy output to an active state when either the initiate output is in the active state or the busy input is in the active state.

Abstract: A false-synchronization detection device comprises an up-down counter which counts down a predetermined amount of clocks when codes of phase changes at former and latter halves of a symbol interval are different, and counts up a different predetermined amount of clocks, which is less than the previous one, when codes of phase changes at former and latter halves of the symbol interval are the same. Thus, the false-synchronization detection device is capable of recognizing false-synchronization of symbol timing when the count value falls as far as the predetermined value.

Abstract: The inventive mechanism is included with each module in a chain of modules. The inventive mechanism includes a clock mechanism which is edge synchronous among all of the clock mechanisms in the other modules, meaning that each clock has the same frequency and zero phase delay with respect to the clocks of the other modules. The clock mechanism of the first module of the chain is the master, the subsequent clocks are slaves. The inventive mechanism includes a trigger mechanism which allows each module of the chain to initiate a trigger event. The trigger mechanism is tied to the clock mechanism, so that the trigger signal is sent out on the next rising edge of the clock. Since each module is tied to the same clock frequency and has zero delay, when one module sends out a trigger, the remaining modules will detect the trigger on the next clock cycle, and the trigger event will begin simultaneously in all modules.

Abstract: A circuit and method for performing a delay locked function for correcting phase differences between an input clock signal RCLK and an internally generated clock signal ICLK and for controlling the correcting step to maintain an accurate locking operation when a phase difference is below a threshold valve (the maximum time for which the internal step jitter may occur).

Abstract: A semiconductor integrated circuit includes a first shift register composed of a plurality of first flipflops each including a first selector for selecting a first or second clock, a second selector for selecting an inverted signal of the first clock or a third clock, a third selector for selecting a first data signal or a first scanning signal, a first latch circuit for latching an output of the third selector, and a second latch circuit for latching an output of the first latch circuit. The semiconductor integrated circuit further includes a second shift register composed of a plurality of second flipflops each including a fourth selector for selecting a second data signal or a second scanning signal, a third latch circuit for latching an output of the fourth selector, and a fourth latch circuit for latching an output signal of the third latch circuit.

Abstract: The present invention has been made in view of the above mentioned problem, and the present invention provides a sticky signal generator for rapidly generating a sticky signal with a small layout area which uses a shift register of which the size is equal to the size of the inputted operand data.

Abstract: A symbol timing recovery circuit in a digital demodulator is disclosed. The symbol timing recovery circuit comprises means for generating a clock signal in a predetermined period, means for sampling a received signal according to the clock signal, an interpolator for interpolating the output signal from the sampling means according to a filter tap coefficients calculated by a fractional interval at each sampling period to obtain an interpolant, a data filter for filtering the interpolant and providing the filtered interpolants as a strobe data, a timing error detector for detecting a timing error from the strobe data to generate a timing error signal, a loop filter for filtering the timing error signal to obtain and provide a mean timing error signal; and a controller for providing the fractional interval and controlling the signal processing operation of the data filter, timing error detector, and loop filter according to the mean timing error signal.

Abstract: An interface circuit with high speed data transmission is disclosed. The interface circuit comprises a clock signal generator outputting a clock signal and an inversion clock signal, a shift signal generator receiving a start signal, the clock signal and the inversion clock signal. The shift signal generator outputs shift signals having odd shift signals and even shift signals. A first signal of the odd shift signals is generated in response to the start signal and the clock signal. The even shift signal is generated in response to a previous odd signal and the inversion clock signal. The odd shift signal is generated in response to a previous even signal and the clock signal. The interface circuit further comprises a data distribution circuit and odd and even output circuits. The data distribution circuit receives data, the clock signal and the inversion clock signal and outputs odd data in response to the data and the clock signal and even data in response to the data and the inversion clock signal.

Abstract: A method an apparatus for performing a reset operation in an integrated circuit where a memory programming voltage is recovered allowing use of the memory during reset. The voltage recovery unit includes a high voltage conversion portion active for a first recovery period, and a low voltage conversion portion active for a subsequent second recovery period, the low voltage conversion portion is inactive for the first recovery period. The first and second recovery portions are responsive to assertion of a reset signal and an intermediate reset signal generated before the end of the reset period. Recovery of the programming voltage allows uncorrupted retrieval and use of a configuration word during reset. The high voltage conversion portion includes p-channel devices with robust breakdown resistance, and the low voltage conversion portion includes n-channel devices which provides improved speed of operation.

Abstract: A semiconductor integrated circuit and a method for reducing the consumed power are provided. A comparator outputs bits having the same level, which correspond to each other, of a last input stored in a register and a current input that acts as an input signal. A zero counter counts the number of the bits having the same level output from the comparator. If the number of the bits having the same level is smaller than a predetermined number, the current input is not similar to the last input. Consequently, an instruction is given to a flip-flop to invert the current input. The inverted current input becomes similar to the last input. Thus, the consumed power of a logic can be reduced.

Abstract: The ON and OFF states of a second device are controlled by a first device through a three-conductor bus. The bus carries data, clock, and enable signals and the second device is in the OFF state when all the signals of the three-conductor bus have an L level. The second device is in the ON state when at least one of the signals has an H level (higher potential than the L level). The enable signal is set to the H level during the data transmission. Otherwise, it carries an L level, while the data or clock signal has an H level. The system obviates an additional housing pin. The operating state information is transmitted relatively rapidly.

Abstract: An adjustable phase clock includes a number (n) of delay circuits having respective controllable delays and being connected in cascade for generating n respective delayed signals. A first delay circuit receives the input clock signal and an nth delay circuit generates a total delay signal. A phase detector and filter are connected to the n delay circuits for controlling the respective delays thereof so that the total delay signal locks in relation to the input clock, such as to its period. In addition, the adjustable phase clock preferably further permits control of the output based upon selecting one of the n delayed signals having a corresponding adjusted phase delay relative to the input clock signal. Of course, multiple ones of the n delayed signals can also be selected. The adjustable phase clock may be used in a line locking application and an adjustable frequency clock circuit.

Abstract: An apparatus for adjusting phase relation of a plurality of clock signals in a processor. The apparatus contains a phase detection circuit that receives a plurality of clock signals and generates a first output based on a phase relation between those clock signals. A controller then adjusts the delay of the clock signals based on the first output of the phase detection circuit and a bit of a delay shift register to synchronize the clock signals within a predefined range. The controller generates a second output if the phase relation between the plurality of clock signals has changed before the adjusting of the delay of the clock signals has occurred. A noise band circuit is configured to receive the second output of the controller and adjust the predefined range in response to the receiving of the second output.

Abstract: A search unit of a receiver synchronizer includes a search PN signal generator for generating PN signals for all PN phases in order to search the maximum power path; a search correlation unit which outputs a correlation value from sampling data and the PN signal; a data buffer for storing the correlation value; a path search unit for controlling a search the path using the correlation value received from the data buffer; a PN signal generator for outputting a PN signal to a DLL and a data demodulation correlation device; and a DLL switch for switching the PN phase to the phase of the maximum power path by controlling the PN signal generator as a result of the search for the path. The PN phase of the PN signal output to the DLL is constantly maintained in synchronization with the phase of the maximum power path.

Abstract: A voltage controlled delay circuit having the same structure, except for a loop, as a voltage controlled oscillator included in a PLL circuit which in turn generates an internal clock signal from an external clock signal is controlled by a control voltage from the PLL circuit, and the delay output of the voltage controlled delay circuit is selected by a selection circuit in accordance with the output signal of a vernier-adjusting counter in order to generate a read clock signal. Therefore, a vernier for optimizing data input timing in a controller can be realized which always has a constant delay amount regardless of a change in operating environment.

Abstract: A semiconductor device for inputting/outputting data in synchronism with a reference clock signal and an internal clock signal in each circuit. In this device, a variably delay section delays a generated clock signal to output an internal clock signal, and a phase error-detecting section detects a time difference between the internal clock signal and the reference clock signal, thereby controlling the delay amount of the variable delay section to make the time difference substantially zero.

Abstract: Digital information including a sync data field and a user data field subsequent thereto is read from a storage media as a digital information signal in an analog signal format. The obtained signal is sampled according to a clock signal and is thereby transformed into a digital information signal in a digital format. In the sync data field, the clock signal is synchronized with the digital information signal by an analog PLL circuit. Thereafter, in the user data field, the clock signal is synchronized with the digital information signal by a digital PLL circuit.

Abstract: A simply structured clock pulse generator operating stably in a wide range of frequencies in response to a timing signal fed from outside a semiconductor integrated circuit. A first frequency signal fed from the external terminal of the semiconductor integrated circuit and a second frequency signal generated within the semiconductor integrated circuit are input to a phase comparator. The output signal of the phase comparator is smoothed by a low-pass filter for conversion to a voltage signal. A compensation circuit uses both a delay signal from a current-controlled delay circuit receiving the first frequency signal and the first frequency signal to generate a current signal corresponding to the frequency of the latter signal. The voltage signal generated by the low-pass filter is converted into a current signal.

Abstract: A programmable device includes means for generating an asynchronous logic derived clock signal from one or more of a plurality input signals. Means for synchronizing the asynchronous logic derived clock signal to a reference clock signal are coupled to the means for generating the asynchronous logic derived clock signal. The means for synchronizing generate a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal.

Abstract: A programmable device includes a circuit for generating an asynchronous logic derived clock signal derived from one or more of a number of input signals. Circuits for synchronizing the asynchronous logic derived clock signal to a reference clock signal are coupled to the circuit for generating the asynchronous logic derived clock signal. The circuits for synchronizing generate a synchronized logic derived clock signal from the asynchronous clock signal and a reference clock signal. The programmable device further includes a circuit for suspending a clock signal. In one embodiment, a logic derived clock signal is generated and synchronized with a synchronous clock signal. In synchronizing the logic derived clock signal an intermediate signal is generated during a first clock cycle of the synchronous clock signal and is combined with the synchronized logic derived clock signal during a second clock cycle of the synchronous clock signal to produce a suspendable clock signal.

Abstract: Briefly, in accordance with one embodiment, an integrated circuit includes: electronic circuitry for transferring digital data signals along a digital data signal path between different clock timing domains. The clock timing domains have a common higher frequency source clock. A first clock timing domain clock signal has a relatively fixed phase and a second clock timing domain clock signal has a relatively varying phase. The electronic circuitry includes delay elements in clock signal paths associated with the digital data signal path so that along the digital data signal path, clock signals in different clock timing domains are respectively staggered for a relatively short time compared with a given cycle of the source clock. The electronic circuitry further includes a digital data signal path including a data value retention element to delay the transfer of digital data signals between different clock timing domains at selected times.

Abstract: A semiconductor integrated circuit has a de-skew circuit for reducing a skew of an incoming signal from a specific circuit with respect to a synchronous clock signal. The de-skew circuit controls the phase of an outgoing signal to be transmitted from the semiconductor integrated circuit to the specific circuit in response to the skew of the input signal. This arrangement decreases not only a skew of incoming signals from the specific circuit but also a skew of outgoing signals to the specific circuit.

Abstract: A programmable device includes circuitry for generating an asynchronous logic derived clock signal from one or more of a number of input signals. Circuits for synchronizing the asynchronous logic derived clock signal to be a reference clock signal are coupled to the circuitry for generating. The circuits for synchronizing generate a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal but only when the input signals are recognized as clocking signals. That is, the synchronizing circuits discriminate between valid input signals and spurious signals or noise.

Abstract: A clock timing recovery circuit for recovering the clock timing from a baseband signal obtained by detection of a received signal. The clock timing is rapidly established using a clock signal which has been phase-shifted from the desired clock timing to sample the baseband signal, and by obtaining the optimum phase from the sampled signal obtained as a result. A clock-timing recovery circuit according to this invention does not require oversampling and provides easy optimization of circuit constants.

Abstract: A programmable device includes circuitry for generating an asynchronous logic derived clock signal from one or more of a plurality of input signals. Further circuitry for synchronizing the asynchronous logic derived clock signal to a reference clock signal is coupled to the generating circuitry. The synchronizing circuit generates a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal. The synchronized logic derived clock signal is produced only when the input signals from which the asynchronous logic derived clock signal is created are recognized as proper input signals and the synchronized logic derived clock signal has a fixed duration logic HIGH interval for variable duration logic HIGH intervals of the input signals. Spurious input signals or noise are rejected.

Abstract: A spread spectrum receiving apparatus is constructed by a generator for generating a reference clock, a phase shift circuit for shifting the phase of the reference clock generated by the generator in accordance with a code timing in a reception signal and the reference clock, and a de-spreading circuit for de-spreading the reception signal in accordance with the reference clock whose phase is shifted by the phase shift circuit. The de-spreading circuit generates a code for de-spreading in accordance with the phase shifted reference clock. The phase shift circuit has a calculator for calculating a phase shift amount so as to synchronize the code timing in the reception signal with the code for reception in accordance with a deviation between the code timing in the reception signal and the reference clock.

Abstract: The present invention involves an electrical component interface system. The system includes clocking circuitry to provide a clock signal. A sending component provide a non-periodic strobe signal and a data signal responsive to the clocking signal. A receiving component receives the strobe signal and data signal. The receiving component includes delay circuitry to delay the strobe signal so as to position edges of the strobe signal with respect to data cells of the data signal. The delay circuitry includes a loaded delay elements and DC level restoration circuitry to control the load of the loaded delay element. The delay elements may be a series of inverters loaded with RC loads. The DC level restoration circuitry may be pulse generation circuitry.

Abstract: In an automatic frequency control circuit, a circuit constitution thereof is simplified without decreasing performance of demodulation. In the control circuit, a frequency counter counts a number of regenerative intermediate frequency from an intermediate frequency or a wave detection circuit, then a magnitude comparator compares an output of the frequency counter with a prescribed comparison data, before a subtraction circuit subtracts the output of the frequency counter from the prescribed comparison data. An operation part implements required operation according to an output of the magnitude comparator and an output of the subtraction circuit. A D/A converter converts an output data of the operation part into an analog signal. A TCXO oscillates an oscillation frequency according to the analog signal of the D/A converter. A variable frequency demultiplier is connected to a stage in front of the frequency counter.

Abstract: A D flip-flop latches a reference clock signal in response to an output signal fed back from an output circuit. A pulse generating circuit generates a pulse in response to the output signal fedback from the output circuit. From the latched signal and the pulse generated by the pulse generating circuit, a count pulse is generated. The count pulse is output to an up/down counter. Based on the counting result of the up/down counter, a digital-to-analog conversion circuit generates a delay control signal. Using this delay control signal, the delay circuit synchronizes its output signal with the reference clock signal. It is possible to synchronize the output data signal with the reference clock signal regardless of variations in the reference clock signal, source voltage, and ambient temperature.

Abstract: An active/stand-by determination method for use in a duplicated system, wherein two elements, one given a priority and the other not given a priority, in the duplicated system operate in an active mode and a stand-by mode alternatively by using an X.sub.-- ACTIVE signal, a S.sub.-- ACTIVE signal, a STATUS signal for each element and a SIDE signal, the method comprising the steps of: a) setting both the elements in the stand-by mode upon power-on; b) checking the X.sub.-- ACTIVE signal and the STATUS signal at both the elements; c) entering into the active mode if it is determined at the step b) that both the X.sub.-- ACTIVE signal and the STATUS signal are "high"; d) remaining in the stand-by mode if it is determined at the step b) that at least one of the X.sub.

Abstract: The present invention relates to a device for detecting the locking of an automatic gain control circuit, the automatic gain control circuit receiving a signal to be regulated, a check signal and a sampling control signal for driving the operation of the circuit. The detection device includes a comparator receiving the check signal and the signal to be regulated or a signal representative of the signal to be regulated. The comparator generates two logic signals, the states of which form a specific combination of logic states when the value of the signal to be regulated is in a range of values including the value of the check signal. A logic comparator circuit generates a logic comparison signal, the state of which is representative of the presence or absence of this specific combination, and a storage means, driven by the sampling control signal, stores the state of the signal provided by the logic circuit.

Abstract: A device for deriving a clock signal having a specific frequency, from an electrical signal, for example, a video signal, the device including an input terminal (1) for receiving the synchronizing signal; a phase comparator (5) having a first input coupled to the input terminal, a second input and an output; a voltage controlled oscillator (15) having an input coupled to the output of the phase comparator, and an output; a counter (23) having a first input coupled to the output of the voltage controlled oscillator, a second input for receiving a preset control signal, and an output coupled to the second input of the phase comparator; a preset control signal generator (30) having an input coupled to the input terminal, and an output coupled to the second input of the counter, the counter being adapted to set its count value to a preset value in response to the preset control signal applied to its preset control signal input.

Abstract: A semiconductor integrated circuit device is provided which includes at least one first functional circuit block which receives an input signal and executes a logical operation to output an output signal as a result. At least one second functional circuit block is connected in parallel with the first functional circuit block. The second functional circuit block also responds to an input signal to execute a logical operation and output an output signal as a result. The first and second functional circuit blocks are connected to one another such that the second functional circuit block will operate synchronously with the first functional circuit block. More specifically, the first functional circuit block is arranged to control an output timing of the second functional circuit block.

Abstract: The clock synthesizer includes an oscillator section for providing a train of pulses corresponding to the transitions of a master clock signal, a first register coupled to the oscillator for dividing the train of pulses by a fixed integer to produce a plurality of first phase shifted signals corresponding in number to said integer, and a plurality of second shift registers corresponding in number to the integer and each having a clocking input coupled to a respective one of the first phase shifted signals. The second registers produce a plurality of second phase shifted signals having leading edge transitions separated from each other by displacements corresponding to the transitions of the master clock signal. The second phase shifted signals are then combined to generate the lower frequency clock pulses, which may be used, e.g., in the clocking of a charge coupled device image sensor.

Abstract: An internal voltage generator for a semiconductor device. Whereas a feedback signal is given to maintain a voltage of a predetermined level by a voltage detector in the conventional art, the internal voltage generator adopts a method of adjusting the period. Therefore, the variance of a signal generated due to a time delay can be reduced. The internal voltage generator includes an oscillator for generating pulses of a predetermined period when a power-up signal is activated, a timing generator for generating appropriate timing according to the output of the oscillator for determining the basic operational period of a voltage pump and a series of signals, a pump driver for controlling a voltage pump to operate with a predetermined phase by controlling a pulse signal from the oscillator by the pulse signal of a predetermined period generated from the timing generator, and a voltage pump for pumping voltage to a third voltage and outputting the same.

Abstract: A timing error detecting circuit detects a timing error of a measurement objective circuit by reading an input data in synchronism with rising or falling of a timing signal and outputting a first output data as a result of the process. The timing error detecting circuit includes a specification insertion circuit for providing an allowable specification value of a delay period relative to the timing signal, a signal processing detecting portion reading the first output data of the measurement objective circuit in synchronism with rising or falling of output of the specification insertion circuit and performing similar process to the measurement objective circuit for outputting a second output data, and a judgement circuit inputting the first and second output data of the measurement objective circuit and the signal processing detecting portion and making judgement of the timing error of the measurement objective circuit in synchronism with rising or falling of the specification insertion circuit.

Abstract: A PCI interface includes a PCI core that operates at the PCI bus frequency and glue logic which provides an interface to a higher frequency clock domain. The glue logic includes FIFO buffers for addresses and data coming from or going to the PCI bus, and synchronizers for control signals coming from or going to the PCI core. In one embodiment, a novel synchronizer includes three flip-flops at least two of which are JK flip-flops.

Abstract: A design method for an asynchronous sequential circuit that employs synchronous design techniques wherein a synchronous sequential circuit is designed to perform a desired function. A terminating state for the synchronous sequential circuit is then defined wherein the terminating state occurs before a transition to an idle state in the synchronous sequential circuit. A circuit is provided for latching at least one asynchronous input for the asynchronous sequential circuit and a circuit is provided for generating a synchronous clock that drives the synchronous sequential circuit such that the synchronous clock is enabled by a latched asynchronous input and is disabled by the terminating state of the synchronous sequential circuit.

Abstract: .[.A bit clock reproducing circuit produces an output bit clock signal in response to an input clock signal but without reproducing jitter present in the input signal. A counter is supplied with a reference clock signal as a counting input, and the counter is periodically loaded, at a fixed time during each cycle of the input clock signal, with data which is a predetermined function of the state of the counter at such times..]. .Iadd.A bit clock reproducing circuit incorporates a counter for counting pulses of a clock pulse source after the arrival of an edge of a data pulse, at which time the counter is loaded with one of a number of preset values stored in a read-only memory, the contents of which are addressed by the counter output. Input data pulses are gated to an output terminal when the counter arrives at a predetermined state.