Abstract: A multi-phase clock generation circuit includes a first clock buffer unit configured to invert and buffer a first internal clock and a second internal clock in response to an external clock, and to generate a third internal clock and a fourth internal clock, and a second clock buffer unit configured to invert and buffer the third internal clock and the fourth internal clock in response to the external clock, and to generate the first internal clock and the second internal clock.

Abstract: A circuit device includes a clock generator outputting a clock signal having a first frequency; plural phase controllers inputting the clock signal having the first frequency, and outputting clock signals having the first frequency and having phases advanced or delayed with respect to a phase of the clock signal; a selector inputting the plural clock signals having the first frequency output from the plural phase controllers, sequentially selecting pulses of the plural clock signals, and outputting a clock signal having a second frequency; a pattern generator generating a test pattern based on the clock signal having the second frequency; and a circuit inputting the clock signal having the second frequency and the test pattern generated by the pattern generator, operate based on the clock signal having the second frequency, and outputting operation results.

Abstract: An apparatus includes a drive signal circuit for MEMS sensor. The drive signal circuit includes an input configured to receive a voltage signal representative of charge generated by the MEMS sensor, a phase-shift circuit electrically coupled to the input and configured to phase shift an input signal by substantially ninety degrees, and a comparator circuit with hysteresis. An input of the comparator is electrically coupled to an output of the phase-shift circuit and an output of the comparator circuit is electrically coupled to an output of the drive signal circuit. A feedback loop extends from the output of the drive signal circuit to the input of the phase-shift circuit and is configured to generate a self-oscillating signal at an output of the drive signal circuit. An output signal generated by the drive signal circuit is applied to a drive input of the MEMS sensor.

Abstract: One object is to provide a front-end module with a shared output terminal wherein an input impedance is readily matched and an insertion loss is suppressed. In accordance with one aspect, the front-end module 10 includes an input terminal, output terminals, a first filter circuit that passes signals in a first passband, a second filter circuit that passes signals in a second passband, a switch that is disposed between the input terminal and the first and second filter circuits and selectively connects the input terminal to the first and second filter circuits, and a matching circuit. The second filter circuit includes phase shifters.

Abstract: The present invention discloses a phase interpolating apparatus comprising: a first signal generation circuit, configured for generating a first signal having a first phase; an optional second signal generation circuit, configured for generating a second signal having the first phase; a third signal generation circuit, configured for generating a third signal having a second phase; a fourth/fifth signal generation circuit, configured for generating a fourth signal having a third phase when operating in a first mode and for generating a fifth signal having the second phase instead of the fourth signal when operating in a second mode; and a phase interpolator, configured for generating an interpolated signal without utilizing the fourth signal when operating in the first mode and for generating the interpolated signal according to the first signal, the third signal, and the fifth signal when operating in the second mode.

Abstract: A current-driven load such as LEDs or laser diodes is driven by a current driver having a two stages (or phases), the outputs of which have ripple which is forced to be out-of-phase with one another. In analog embodiments, an output (ripple or switching) of a master stage hysteresis controller is phase-shifted and scaled, and modulates the input of a slave stage hysteresis controller so that the slave stage pulls into a ripple-canceling phase. In digital embodiments, a faster of the two phases is designated “master”, maximum and minimum thresholds are set, and the slave phase's on time is based on a previous cycle's slave phase ON time, the master stage OFF time and an offset. The slave controller may “lock” to the anti-phase of the master stage (or phase). The ripple currents at the summed output of the master and slave stages substantially cancel.

Abstract: A clock generating apparatus includes an oscillator and a frequency synthesizer. The oscillator is utilized for generating a reference clock signal. The frequency synthesizer is coupled to the oscillator and utilized for synthesizing a target clock signal in accordance with the reference clock signal and a frequency division factor that has been adjusted or compensated, and outputting the target clock signal as an output of the clock generating apparatus.

Abstract: Active directional couplers are provided. In accordance with certain embodiments of the invention, the subject active directional couplers are tunable. The tuning is accomplished via varactors connected to the lines of the active directional couplers. Active directional elements are provided between different lines of the subject active directional couplers to control a signal path between ports of the different lines. The active directional elements are selected from diodes, transistors, inverting amplifiers, non-inverting amplifiers, differential amplifiers, and active baluns. The lines include a phase shift element between the two ports of each line. The phase shift element is selected from a transmission line, a delay line, and a phase shifter. Advantageously, the subject lines do not have to be designed for ideal phase shifting and can be designed at near 90° or near ?/4 values.

Abstract: A digital-to-analog conversion apparatus and a current-mode interpolation buffer thereof are provided. The current-mode interpolation buffer comprises a current source, a first differential transistor pair, a second differential transistor pair and an output stage. The current source outputs a first current and draws a second current. Wherein, the amperages of the first current and the second current are dependent on a digital code. First differential transistor pair generates a first differential current according a first rough voltage, an analog voltage and the first current. Second differential transistor pair generates a second differential current according a second rough voltage, the analog voltage and the second current. Output stage generates the analog voltage according to the first differential current and the second differential current, where the analog voltage belongs to a rough range from the first rough voltage to the second rough voltage.

Abstract: Phase mixers, clock signal generators, memories and methods for providing an output signal having a phase relative to the phase difference of input clock signals are disclosed. One such phase mixer includes a phase mixer circuit having inputs and an output. The phase mixer is configured to receive a plurality of input clock signals and generate an output clock signal at the output having a phase relative to the plurality of input clock signals. The phase mixer further includes an adjustment circuit coupled to the phase mixer circuit. In some phase mixers, a control circuit coupled to the phase mixer circuit and the adjustment circuit is included. The control circuit is configured to generate a control signal based on the input signals to adjust an electrical load-to-drive ratio of the phase mixer.

Abstract: A phase rotator based on voltage referencing is disclosed. A voltage signal is generated that is proportional to the phase difference between two input signals. The voltage signal is then used as the upper voltage limit for a digital-to-analog converter (DAC). The DAC is programmable via an input vector to generate a DAC output. The DAC output is used to generate a phase rotated (phase shifted) output, which is at an intermediate phase between the two input signals.

Abstract: In one embodiment, a phase interpolator with a phase range of n degrees, where 0<n?360, and having m reference signals, where m?2, and a control signal as input, and producing an output signal with a phase within the phase range using one or more of the m reference signals based on a control code provided by the control signal. The phase interpolator comprises one or more circuits configured to: divide the phase range of n degrees into k sections, wherein k>m; and for each of the k sections, select a relative gain of one or more weights assigned to the one or more reference signals, respectively, with respect to the control code provided by the control signal.

Abstract: A phase interpolator, multi-phase interpolation device, interpolated clock generating method and multi-phase clock generating method is related to a phase interpolator with a differential to single-ended converter, a load circuit, two differential pairs, a current source and at least a switch pair. By using the switch pair to control the current providing for the two differential pairs from the current source, and through regulating the load of the load circuit and/or the reference current of the current source, the intersection of a first signal and a second signal is in the overlap duration between a first input clock and a second input clock, so that uniform multi-phase output clock signal can be interpolated.

Abstract: Provided is a semiconductor device which inputs an input clock signal of predetermined frequency and outputs a plurality of clock signals of the same frequency, the semiconductor device including: an input unit configured to input the input clock signal of the predetermined frequency; and a delay unit configured to generate a plurality of clock signals of the same frequency by providing predetermined delay time period to the input clock signal to be delayed in order to reduce load applied to a power supply in common with the plurality of the clock signals. According to the semiconductor device, output waveform distortion of the clock signals can be improved even with simple structure.

Abstract: A splitter circuit in a semiconductor device includes a first inverter that receives an input signal and outputs an inverted signal, a second inverter that receives the inverted signal and outputs a non-inverted signal (a first output signal), a third inverter that receives the input signal and outputs an inverted signal (a second output signal) and an auxiliary inverter that shares an output signal line with the third inverter. The third inverter and the auxiliary inverter use an inverted signal of the input signal as power supplies.

Abstract: One embodiment provides a system for generating a reference waveform. The system can include a first pulse-width modulation (PWM) channel configured to provide a first PWM waveform having a first duty cycle and a first frequency. A second PWM channel is configured to provide a second PWM waveform having a second duty cycle and the first frequency. Combinational logic is configured to combine the first PWM waveform and the second PWM waveform to generate a phase-shifted reference PWM waveform having the first frequency and a phase shift that is based on the first duty cycle and the second duty cycle.

Abstract: There is provided a frequency synthesizer capable of improving phase noise. A sinusoidal signal with a frequency set by a frequency setting part is output as a digital signal from a set signal output part, and the digital signal is D/A-converted. A difference between a sinusoidal signal with a frequency corresponding to an output frequency of a voltage controlled oscillating part and a sinusoidal signal output from a D/A converting part is amplified by a differential amplifier, and an amplified signal is input via an A/D converting part to a means for extracting a phase difference between the aforesaid sinusoidal signals. A voltage corresponding to a signal being the result of integration of the phase difference is input as a control voltage to the voltage controlled oscillating part. Then, a gain of the differential amplifier is set larger than a maximum value of phase noise degradation of the A/D converting part, whereby the phase noise degradation of the A/D converting part is cancelled.

Abstract: Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.

Abstract: One embodiment relates to an integrated circuit which includes a transmitter buffer circuit, a duty cycle distortion (DCD) detector, correction logic, and a duty cycle adjuster. The DCD detector is configured to selectively couple to the serial output of the transmitter buffer circuit. The correction logic is configured to generate control signals based on the output of the DCD detector. The duty cycle adjuster is configured to adjust a duty cycle of the serial input signal based on the control signals. Another embodiment relates to a method of correcting duty cycle distortion in a transmitter. Other embodiments and features are also disclosed.

Abstract: A slew rate enhancing system includes first and second modules. The first module is configured to generate a first output signal in response to complementary first and second input signals. The second module is configured to generate a second output signal in response to the first and second input signals. The first module is configured to switch between tracking the first input signal and not tracking the first input signal during each half cycle of the first input signal based on values of the first input signal, the second input signal, and a predetermined threshold of the first module. The second module is configured to switch between tracking the first input signal and not tracking the second input signal during each half-cycle of the second input signal based on values of the first input signal, the second input signal, and a predetermined threshold of the second module.

Abstract: A signal transmission circuit includes a first selection driver configured to generate a first drive signal in response to an input signal and a first selection signal and drive a transmission signal in response to the first drive signal, and a second selection driver configured to delay the input signal by a first delay time to generate a first delay signal. The second selection driver generates a second drive signal in response to the first delay signal and a second selection signal, generates a first code signal in response to the input signal and the second selection signal, and drives the transmission signal in response to the second drive signal and the first code signal.

Abstract: The present invention discloses a phase interpolating apparatus comprising: a first signal generation circuit, configured for generating a first signal having a first phase; an optional second signal generation circuit, configured for generating a second signal having the first phase; a third signal generation circuit, configured for generating a third signal having a second phase; a fourth/fifth signal generation circuit, configured for generating a fourth signal having a third phase when operating in a first mode and for generating a fifth signal having the second phase instead of the fourth signal when operating in a second mode; and a phase interpolator, configured for generating an interpolated signal without utilizing the fourth signal when operating in the first mode and for generating the interpolated signal according to the first signal, the third signal, and the fifth signal when operating in the second mode.

Abstract: An interpolation circuit includes: a generation circuit that generates interpolation data from a plurality of pieces of input data, using an interpolation coefficient, among input data inputted in time series including a data point and a transition point; a detection circuit that detects that the input data lacks at the data point; and a coefficient circuit that changes the interpolation coefficient for each given data interval, and skips a position for changing the interpolation coefficient to the transition point when the detection circuit detects the lack of the input data.

Abstract: A signal transmission circuit includes a first selection driver configured to generate a first drive signal in response to an input signal and a first selection signal and drive a transmission signal in response to the first drive signal, and a second selection driver configured to delay the input signal by a first delay time to generate a first delay signal. The second selection driver generates a second drive signal in response to the first delay signal and a second selection signal, generates a first code signal in response to the input signal and the second selection signal, and drives the transmission signal in response to the second drive signal and the first code signal.

Abstract: A phase shifter includes a low-pass filter, a high-pass filter, and an all-pass filter coupled in series between an RF input terminal and an RF output terminal of the phase shifter, at least one of the filters being tunable, controlling the phase of an input signal over a wide range of frequencies.

Abstract: A method for reducing noise in a frequency synthesizer includes selecting a design variable k, calibrating a feedback time delay (Td), such that Td=kTVCO, where TVCO is the period of the synthesizer output signal. The method further includes estimating an instantaneous quantization error to a number of bits equal to q, defining a reference bias current of Icp/(k2q), where Icp is a charge pump current signal, and applying the estimated instantaneous quantization error to a current array to produce a down modification signal (?I). The current array is biased by the reference bias current. The down modification signal (?I) is summed with the charge pump current signal Icp to modulate a down current portion of the charge pump current signal Icp.

Abstract: A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.

Abstract: Embodiments of a device and circuit implementing a digitally controlled oscillator with reduced analog components. In an example, the digitally controlled oscillator can include a phase accumulator controlled by a stall circuit to selective stall the phase accumulator. In some examples, the digitally controlled oscillator can include a phase select circuit to select multiple phases of a phase select circuit based on the output of the phase accumulator. In some examples, these selected phases can then be used by a phase interpolator to generate a synthetic clock signal.

Abstract: A data acquisition system includes an analog-to-digital converter (ADC) having a MUX control outputs, a controller coupled to the ADC, a multiplexer coupled to the MUX control outputs of the ADC, and an operational amplifier coupling an analog data output of the multiplexer to an input of the ADC. An ADC having integrated multiplexer control includes control logic circuitry, ADC circuitry, MUX logic and an oscillator coupled to the control logic circuitry, the ADC circuitry, and the MUX logic.

Abstract: Duty cycle based phase interpolators, and methods for implementing duty cycle based phase interpolators are disclosed. One such phase interpolator includes a first pulse width modulator configured to generate a first duty cycle signal, and a second pulse width modulator configured to generate a second duty cycle signal. The phase interpolator further includes a logic unit configured to merge the first duty cycle signal and the second duty cycle signal to produce a periodic digital signal with a controllable phase depending on the first and second duty cycle signals.

Abstract: A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.

Abstract: A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.

Abstract: A phase interpolation circuit includes a waveform shaping unit and a phase interpolator. The waveform shaping unit adaptively waveform-shapes first or second phase offset input clock signal pair that is applied, to output first and second buffered clock signals having a rising time and falling time each of more than about a quarter of a period of the first and second offset input clock signals. The phase interpolator is applied to generate a phase interpolation clock signal selected from phases between the first and second buffered clock signals in response to a weight value of a phase interpolation control signal.

Abstract: An embodiment of the invention discloses phase shifting a second clock signal by a phase increment with respect to a first clock signal, where the first clock signal and the second clock signal have the same periods. The first clock signal is sampled with the second clock signal, and the output of the sample indicates whether the sample of the first clock signal is at a logic one state or a logic zero state. A count of logic one samples is incremented if the sample of the first clock signal is at a logic one state. The process of phase shifting the second clock signal and sampling the first clock signal is repetitively performed to a maximum number of samples.

Abstract: A phase shifter comprises a differential quadrature all-pass filter (QAF) including a balanced input port and two balanced output ports. A quadrature phase shift is manifested between the balanced output ports. The phase shifter also comprises a resistance-capacitance polyphase filter (PPF) section defining two balanced input ports and two balanced output ports. The balanced input ports of the PPF are coupled to the balanced output ports of the QAF. The combination exhibits broad bandwidth and relatively low ohmic loss.

Abstract: Methods and systems to adjust a phase difference between signals, such as to perform quadrature phase correction. First and second signals are digitally compared, such as with exclusive OR circuitry, to provide a comparison signal having a duty cycle representative of a phase difference between the signals. A phase delay of one or both of the first and second signals is adjusted until the duty cycle of the comparison signal corresponds to a desired phase difference. In a clock and data recovery system, the signals may correspond to a zero degree phase of a first phase interpolator and a ninety degree phase of a second phase interpolator, and digital codes to the first and second phase interpolators may be adjusted to provide a fifty percent duty cycle in the comparison signal.

Abstract: An exemplary phase interpolator includes a first to a fourth differential pair. Each of the differential pairs includes a first and a second transistor and a stabilizing capacitor connected between a source coupled node and a reference voltage. The phase interpolator also includes a plurality of current sources and a group of switches to switch connections between the source coupled nodes of the differential pairs and the current sources so that (i) a first operating current is supplied to a first selected one of the first and second differential pairs and (ii) a second operating current is supplied to a second selected one of the third and fourth differential pairs. Drains of the first transistors in the differential pairs are commonly connected and drains of the second transistors in the differential pairs are commonly connected to form a first and a second output node so that a differential output signal is output.

Abstract: Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase interpolator. The more linear slope on the output of the push-pull buffer may improve the linearity of a phase interpolator using the clock signals output from the push-pull buffers.

Abstract: A third periodic signal is synthesized using a first output signal having a phase corresponding to a first periodic signal and a second output signal having a phase corresponding to the second periodic signal. A value of the third periodic signal is detected at a timing of the phase of the delayed first periodic signal. The value of the third periodic signal detected with the delayed first periodic signal is compared with the value of the third periodic signal detected by the first periodic signal delayed by the different delay amount. The delay amount is obtained for the detected third periodic signal being a maximum or a minimum. In a state of the optimum delay amount, an amplitude of the third periodic signal is adjusted so that the detected value of the third periodic signal falls within a predetermined range.

Abstract: In one embodiment of the invention, a method is disclosed to generate a clock output signal with selected phase. The method includes selecting a phase delay for the clock output signal; charging a capacitor with a first weighted current during a first phase input clock, charging the capacitor with a second weighted current during a portion of a second phase input clock, and determining if a voltage across the capacitor is greater than or equal to a threshold voltage to generate a first edge of the clock output signal with the selected phase delay. The first weighted current may have a weighting of N out of M to charge the capacitor with a predetermined rate of change in voltage in response to the selected phase delay. The second weighted current may have a weighting of M out of M to charge the capacitor with a constant rate of change.

Abstract: A phase shifter with selectable phase shift and comprises a switchable phase shifting element that includes a first and second signal path coupled between an input and an output and providing a, respective, first and second phase shift for a signal coupled through the respective signal paths; a switch circuit for selecting between the first and second signal paths where the first and second signal paths and the switch circuit are configured to equalize the insertion loss for the first and second signal path, the phase shifter further including control circuit for controlling the switch circuit.

Abstract: A clock generator includes a first latch configured to output a first intermediate clock phase signal based on a first clock signal and a second intermediate clock phase signal. A first phase interpolation circuit has a first input coupled to a first input of the first latch and a second input coupled to a first output of the first latch. The first phase interpolation circuit is configured to output a first clock phase signal based on the first and second intermediate clock phase signals.

Abstract: A semiconductor integrated circuit includes: a plurality of chips configured to receive an external voltage. Each one of the chips detects a signal delay characteristic of the one of the chips to generate an internal voltage having a level corresponding to the signal delay characteristic.

Abstract: Disclosed is a mixer able to simultaneously suppress self-mixing and low-order harmonic response in a charge sampling circuit. Specifically disclosed is a multiphase mixer provided with a transconductance amplifier (101) for converting a voltage signal into a current signal, an N number (where N is a natural number that is 2 or more) of first integrators (401, 402) which are connected in parallel to the subsequent stage of the transconductance amplifier (101), and a 2N number of mixers (102, 103, 104, 105) connected in parallel in pairs to the respective N number of first integrators (401, 402), wherein two mixers connected to the same first integrator of any of the N number of first integrators (401, 402) are controlled by driving signals comprised of pulse trains with the same frequency and phases differing by 180°.

Abstract: Phase profile generator systems and methods are disclosed. A system includes a signal generator, a target phase trajectory module, an error detector and a control loop filter. The signal generator is configured to generate an output signal. In addition, the target phase trajectory module is configured to track a target phase trajectory and determine a next adjustment of the output signal to conform the output signal to a portion of the target phase trajectory. Further, the error detector is configured to determine an error between the output signal and a current target phase trajectory value that precedes the portion of the target phase trajectory, where the determination of the error is independent of the next adjustment of the output signal. Moreover, the control loop filter is configured to control the signal generator in accordance with both the next adjustment and the error to generate a phase profile.

Abstract: Active directional couplers are provided. In accordance with certain embodiments of the invention, the subject active directional couplers are tunable. The tuning is accomplished via varactors connected to the lines of the active directional couplers. Active directional elements are provided between different lines of the subject active directional couplers to control a signal path between ports of the different lines. The active directional elements are selected from diodes, transistors, inverting amplifiers, non-inverting amplifiers, differential amplifiers, and active baluns. The lines include a phase shift element between the two ports of each line. The phase shift element is selected from a transmission line, a delay line, and a phase shifter. Advantageously, the subject lines do not have to be designed for ideal phase shifting and can be designed at near 90° or near ?/4 values.

Abstract: One embodiment relates to an integrated circuit which includes a transmitter buffer circuit, a duty cycle distortion (DCD) detector, correction logic, and a duty cycle adjuster. The DCD detector is configured to selectively couple to the serial output of the transmitter buffer circuit. The correction logic is configured to generate control signals based on the output of the DCD detector. The duty cycle adjuster is configured to adjust a duty cycle of the serial input signal based on the control signals. Another embodiment relates to a method of correcting duty cycle distortion in a transmitter. Other embodiments and features are also disclosed.

Abstract: An interpolation circuit, includes a bias generating module, a load module consisting of a current source sub-module and a load resistance sub-module, first and second clock control modules, and an output module. The first clock control module includes a first input sub-module, a first source terminal negative feedback sub-module, a first multiplex switch sub-module and a first multiplex current sink sub-module. The bias generating module includes first, second and third FETs, and a bias current terminal. The current source sub-module includes fourth and fifth FETs. The load resistance sub-module includes first and second resistors. The first input sub-module includes sixth and seventh FETs. The first source terminal negative feedback sub-module includes a third resistor and a first capacitor. The first multiplex switch sub-module includes first and second groups of switches. The first multiplex current sink sub-module includes first and second groups of FETs. An interpolation system is further provided.

Abstract: An apparatus comprising: a first control switch driven by a first bit value; a first weighted switch driven by a first clock signal; a first intermediate node coupled between the first control switch and the second weighted switch; a first precharge transistor coupled to the first intermediate node, wherein the precharge transistor is driven by an inverse of the clock signal; a second control switch driven by an inverse of the bit; a second weighted switch driven by a second clock signal; a second intermediate node coupled between the second control switch and the second weighted switch; a second precharge transistor coupled to the second intermediate node, wherein the second precharge transistor is driven by an inverse of the second clock signal; and a capacitor coupled to the first control switch, the second control switch, the first precharge transistor and the second precharge transistor.

Abstract: Embodiments of the invention may be directed to a continuous analog phase shifter for radio frequency (RF) signals, which can be integrated on a CMOS process or another compatible process where inherent process-dependent passive components such as inductors and capacitors may have low quality factors. Insertion loss degradation for a given amount of phase shift may be compensated by using an active compensation circuit/device that smartly controls negative resistance generated from the compensation circuit/device to cancel out finite resistance of a network, leading to very small insertion loss variation. According to an example aspect of the invention, improved phase linearity and increased phase shift for a given size may be obtained by incorporating the compensation circuit/device. Thus, example analog phase shifters in accordance with example embodiments of the invention may have one or more of low insertion loss variation, small size, and good phase linearity over more than a 360 degree phase shift.