Abstract: Various embodiments provide a Phase Interpolator (PI) that receives input clocks, and outputs intersymbol interference-equalized, phase-shifted output clocks. In one embodiment, the Phase Interpolator comprises two PI Conditioners and a PI Mixer. In one embodiment, a PI Conditioner receives input clocks and is controlled by a different phase-shifted input clock by using a suitable circuit element, such as a flip-flop. Collectively, the input clock-controlled PI Conditioner and Mixer act in concert to control the band limiting effect of the PI Conditioner which, in turn, equalizes intersymbol interference.

Abstract: A waveform generating circuit includes a constant current circuit that supplies a constant current through a power source; a current mirror circuit that flows an output current that is n times an input current; and a switching circuit that switches a flowing direction of the current in the constant current circuit between the current mirror circuit and the output terminal according to the logical level of the rectangle input signal. The waveform generating circuit generates a triangle wave having a falling slope waveform that is n times the rising slope. On the other hand, the waveform generating circuit that receives an inverted signal of the signal generates a triangle wave and its voltage is compared with another in the comparator to generate an output signal.

Abstract: A phase shift circuit that includes two, rather than four, delay chains and corresponding selectors is described. This provides a significant area savings and reduces the intrinsic delay of the phase shift circuit, which is particularly beneficial for embodiments in which there is no intrinsic delay matching. In one implementation, the phase shift circuit includes a first delay circuit and a matching delay circuit. The first delay circuit provides a first delay that includes a first intrinsic delay and a first intentional delay. The delay matching circuit provides a matching delay that matches the first intrinsic delay. In one implementation, the phase shift circuit also includes a second delay circuit to provide a second delay that includes a second intrinsic delay and second intentional delay, where the second intrinsic delay matches the first intrinsic delay and the second intentional delay is half as long as the first intentional delay.

Abstract: A delay circuit includes: a delay unit configured to delay an input signal and output the delayed signal; a selecting unit configured to select a first signal at the time of a normal operation or a second signal at the time of a test operation, and provide the selected signal to the delay unit; an inverting unit configured to invert an output signal of the delay unit, and output the inverted signal as the second signal; and a counting unit configured to count an output waveform of the delay unit.

Abstract: A multi-phase signal generator may include a duty control buffer configured to receive a first differential input signal and a second differential input signal, and generate a first differential output signal and a second differential output signal having variable duty ratios based on a control voltage, a first edge combiner configured to generate a first pulse signal based on first edges of the respective first and second differential output signals, a second edge combiner configured to generate a second pulse signal based on second edges of the respective first and second differential output signals, and a control voltage generator configured to generate the control voltage in response to a logic signal obtained by performing a logic operation on the first and second pulse signals.

Abstract: A phase detector apparatus and method used for clock recovery from a data signal is provided. The phase detector provides phase correction signals to a clock signal generator, where the phase correction signals are only generated if a predetermined data sample pattern is observed. In particular, the predetermined data sample pattern is preferably a transition from one to zero. Thus, transitions from zero to one will not provide a valid phase update output signal, even though a transition has occurred. In other embodiments the predetermined data sample pattern is preferably a one to zero transition preceded by an additional logic one sample.

Abstract: In a particular embodiment, a circuit device includes a pulse edge control circuit to receive at least one pulse-width modulated (PWM) signal from a PWM source. The pulse edge control circuit is adapted to selectively apply a phase shift operation to the at least one PWM signal at integer submultiples of a frame repetition rate to produce at least one modulated PWM signal having a changed power spectrum. The pulse edge control circuit provides the at least one modulated PWM signal to at least one output of the pulse edge control circuit.

Abstract: In general, in one aspect, the disclosure describes a delay line including a cascade of delay stages where each stage delays the phase a defined amount. Each delay stage includes an active voltage control delay element and one or more passive delay elements (e.g., resistive-capacitive (RC) networks). The aggregate amplitude gain roll-off of an active/passive multi pole delay stage delaying the phase a defined amount is less than the amplitude gain roll-off of a single pole delay stage delaying the phase the defined amount. Accordingly jitter amplification of the active/passive multi pole delay stage is less than that of a single pole delay stage. The power consumption of an active/passive multi pole delay stage is less than an all active multi pole delay stage.

Abstract: A phase detector apparatus and method used for clock recovery from a data signal is provided. The phase detector provides phase correction signals to a clock signal generator, where the phase correction signals are only generated if a predetermined data sample pattern is observed. In particular, the predetermined data sample pattern is preferably a transition from one to zero. Thus, transitions from zero to one will not provide a valid phase update output signal, even though a transition has occurred. In other embodiments the predetermined data sample pattern is preferably a one to zero transition preceded by an additional logic one sample.

Abstract: A phase interpolator includes a first circuit to generate a first signal having a first phase delay and a second signal having a second phase delay and a phase mixer. The phase mixer is coupled to receive the first and second signals from the first circuit. The phase mixer includes multiple current drivers each including a current driver input coupled to selectively delay one of the first or second signals and a current driver output coupled to output a phase delayed signal. The current driver outputs of the current drivers are coupled together to combine the phase delayed signals from the current drivers to generate an output phase delayed signal having a phase interpolated from the first and second signals.

Abstract: The present invention provides a phase shifter comprising a first multiplier unit that outputs a first output signal obtained by multiplying an input signal input thereto by a multiplication value calculated based upon a first digital control signal also input thereto and specifying a phase shift quantity for the input signal, a second multiplier unit that outputs a second output signal obtained by multiplying an orthogonal input signal input thereto and having a phase perpendicular to the phase of the input signal by a multiplication value calculated based upon a second digital control signal also input thereto and specifying the phase shift quantity, and an adder/subtractor unit that executes addition or subtraction by using the first output signal and the second output signal based upon a third digital control signal corresponding to the phase shift quantity.

Abstract: A programmable delay lock loop system provides a delayed output signal having a programmed delay from an input signal. A phase detector provides a phase delay signal indicative of an actual phase difference between the input signal and the delayed output signal. An accumulator provides a delay command signal as a function of a difference between a commanded delay and the actual phase difference. A programmable phase delay circuit is configured to generate a ramp signal based upon the input signal, to adjust the ramp signal with respect to a threshold level in response to the delay command signal, to generate a trigger signal based upon a comparison of the ramp signal with the threshold level, and to clock the delayed output signal in response to the trigger signal.

Abstract: A phase splitter that receives an external clock signal and that generates first and second internal clock signals having a phase difference of 180° between the first and second internal clock signals, the phase splitter including: a first buffer that buffers the external clock signal and outputs a first signal; an inverting unit that inverts the external clock signal and outputs a second signal; a second buffer that buffers the second signal and outputs a third signal; a first interpolating signal generator that inverts the external clock signal and outputs a fourth signal; and a second interpolating signal generator that inverts the second signal and outputs a fifth signal. The first signal and the fifth signal are interpolated to generate the first internal clock signal. The third signal and the fourth signal are interpolated to generate the second internal clock signal.

Abstract: A deskew system includes a first voltage control delay receiving a data signal and generating N-numbered delayed data signals obtained by delaying a phase of the data signal in units of 90/N, where N is a natural number that is not less than 1. In response to a phase control signal, a second voltage control delay receives a clock and generates N-numbered delayed clocks by delaying a phase of the clock in units of 90/N. A skew compensation control unit generates a plurality of skew control signals to compensate for skew between the data signal and the clock based on the data signal, the N-numbered delayed data signals, the clock, and the N-numbered delayed clocks.

Abstract: Methods and apparatus are provided for improving phase switching and linearity in an analog phase interpolator. A phase interpolator in accordance with the present invention comprises (i) a plurality of tail current sources that are activated for substantially all times when the phase interpolator is operational; (ii) at least two pairs of input transistor devices, wherein one pair of the input transistor devices is associated with a minimum phase of the phase interpolator and another pair of the input transistor devices is associated with a maximum phase of the phase interpolator; and (iii) a plurality of current steering switches that provide currents generated by the plurality of tail current sources to one or more of the at least two pairs of input transistor devices, based on an applied interpolation control signal.

Abstract: A method for processing information is described. The method includes providing a phase reference, ?i, where the phase reference comprises N distinct values, expressed as ?i=?0 . . . ?N?1. A reset signal is received. The phase reference, ?0, is initialized in response to receipt of the reset signal. The phase reference values are repeatedly advanced from ?0 through ?N?1. The process then includes enabling at least one function at a predetermined phase reference value ?A, wherein ?A?{?0 . . . ?N?1}.

Abstract: A phase interpolation circuit and method are provided that are capable of operating in a low voltage and capable of generating a substantially exact phase-interpolation signal, where the phase interpolation circuit is configured to output a phase interpolation signal having a phase between phases of at least two input signals and comprises an interpolation unit configured to discharge an output node by a first interpolation control signal in case a first input signal of two input signals having different phases is inputted to the interpolation unit when the output node has been precharged to a power supply voltage level, the interpolation unit additionally discharging the output node by a second interpolation control signal in case of input of a second input signal of the two input signals; a comparison unit for comparing a reference voltage level and a voltage level of the output node of the interpolation unit to output a signal corresponding to the comparison; and a short pulse generation unit for generatin

Abstract: A method, circuit, and system are disclosed. In one embodiment, the method comprises receiving a differential clock signal from two clock signal lines into a first differential pair of transistors of a first size, receiving the differential clock signal from the two clock signal lines into a second differential pair of transistors of a size smaller than the first size, converting the differential clock signal into a single-ended clock signal, outputting the single-ended clock signal through an inverter, and synchronizing any differential clock phase error by controlling the transconductance between the first differential pair of transistors and the second differential pair of transistors.

Abstract: A phase interpolator circuit may comprise a multiplexer circuit (MUX) to receive a plurality of clock signals at MUX inputs and to output a first clock signal and a second clock signal that are out of phase with each other, a digital to analog converter circuit (DAC) to convert a digital input to first and second DAC output currents such that a sum of the first and second DAC output currents comprises a substantially constant current value, and a weighted averager circuit coupled to the MUX and the DAC. The weighted averager circuit may operate to sum weighted first and second clock signals and to output a phase interpolated clock signal. The first clock signal may be weighted according to the first DAC output current and the second clock signal may be weighted according to the second DAC output current. Other apparatus, systems, and methods are disclosed.

Abstract: In order to mitigate electromagnetic interference (EMI), the present invention provides a circuit device for an electronic device including a signal generating unit, a phase adjusting unit and an output interface. The signal generating unit generates a plurality of in-phase signals. The phase adjusting unit is coupled to the signal generating unit and is used for adjusting the plurality of in-phase signals to generate a plurality of output signals, where all or some of the output signals have different phases. The output interface is coupled to the phase adjusting unit and is used for outputting the plurality of output signals to a plurality of signal processing units for image processing.

Abstract: Provided are a digital phase interpolator, which performs linear phase interpolation irrelevantly to input order of two input signals, and a semi-digital delay locked loop (DLL), which includes and controls the same. The phase interpolator includes: a first clocked inverter controlled by a phase indicating signal and providing a first output signal to a common output terminal by inverting a first input signal, and a second clocked inverter controlled by the phase indicating signal and providing a second output signal to the common output terminal by inverting the second input signal. The second clocked inverter is clocked by the first input signal when the phase indicating signal is in a first logic state, and the first clocked inverter is clocked by the second input signal when the phase indicating signal is in a second logic state.

Abstract: A phase shift circuit that includes two, rather than four, delay chains and corresponding selectors is described. This provides a significant area savings and reduces the intrinsic delay of the phase shift circuit, which is particularly beneficial for embodiments in which there is no intrinsic delay matching. In one specific implementation, the phase shift circuit includes a first delay circuit and a matching delay circuit. The first delay circuit provides a first delay that includes a first intrinsic delay and a first intentional delay. The delay matching circuit provides a matching delay that matches the first intrinsic delay. In one specific implementation, the phase shift circuit also includes a second delay circuit to provide a second delay that includes a second intrinsic delay and second intentional delay, where the second intrinsic delay matches the first intrinsic delay and the second intentional delay is half as long as the first intentional delay.

Abstract: There is provided a signal generating apparatus including: a multiphase oscillating portion for generating a number of base signals having the same frequency and a predetermined phase difference of which the signal level transitions between a first level and a second level, and where periods during which the signal level of any given base signal is at the first level and the signal level of the next base signal having the predetermined phase delay relative to the given base signal is at the first level overlap; and a transition time point changing portion for generating a pulse signal by changing the time point when each base signal transitions from the first level to the second level to a time point before the next base signal transitions from the second level to the first level.

Abstract: The invention relates to a phase-interpolation circuit and a phase-interpolation signal generating circuit applying the phase-interpolation circuit. The phase-interpolation circuit can avoid short-circuit current effectively. In addition, an inter-phase signal can be interpolated between the rising edge and the falling edge of the clock pulse. The phase-interpolation signal generating device can generate multiphase clock signals which not only have linearly distributed phases but also maintain good 50% duty cycle of the multiphase clock signals.

Abstract: An active 90-degree phase shifter with LC-type emitter (source) degeneration is provided, which is practiced in an integrated circuit. The phase shifter comprises a first differential amplifier, having one first signal output end and comprising an inductor, a first transistor and a second transistor, wherein the inductor is connected to the emitters (sources) of the first and the second transistors; and a second differential amplifier, having one second signal output end and comprising a capacitor, a third transistor and a fourth transistor, wherein the capacitor is connected to the emitters (sources) of the third and the fourth transistors. Wherein the bases (gates) of the first and the fourth transistors are signal input ends, and the bases (gates) of the second and the third transistors are coupled together.

Abstract: The methods and circuits of the various embodiments of the present invention relate to phase shifting of a generated clock signal. According to one embodiment, a method of phase shifting a clock signal using a delay line is described. The method comprises the steps of coupling a first delay line and a second delay line in series; generating a transition edge using the first delay line; generating an opposite transition edge using the second delay line; and outputting a first phase shifted clock signal based upon the transition edge and the opposite transition edge of the clock signal. A circuit for shifting a clock signal is also disclosed.

Abstract: A method of phase angle control including the steps of generating a first periodic function having a first amplitude and generating a second periodic function having a second amplitude, which second periodic function is phase shifted relative to the first periodic function by a first phase angle. The method further includes generating a first positive feedback periodic function and generating a second positive feedback periodic function which is phase shifted relative to the first positive feedback periodic function by a second phase angle. In addition, the method includes generating a first control function, a first weighting function, a second weighting function, and linearly combining the product of the first positive feedback periodic function and the first weighting function with the product of the second positive feedback periodic function and the second weighting function to generate a second control function.

Abstract: A programmable delay circuit including a first inverter, a second inverter, a variable resistance unit, and a variable capacitance unit is provided. The first inverter receives a positive-phase received signal, and transmits an anti-phase output signal through an anti-phase output signal line. The second inverter receives an anti-phase received signal, and transmits a positive-phase output signal through a positive-phase output signal line. The variable resistance unit regulates an equivalent resistance between the anti-phase output signal line and the positive-phase output signal line according to M bits in a delay-controlled code. The variable capacitance unit regulates an equivalent capacitance between the anti-phase output signal line and the positive-phase output signal line according to N bits in the delay-controlled code.

Abstract: A phase interpolator circuit may comprise a multiplexer circuit (MUX) coupled to a plurality of clock signals at MUX inputs and may provide a first clock signal and a second clock signal at MUX outputs that are out of phase with each other, a digital to analog converter circuit (DAC) to convert a digital input to first and second DAC current outputs such that a sum of the first and second DAC output currents comprises a substantially constant current value, a weighted averager circuit coupled to the MUX and the DAC, and a variable capacitive load circuit coupled to the first and second DAC current outputs. The weighted averager circuit may operate to sum weighted first and second clock signals and to output a phase interpolated clock signal, wherein the first clock signal is weighted according to a first DAC output current and the second clock signal is weighted according to a second DAC output current. Other apparatus, systems, and methods are disclosed.

Abstract: Disclosed is a phase shift circuit. The phase shift circuit comprises a frequency multiplier outputting a square wave signal by frequency-multiplying a reference signal, a frequency synchronizer receiving the square wave signal to output a triangle wave signal, and a PWM nodule receiving the triangle wave signal to output a phase-shifted multi-channel control signal.

Abstract: An integrated circuit includes clock deskew circuitry. The deskew circuitry includes multiple loop circuits to align a received clock with a data eye, and to reduce the effects of clock drift caused by voltage and temperature variations. The loop circuits include phase interpolators to produce local clock signals. Local clock signals are provided to seqiuential elements through local clock trees and are also provided to a phase detector through a dummy local clock tree. The operation of the phase interpolators is influenced by the phase detector.

Abstract: A phase interpolator generates a phase-interpolated output clock signal Z from two phase-offset input clock signals A and B, where the interpolation angle of the output clock is based on a weight value W. The phase interpolator has A-side and B-side circuitry, each having (1) an array of parallel current mirrors, (2) a block of parallel switches, where each switch is connected in series with a corresponding current mirror, and (3) an encoder that controls the corresponding switches based on the weight value W. The total current through the phase interpolator varies with interpolation angle, such that, for example, the variation in output amplitude with interpolation angle is reduced. In general, individual bit values in weight value W are not used to control individual switches for all interpolation angles.

Abstract: There is provided a clock phase interpolator comprising a pair of output nodes, at least three complementary clock signal inputs, an equal plurality of current sources, and an equal plurality of clock switching sections. Each clock switching section is connected to switch, under the control of a complementary clock signal on a respective one of the complementary clock signal inputs, the current provided by a respective one of the current sources between the two output nodes. The current sources are controllable to provide interpolation between signals on the complementary clock signal inputs. Also provided is a clock phase interpolator comprising a pair of output nodes, two complementary clock signal inputs, an equal plurality of current sources, an equal plurality of clock switching sections.

Abstract: A phase adjustor circuit and a phase adjusting method are capable of preventing a phase shift amount from fluctuating even if a frequency of a transmission carrier wave of a sensor signal fluctuates. A chopping wave converter circuit converts a pulse string signal into a chopping wave. A chopping wave amplitude control circuit compares the amplitude value of the chopping wave with an amplitude reference value and outputs an adjustment signal corresponding to a difference between those values to the chopping wave converter circuit. The chopping wave converter circuit changes a slope of the chopping wave according to the adjustment signal to adjust the amplitude value of the chopping wave. As a result, a feedback group is structured, and the amplitude value of the chopping wave is maintained to a constant value according to the amplitude reference value.

Abstract: Method and apparatus for interpolation of signals from a delay line is described. An input signal is obtained from which progressively delayed input signals are generated from the input signal. Two of the progressively delayed input signals are accessed and interpolated to provide a phase-adjusted signal.

Abstract: A characteristic detecting unit detects characteristics of a digital imaged signal at every phase shift interval set in advance. A timing adjustment unit gives a phase adjustment instruction of a pulse so as to converge to an imaging phase in the digital imaged signal at which the characteristics are a predetermined value or within a predetermined range. A shift interval switching unit switches the phase shift interval according to photographing conditions of an imaging element.

Abstract: A broad frequency range phase shift circuit is responsive to a radio-frequency signal generated by a radio-frequency source and generates a lagging phase signal and a leading phase signal, 90° out of phase with the lagging phase signal, corresponding to the radio-frequency signal. An operational amplifier has a signal input that receives the radio-frequency signal from the radio-frequency source and generates a low impedance amplified output signal. A series resonant circuit receives the amplified signal from the operational amplifier and shifts the phase of the amplified signal in an amount that approaches 90° as the amplified signal frequency approaches DC to 0° as the amplified signal frequency increases to the cut-off frequency. A transmission line receives the amplified signal from the operational amplifier and has an electrical length substantially equal to one-fourth of a wavelength corresponding to the cut-off frequency.

Abstract: The 90-degree phase shifter of the invention has: a T flip-flop including transistors Q3 to Q6 and Q9 to Q12 that together constitute a dual differential circuit, input transistors Q1 and Q2 that receive at their bases an input signal, and input transistors Q7 and Q8 that receive at their bases a signal complementary to the input signal; variable current sources 14 to 17 connected respectively to the nodes between the individual input transistors and the dual differential circuit; and a 90-degree phase comparator 10 that compares the phase differences between the signals outputted from the T flip-flop to output signals commensurate with the deviations of those phase differences from 90 degrees. The variable current sources 14 to 17 are controlled by signals based on the signals outputted from the 90-degree phase comparator 10. This configuration more surely yields output signals with a phase difference of exactly 90 degrees.

Abstract: A phase interpolator generates a phase-interpolated output clock signal Z from two phase-offset input clock signals A and B, where the interpolation angle of the output clock is based on a weight value W. The phase interpolator has A-side and B-side circuitry, each having (1) an array of parallel current mirrors, (2) a block of parallel switches, where each switch is connected in series with a corresponding current mirror, and (3) an encoder that controls the corresponding switches based on the weight value W. The total current through the phase interpolator varies with interpolation angle, such that, for example, the variation in output amplitude with interpolation angle is reduced. In general, individual bit values in weight value W are not used to control individual switches for all interpolation angles.

Abstract: A phase shifter according to an embodiment of the present invention includes: an AC component amplifying unit; and a dividing circuit. The AC component amplifying unit has positive gain slope characteristics and deforms a waveform of an input differential clock signal to output the deformed differential clock signal. The dividing circuit includes a T-flipflop having two D latches connected in series and receives the deformed differential clock signal defoemed by the AC component amplifying unit to generate at least two output signals having a phase difference of 90 degrees with a frequency of ½ of the deformed differential clock signal.

Abstract: A circuit for controlling phase includes a first node providing a current responsive to a first clock signal, a first plurality of switch circuits coupled to the first node, a first plurality of current supply sources coupled to the first plurality of switch circuits, respectively, a second node providing a current responsive to a second clock signal, a second plurality of switch circuits coupled to the second node, and a second plurality of current supply sources coupled to the second plurality of switch circuits, respectively, wherein the first node and the second node are coupled to combine the first clock signal and the second clock signal, at least one of the first plurality of current supply sources having a current supply amount different from another, and at least one of the second plurality of current supply sources having a current supply amount different from another.

Abstract: A steering current generator for a phase interpolator has a multiplicity of fine phase adjustment current sources, each of which is switchable to direct its current to one or other of two summing nodes. The current of each of those two summing nodes is supplemented by respective fixed always-on current sources. The steering current generator has four current outputs and a switching matrix is provided to switch the current from the summing nodes to first and second selected ones of those outputs. The switching matrix is also connected to switch bleed currents to the other two of the current outputs.

Abstract: A phase shifting device includes a signal source; a variable phase shifter; first and second doubling circuits; and a 90-degree phase comparator. An output from the signal source is connected to an input of the variable phase shifter and to an input of the second doubling circuit, an output from the variable phase shifter is connected to an input of the first doubling circuit, an output from the first doubling circuit serves as a first output signal, and an output from the second doubling circuit serves as a second output signal. The first output signal and the second output signal are inputted to the 90-degree phase comparator. The amount of phase shift rotation of the variable phase shifter is changed by a phase shift control signal outputted from the 90-degree phase comparator. By this, an exact 90-degree phase shift is obtained.

Abstract: A phase adjustor circuit and a phase adjusting method are capable of preventing a phase shift amount from fluctuating even in the case where a frequency of a transmission carrier wave of a sensor signal fluctuates. A chopping wave converter circuit converts a pulse string signal into a chopping wave. A chopping wave amplitude control circuit compares the amplitude value of the chopping wave with an amplitude reference value, and outputs an adjustment signal corresponding to a difference between those values to the chopping wave converter circuit. The chopping wave converter circuit changes a slope of the chopping wave according to the adjustment signal to adjust the amplitude value of the chopping wave. As a result, a feedback group is structured, and the amplitude value of the chopping wave is maintained to a constant value according to the amplitude reference value.

Abstract: The present invention discloses a multi-phase clock generator of a network controller for generating a set of multi-phase clocks, and a method thereof. The multi-phase clock generator includes a first gating element and a second gating element. The first gating element operates according to a first control clock and generates a first output clock of the set of multi-phase clocks according to an input clock. The second gating element operates according to a second control clock and generates a second output clock of the set of multi-phase clocks according to the first output clock. The second control clock is an inverted signal of the first control clock.

Abstract: An output signal is generated with a predetermined phase shift with respect to an input signal using a closed loop control. The input and output signal of the closed loop control are logically combined in accordance with first and second combinatory logic to generate first and second control signals. The first and second control signals selectively activate first and second current sources, respectively. The current supplied by the first current source charges a capacitance controlling the closed loop control, while the current supplied by the second current source discharges the capacitance. By selecting the types of the combinatory logics as well as the ratio of the currents supplied by the first and second current sources, the phase shift of the output signal with respect to the input signal can be variably adapted to individual requirements.

Abstract: A precision timing generator and an associate method provide a precise clock signal based on a reference clock signal. Using the reference clock signal in a phase locked loop or delay locked loop, a number of clock signals of equal frequency are generated separated consecutively by a known phase. Two of these clock signals of consecutive phases are selected for interpolation for higher precision according to predetermined weights. The resulting interpolated clock signal has a phase offset that is intermediate between the selected clock signals in proportion to the predetermined weights. In one implementation, a second interpolated clock signal is created by selecting and weighting a second group of clock signals using independent selection and weights. The two interpolated clock signals are then combined by logic operations to provide a precise clock signal of predetermined duty cycle and phase.

Abstract: A phase shift driver for phase shifting an input clock signal at a first phase to generate an output signal at a second phase without missing subsequent input signals. Input logic circuitry of the phase shift driver may receive an input signal at a first phase. Output logic circuitry of the phase shift driver may generate an output signal at a second phase relative to the input signal. The output signal may be a phase-shifted version of the input signal. A reset control circuit may receive a feedback signal from the output logic circuitry and an intermediate signal from the input logic circuitry and generate a reset signal based on the received feedback and intermediate signals. The reset control circuit may control a pulse width of the reset signal to reset the input logic circuitry within a period of time before the input logic circuitry receives a subsequent input signal.

Abstract: A timing signal generating circuit receives multiphase input signals and generates a signal having a phase intermediate therebetween, and weighting is applied to the multi-phase input signals by using a variable impedance circuit. The timing signal generating circuit (receiver circuit) can operate with a low supply voltage, is simple in configuration, and can generate timing signals with high accuracy.

Abstract: In a clock phase corrector appropriately correcting the phase of a data sampling clock signal, a series of shift registers responds to respective sampling clock signals to store received data sequentially. The stored data are duplicated by a comparator register in response to corresponding clock signals to output a demodulated signal. A corrector shift register is provided to store sampled data in response to a clock signal. The data thus stored are then held in a reception register as intended reception data. A comparator compares the demodulated signal with the intended reception data. Based upon a result from the comparison, a bit adder produces the number of inconsistent bits. Another comparator compares the number of inconsistent bits with the number of error acceptance bits stored in an error acceptance memory to generate a phase detection signal, in response to which a timing control adjusts the phase of a data sampling clock signal.