Abstract: A picosecond pulse generator apparatus and methodology is disclosed. A pulse generator is provided by forming a transmission line and a switching element on a common semiconductor substrate or semiconductor chip. The transmission line and the switching element can be provided on the common CMOS semiconductor substrate using standard CMOS technology. A voltage is applied to the transmission line to charge the transmission line. An input pulse is applied to the switching device to trigger the switching device to cause the transmission line to discharge an output pulse across a load resistor. The pulse width of the output pulse depends in major part on the length of the transmission line. Additional components can be provided on the common semiconductor substrate or chip to shape the input pulse to the switching device to ensure a fast rise time.

Abstract: A clock duty correction circuit includes a first current sourcing unit that sources a current to a current path in response to a clock signal, a first current sinking unit that sinks the current of the current path in response to the clock signal, a second current sourcing unit that sources a current to the current path in response to a delay clock signal obtained by delaying the clock signal by a predetermined time, a second current sinking unit that sinks the current of the current path in response to the delay clock signal, a current adjustment unit that adjusts an amount of the current flowing through the current path according to a voltage level of a control voltage, and a clock output unit that outputs an output clock signal having a voltage level corresponding to the amount of the current flowing through the current adjustment unit.

Abstract: A flag signal generation circuit includes a first periodic signal detection unit, a second periodic signal detection unit, and a flag signal output unit. The first periodic signal detection unit is configured to detect a change in a level of a first periodic signal and generate a first detection signal. The second periodic signal detection unit is configured to detect a change in a level of a second periodic signal and generate a second detection signal. The flag signal output unit is configured to generate a pre-flag signal from the first and second detection signals, buffer the pre-flag signal in response to a mode register read signal, and output the buffered pre-flag signal as a flag signal.

Abstract: A clock signal recovery device has a digital data signal input for the input of a digital data signal and a clock signal output for the output of a recovered clock signal. The digital data signal has a given nominal clock signal frequency. The clock signal recovery device is a digital circuit.

Abstract: A pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different state based on a cutting or non-cutting state of a fuse on which information on a change of process is programmed, and a pulse generator provided with a plurality of delay cells with predetermined time delay for selectively increasing or decreasing the number of the plurality of delay cells depending on the delay increase signal and the delay decrease signal to generate an internal clock with a pulse width corresponding to the number of the increased or decreased delay cells.

Abstract: A frequency-control circuit, which is configured to receive a first signal having a first untuned frequency from a first oscillator, and to alter one or more pulses of the first signal to tune an output frequency of an output clock signal to have an average frequency at the desired target frequency. In some embodiments, the frequency-control circuit receives a signal from a single oscillator to generate a calibrated, precise, and temperature-stable clock.

Abstract: A minimum leading edge blanking (MLEB) signal generator is provided. The MLEB signal generator includes a buck unit and a signal generation unit. The buck unit receives an error amplification signal, and generates a reference blanking signal. The reference blanking signal has a voltage lower than a voltage of the error amplification signal. The signal generation unit receives the reference blanking signal, and generates the MLEB signal according to the current sensing signal. When the current sensing signal is equal to the reference blanking signal, the MLEB signal changes its voltage level. As such, the width of the MLEB signal is a time width of the high level or low level of the MLEB signal before the voltage level of the MLEB signal changes. The MLEB is provided to an external unit, such that the external unit can be prevented from misoperation, thus improving the electric performance in its entirety.

Abstract: A multi-port circuit and corresponding method for simultaneous shaping of sub-nanosecond pulses (MCS3P). The MCS3P includes a coupled-line coupler, a Schottky detector diode, and circuitry for compressing the rising and falling edges of a waveform. The MCS3P simultaneously produces square wave, Gaussian, and monocycle waveforms by differentiating a sinusoidal source. The method includes the steps of compressing the rising edge of a sinusoidal source waveform, differentiating the resulting waveform to form a square waveform and a Gaussian waveform, filtering out the positive going Gaussian to produce a negative going Gaussian, differentiating the Gaussian waveform to form a monocycle waveform, and compressing the falling edge of the square waveform to produce a square wave form with both edges compressed.

Abstract: A data communication network may, include a first sub-network and a second sub-network. The first sub-network may include two or more two master clocks, and a synchronization system connected to the master clocks. The synchronization system may, for determine a time-base for the master clocks and control the master clocks based on the determined time-base. The first sub-network may include one or more slave synchronization data source for generating slave clock synchronization data derived from time information of the master clocks. The second sub-network may include one or more slave clocks and a slave clock time-base controller connected to the slave synchronization data source. The time-base controller may receive the slave clock synchronization data and control one or more of the one or more slave clocks in accordance with the slave clock synchronization data.

Abstract: A method is provided for propagating clock signals in a circuit segment having a first clocked device, a second clocked device and a data path between the first clocked device and the second clocked device. The data path propagates data released by the first clocked device to the second clocked device and is associated with a data propagation delay. The method comprises providing a clock propagation path for propagating clock signals to the first clocked device and the second clocked device, wherein the clock signal propagated to the second clocked device is delayed from the clock signal propagated to the first clocked device by a clock delay interval, the clock delay interval being related to the data propagation delay of the data path. A circuit segment making use of the above method is also provided.

Abstract: In accordance with some embodiments of the present disclosure, an oscillator may include a crystal resonator and a squaring circuit coupled to the crystal resonator and configured to convert a sinusoidal signal produced by the crystal resonator to a square-wave signal, the squaring circuit comprising a bias circuit configured to transmit a selected bias voltage for the squaring circuit, the selected bias voltage selected from a plurality of potential bias voltages. In accordance with this and other embodiments of the present disclosure, an oscillator may include a crystal resonator, an inverter coupled in parallel with the crystal resonator, and a programmable voltage regulator coupled to the inverter. The programmable voltage regulator may be configured to supply a first supply voltage to the inverter during a startup duration of the oscillator, and supply a second supply voltage to the inverter after the startup duration, wherein the second supply voltage is lesser than the first supply voltage.

Abstract: Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock pulses that are generated so that the pulse latches that are controlled by the clock pulses exhibit a reduced risk of race through conditions. Latch circuitry may be provided that is based on a pulse latch and an additional latch connected in series with the pulse latch. In situations in which there is a potential for race through conditions on an integrated circuit, the additional latch may be switched into use to convert the latch circuitry into an edge-triggered flip flop. Clock trees may be provide with configurable shorting structures that help to reduce clock skew. Low-contention clock drivers may drive signals onto the clock tree paths.

Abstract: A circuit that produces a clocking signal for a low to medium capacitance input of a device includes a drive gate connected to a common-base bi-polar driver circuit. The output of the drive gate is connected to an emitter of an NPN bi-polar transistor through one coupling capacitor and to an emitter of a PNP bi-polar transistor through another coupling capacitor. The transistors are connected in a common-base configuration with the collectors of the transistors connected together. One voltage is connected to the base of the PNP transistor. Another voltage is connected to the base of the NPN transistor. A diode is connected in parallel with the base-emitter of the PNP transistor. Another diode is connected in parallel with the base-emitter of the NPN transistor. A damping resistor is connected between the collectors of the transistors and the low to medium capacitance clock input of the device.

Abstract: The disclosure relates to a method for generating UWB waveforms, each comprising a sequence of pulses, the method comprising: generating consecutive elementary pulses having durations corresponding to setpoint durations and a constant amplitude, amplifying each elementary pulse separately as a function of a respective setpoint amplitude, and combining the amplified elementary pulses to obtain a waveform successively comprising each of the amplified alternately positive and negative, elementary pulses.

Abstract: A controller is configured to determine a word in a set of words corresponding to a received coding value, the set of words including at least one data word, at least one modulator command word and at least one gain command word. When the received coding value corresponds to a data word, the controller causes the data word to be modulated. When the received coding value corresponds to a modulator command word, the controller controls a modulator based on the modulator command word. When the received coding value corresponds to a gain command word, the controller controls a gain based on the gain command word.

Abstract: According to an aspect of the embodiment, a skew detecting unit includes at least one over delay path or racing path for detecting skew. A clock adjusting unit sets a set value of delay based on the skew detected by the skew detecting unit. A clock cell adjusts delay in a first clock according to the set value of the delay, and outputs the result as a second clock.

Abstract: The terminating module includes integrated circuits and a termination circuit which receive clock signals from the integrated circuit. The integrated circuit includes at least one memory integrated circuit mounted on a printed circuit board. An electrical connector is configured to couple the terminating module to a motherboard. Additionally, the termination circuit includes a resistor. In another embodiment, the terminating module provides a printed circuit board, a memory integrated circuit mounted on the circuit board, a terminator circuit which includes a resistor, and an electrical connector. The electrical connector couples the terminating module to a motherboard.

Abstract: Disclosed is a proportional controller that utilizes a deflected metal cantilever that provides a progressive change in capacitance for a given deflection that is used to generate a proportional control signal. In addition, a efficient step-up converter 1500 is disclosed, which is capable of operating with a single alkaline cell. Further, a LED drive circuit is disclosed that has high efficiency and is capable of driving an infrared LED with a single alkaline cell.

Abstract: A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes a voltage-controlled delay line generating a plurality of delayed clock signals having different phases. A plurality of the delayed clock signals are combined to generate a plurality of output signals. During an initialization period, an initialization circuit sets the delay of the delay line to a minimum delay value and then compares this delay value to the period of the input clock signal. Based on this comparison, the initialization circuit programs the programmable divider and adjusts the number of delayed clock signals combined to generate the output signals. More specifically, as the frequency of the reference clock signal increases, the divider is programmed to divide by a greater number, and a larger number of delay clock signals are combined to generate the output signals.

Abstract: Within hard disk drives (HDDs), for example, a preamplifier or preamp is generally used to perform read and write operations with a magnetic head. Typically, for write operations, the preamplifier generates a current waveform that uses a DC current to polarize magnetic elements within the disk and overshoot components to compensate for frequency dependent attenuation in the interconnect between the head and preamp. Conventional pulse-shaping circuitry used for this application uses high voltage to accomplish this task. Here, however, pulse-shaping circuitry is provided which can generate a similar waveform using lower voltage (i.e., about 5V) for this application and others.

Abstract: A clock signal generator comprising an input pin for receiving an oscillating signal and an output pin for providing a clock signal. The clock signal generator also comprises a frequency divider connected between the input pin and the output pin. The frequency divider having a plurality of frequency division factors associated therewith, wherein, in use, the frequency divider is configured to apply one of the plurality of frequency division factors as an in-use frequency division factor to the oscillating signal in order to generate the clock signal. The clock signal generator further comprising a controller configured to periodically replace the in-use frequency division factor with another of the plurality of frequency division factors.

Abstract: Methods, circuits and systems may operate to generate a reset signal at an input reset block and synchronously distribute the reset signal, via a number of pipelined reset blocks, to multiple ports of a core circuit. The reset signal may be transmitted successively to each of the pipelined reset blocks to provide delayed reset signals having delay times. The delay times may be based on locations of the pipelined reset blocks in the reset circuit. On or more of the delayed reset signals may be programmably coupled to one or more ports of the core circuit. Additional methods, circuits, and systems are disclosed.

Abstract: In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a bath mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.

Abstract: An improvement in the security of a logic system by minimising observable features such as the power supply or electromagnetic radiation, so called, “side-channel attacks”. Specifically, the present invention comprises a technique and methods for reducing the ability of an intruder to monitor the relationship between currents in the system and the data in the system through the use of a randomised clock wherein the clock eye diagram is closed and without significant reduction in maximum operating speed compared to the reduction in maximum operating frequency that occurs when using conventional means of additive jitter. A system where the clock eye diagram is completely closed is provably more secure than systems where the clock eye diagram is partially open.

Abstract: A first signal processor performs predetermined signal processing on an input signal to provide a change to at least one of the characteristic values thereof. A second signal processor is provided in the subsequent stage of the first signal processor and performs predetermined signal processing on an output signal from the first signal processor to provide a change to a characteristic value thereof. An amount of change provided to the characteristic value of the signal by the second signal processor is dependent on a power supply voltage. An amount of change provided to the characteristic value of the signal by the first signal processor is configured to be adjustable. A control circuit monitors a power supply voltage supplied to the second signal processor and adjusts in accordance with the power supply voltage the amount of change provided to the characteristic value of the signal by the first signal processor.

Abstract: A pulse width modulation signal controlling apparatus including a signal pin, a core circuit, a setting judging circuit, a signal adjusting and selecting circuit, and a timer circuit is disclosed. The signal pin is connected to a setting device for receiving an external input signal. The setting judging circuit receives and compares a setting signal with a reference value to generate a setting judgment result. The signal adjusting and selecting circuit couples the signal pin to the setting judging circuit and adjusts the external input signal into the setting signal according to the setting device in a first state, and couples the signal pin to the core circuit in a second state. The timer circuit controls the state of the signal adjusting and selecting circuit, wherein the timer circuit sets the signal adjusting and selecting circuit in the first state during a predetermined time period.

Abstract: A flag signal generation circuit includes a first periodic signal detection unit, a second periodic signal detection unit, and a flag signal output unit. The first periodic signal detection unit is configured to detect a change in a level of a first periodic signal and generate a first detection signal. The second periodic signal detection unit is configured to detect a change in a level of a second periodic signal and generate a second detection signal. The flag signal output unit is configured to generate a pre-flag signal from the first and second detection signals, buffer the pre-flag signal in response to a mode register read signal, and output the buffered pre-flag signal as a flag signal.

Abstract: An internal precision oscillator (IPO) is trimmed within a microcontroller integrated circuit. The microcontroller integrated circuit receives a test program into flash memory on the microcontroller integrated circuit from a tester. The microcontroller integrated circuit also receives a reference signal from the tester. The IPO generates a clock signal having a frequency that depends upon a trim value. A general purpose timer on the microcontroller integrated circuit counts the number of cycles of the clock signal during a time period defined by the reference signal and outputs a digital value. A processor on the microcontroller integrated circuit executes the test program, reads the digital output, and adjusts the trim value such that the frequency of the clock signal is calibrated with respect to the reference signal. Test-time on the tester is reduced because the decision making during the frequency trimming process is made by the processor instead of the tester.

Abstract: An impulse waveform generating apparatus comprises an oscillator for generating a reference signal having a center frequency in a frequency band of an impulse to generate, a timing matching circuit for shifting a phase of the reference signal by 90 degrees, a frequency demultiplier for dividing a frequency of the phase shift signal and obtaining a timing signal having a frequency component having a frequency width of an impulse to generate, a memory storing a waveform shape table, a waveform forming section for forming a waveform in synchronism with the timing signal, according to information of a shape table having a predetermined waveform, a low-pass filter for obtaining an envelope signal from an output signal of the waveform forming section, and a waveform generating section for changing an amplitude of the reference signal according to a value of the envelope signal.

Abstract: According to one embodiment, a clock generating circuit includes first and second current generating circuits, first and second voltage generating circuits, first and second comparing circuits, a clock output circuit, a control circuit. The first current generating circuit is configured to generate a first current. The first voltage generating circuit is configured to generate a first voltage which increases or decreases according to a phase of a clock signal as time advances by the first current. The first comparing circuit is configured to compare the first voltage with a first threshold voltage to generate a first comparison result. The second current generating circuit is configured to generate a second current. The second comparing circuit is configured to compare the second voltage with a second threshold voltage to generate a second comparison result.

Abstract: In a particular embodiment, a method includes dynamically adjusting a clock rate to one or more hardware components within a mobile device during a silence period. During the silence period of a video telephony call, when a user of the mobile device is not speaking, the mobile device monitors the background noise and compares detected background noise data to previously detected background noise data to determine changes in the background noise. If the comparison shows that the change in background noise does not result in a change in background noise conditions or does not exceed a difference threshold, the clock rate to certain hardware components may be reduced and portions of certain hardware components may be powered down. The mobile device may send previously stored background noise update packets.

Abstract: A transmitter circuit, which transmits data by using an impulse, has a variable delay circuit and a logic circuit. The variable delay circuit takes a clock as an input, and delays the clock in accordance with the data. The logic circuit takes the clock and an output of the variable delay circuit as inputs, and outputs an impulse by performing a logic operation between the clock and the output of the variable delay circuit.

Abstract: Disclosed herein is a delay circuit for performing one of a charge and a discharge in two stages, and delaying a signal, the delay circuit including an output section configured to output a delayed signal; two power supplies; and a delay inverter; wherein the delay inverter has a first transistor and a second transistor of an identical channel type for one of a first charge and a first discharge, the first transistor and the second transistor being connected in series with each other between the output section and one power supply, and the delay inverter has a third transistor of a different channel type from the first transistor and the second transistor for one of a second charge and a second discharge, the third transistor being connected in parallel with one of the first transistor and the second transistor.

Abstract: A digital synchronous circuit includes a clock generator for generating a reference clock signal, a plurality of delays for delaying the reference clock signal by predetermined different times, a transition varying buffer for controlling input transitions of the clock signals received from the plurality of the delays, a transition controller for controlling operation of the transition varying buffer, and a plurality of registers driven by the clock signals from the plurality of delays.

Abstract: A semiconductor device includes a first signal generator that generates a plurality of second signals having a delay relative to a first signal and having states that change at different timings. A second signal generator generates a third signal having a delay relative to the first signal. A detector detects a delay amount based on the states of the second signals when a state of the third signal changes. The first signal generator and the second signal generator are different from each other in an amount of change in delay relative to a change in an operating state.

Abstract: A device has a battery presence detection system. A line charging pulse signal is applied to a terminal battery detection line, which is connected when the battery is present to a ground line via a resistor and a capacitance. A detector determines whether the battery is connected to the mobile terminal based on detecting whether a line voltage edge or a line voltage level on the terminal battery detection line is present.

Abstract: Methods and apparatus to provide per die temperature programming for thermally efficient integrated circuit (IC) operation are described. In some embodiments, the junction temperature of an IC component is determined, e.g., to reduce power consumption and/or improve performance. Other embodiments are also described.

Abstract: A multimedia processing system for processing a program stream containing a program clock reference information. The system comprises a clock generator, a timer, a modifier, a processing unit, a parser and a compensator. The clock generator generates a clock signal. The timer receives the clock signal and generates a time information. The modifier incorporates a timing reference information into the program stream, wherein the timing reference information is provided according to the time information and the program clock reference information. The processing unit processes the program stream to generate a data stream incorporated with the timing reference information. The parser extracts the timing reference information from the data stream. And, the compensator generates a control signal according to the timing reference information. Wherein the clock generator receives the control signal and adjusts the clock signal.

Abstract: Conductive segments (transmission line conductors) are positioned within a transmission line structure in order to generate multi-cycle microwave pulses. The conductor segments are switchably coupled to one or the other conductor of the transmission lines, inside the transmission line structure. Microwave pulses may be induced in the transmission line by closing the switches in a controlled manner to discharge successive segments, or successive groups of segments, into the transmission lines. The induced pulses travel uninterrupted along the transmission lines in a desired direction to the load. Efficiency of systems and energy delivered to the load in multi-section transmission lines is increased and/or maximized by adjusting the ratio of characteristic impedances associated with the transmission line conductor segments according to an optimum ratio.

Abstract: Various apparatuses, methods and systems for a real time clock are disclosed herein. For example, some embodiments provide a real time clock including a clock generator having a first input connected to a clock signal and a second input connected to a time set signal. The clock generator produces a time change signal at an output of the clock generator. Counters, each adapted to track a different unit of time, are connected to the time change signal. The clock generator is adapted to generate a pulse on the time change signal for each pulse of the time set signal, and to generate separate pulses on the time change signal for consecutive pulses on the clock signal and the time set signal.

Abstract: A clock generator and generating method, and a mobile communication device using the clock generator. A clock generator comprises a first accumulator, an oscillating signal generating circuit and a frequency adjustment circuit. The oscillating signal generating circuit generates a first oscillating signal and adjusts a frequency of the first oscillating signal according to a first overflow output signal of the first accumulator. The frequency adjustment circuit generates a frequency control value according to the first oscillating signal and a reference oscillating signal. The first accumulator accumulates the frequency control value according to the first oscillating signal to generate the first overflow output signal.

Abstract: A clock control circuit includes a first clock buffer configured to toggle a first clock signal when a self-refresh exit command signal is inputted during a self-refresh operation; and a second clock buffer configured to toggle a second clock signal when the self-refresh operation is finished, the second clock being provided to internal circuits.

Abstract: An apparatus and method for reducing interference signals using multiphase clocks. An integrated circuit includes a digital circuit and an analog circuit. The digital circuit includes a derived clock circuit configured to receive a root clock having a frequency D*f, D being a divide factor, to divide the root clock by D, and generate multiphase clocks having N phases. N circuits of the digital circuit are configured to receive a corresponding one of the N phases, with edges of the multiphase clocks being spread over the N phases. The multiphase clocks cause a frequency shift in interference signals generated by reduced periodic peak currents drawn by the N circuits from f to N*f and harmonics thereof. The analog circuit receives an in-band range of signals. A value of N is configured to shift the interference signals outside the in-band range of signals.

Abstract: A method is provided for generating local oscillator signals for a mixer. The method includes providing a reference frequency signal and generating a differential in-phase signal and a differential quadrature signal from the reference frequency signal. The method further includes re-clocking each of the differential in-phase and differential quadrature signals using the reference frequency signal. The re-clocked differential in-phase and differential quadrature signals are then provided as the local oscillator signals for the mixer.

Abstract: The invention relates to an electronic circuit making it possible to extract a clock signal from an incident binary data sequence arriving at a constant rate. The electronic circuit comprises an oscillator (VCO) with voltage-controlled frequency providing a sinusoidal signal, a circuit (R, Cp, RD, I1, I2) for extracting the transition edges of the binary sequence producing a brief pulse at each transition, a sampler (MLT) for tapping off the level of the sinusoidal voltage at the instant of the brief pulse, and an integrator (AOP, R1, C1) for integrating this level in tandem with the successive pulses, the output of the integrator being applied as control voltage to the oscillator with controlled frequency, the output of the oscillator being the desired clock frequency with a slaved phase passing through zero substantially in the middle of the interval between two binary data transitions.

Abstract: An apparatus for generating a pulse having a pulse width substantially independent of process variation in resistive and capacitive values. The apparatus includes a PTAT current source to generate a first current to charge a capacitor to produce a first voltage; a ?VGS current source to generate a second current through a resistor to produce a second voltage V2; a comparator to generate the pulse in response to the first and second voltages; and a circuit to enable the charging and discharging of the capacitor. The use of the distinct current sources (e.g., PTAT and ?VGS) enables the pulse generator to be configured substantially process independent of resistive value. The use of a MOSFET capacitor for the capacitor enables the pulse generator to be made substantially process independent of capacitive value. An additional bandgap current source in parallel with the ?VGS current source reduces the pulse width dependency on temperature.

Abstract: A main (sub) clock circuit comprising a first (second) capacitor, a first (second) current-supply circuit to supply to the first (second) capacitor a first (third) current for charging at a predetermined-current value or a second (fourth) current for discharging at a predetermined-current value, a first (second) charge/discharge-control circuit to output a first (second) control signal for switching between the first (third) current and second (fourth) current which are supplied to the first (second) capacitor from the first (second) current-supply circuit when a voltage across the first (second) capacitor has reached a first (third) reference voltage or second (fourth) reference voltage higher than the first (third) reference voltage, and a first (second) output circuit to output a main (sub) clock according to the first (second) control signal, the first capacitor having one end connected to a first potential, the second capacitor having one end to which the main clock is input.

Abstract: A clock receiver (301) on an integrated circuit (202) includes a programmable AC voltage divider (502) for receiving, through an input capacitor (406), a clock signal (206) from a clock generator (204) off the integrated circuit and for outputting a modified signal that has a reduced voltage swing, an inverter (440) coupled to the programmable voltage divider, and a common mode setting circuit (506), coupled to an input and an output of the inverter. The common mode setting circuit sets and maintains a common mode at the input of the inverter in response to a voltage at the input of the inverter and a voltage at the output of the inverter. The strength of transistors in the common mode tracking circuit tracks the strength of transistors in the inverter such that the common mode at the input to the inverter tracks a trip point of the inverter.

Abstract: A clock gating cell that comprises a latch in communication with an input enable logic and an output logic circuit, wherein the latch includes a pull-up and/or a pull-down circuit at an input node of the output logic circuit and circuitry preventing premature charge or discharge of the output logic circuit input node by the pull-up and/or the pull-down circuit when the clock gating cell is enabled.

Abstract: According to one embodiment, provided is a semiconductor boost circuit including a pump circuit, a switch signal generating circuit and a clock signal generating circuit. The pump circuit receives a clock signal and performs charge pump operation on the basis of the clock signal to boost an input potential to a set potential. The switch signal generating circuit outputs CLK cycle switch signal when a potential output by the pump circuit reaches a first potential greater than the input potential and less than the set potential. The clock signal generating circuit outputs the clock signal having a first frequency if not receiving the CLK cycle switch signal, and, on the other hand, outputs the clock signal having a second frequency greater than the first frequency if receiving the CLK cycle switch signal.