Abstract: The present invention relates to a circuit arrangement and method for controlling power supply in an integrated circuit wherein at least one working parameter of at least one electrically isolated circuit region (10) is monitored, and the conductivity of a variable resistor means is locally controlled so as to individually adjust power supply for each of said at least two electrically isolated circuit regions (10) based on the at least one monitored working parameter. Thereby, a fast and simple control functionality with low area overhead can be provided.

Abstract: A system for testing radio frequency (RF) communications of a device capable of such communications is provided. The system includes a chamber for isolating the device from RF interference, an antenna that is suitable for RF communications with the device wherein the antenna is capable of communications over a range of frequencies, the antenna being located within the chamber, and a digital communication link for providing non-RF communications with the device.

Abstract: An apparatus and method are disclosed for generating one or more clock signals. A clock signal is generated based on pattern signals and a reference clock signal. When the reference clock signal transitions high, the state of a first pattern signal is output, and when the reference clock signal transitions low, the state of a second pattern signal is output. Successive states of the first and second pattern signals, selected according to the reference clock signal, provide the generated clock signal.

Abstract: A clock input filter uses a first programmable low-pass delay element to filter during a low period of an input clock signal and to output a SET signal. The clock input filter uses a second programmable low-pass delay element to filter during a high period of the input clock signal and to output a RESET signal. A latch is set and reset by the SET and RESET signals. The latch outputs a filtered version of the input signal that has the same approximate duty cycle as the input signal. A pair of gates generates a corresponding pair of duty cycle adjusted versions of the input signal. Output multiplexing circuitry is provided to output either the output of the latch, or an increased duty cycle version of the input signal, or a decreased duty cycle version of the input signal, or an unfiltered version of the input signal.

Abstract: Methods and apparatuses provide a clocked digital device having dynamically adjustable operating characteristics. The digital device comprises a digital clock management (“DCM”) circuit in which the amount of delay between receipt of an active edge of a clock signal at the input of the DCM circuit and appearance of an active edge of another clock signal at the output of the DCM circuit depends on a phase adjustment signal applied to the DCM circuit's phase adjust input. A phase adjustment circuit provides the phase adjustment signal to the DCM circuit's phase adjust input for controlling the amount of the delay between the clock signal at the input of the DCM circuit and the clock signal at the output of the DCM circuit.

Abstract: A data output clock generating circuit for a semiconductor memory apparatus includes a rising data output clock generating unit configured to combine a rising clock with a rising clock extraction signal generated in response to a rising output enable signal and a falling clock, to generate a rising data output clock; and a falling data output clock generating unit configured to combine the falling clock with a falling clock extraction signal generated in response to a falling output enable signal and the rising clock, to generate a falling data output clock; wherein the rising data output clock generating unit and the falling data output clock generating unit are independently driven in parallel.

Abstract: A data outputting apparatus of a semiconductor integrated circuit if presented for use in standardizing output timing brought about by different electrical output path lengths. The apparatus includes a data clock signal generating section and a data output section. The data clock signal generating section is configured to use an external clock signal in order to generate a plurality of data clock signals in which output timings of the data clock signals vary depending on a data output mode. The data output section is configured to be controlled by the plurality of data clock signals to output inputted data to the outside through a plurality of data input/output pads that have different path lengths.

Abstract: In one embodiment of the present invention, a clock generator circuit receives a clock signal having a period. The clock signal is employed by a digital circuit that is resident on the same substrate as an analog circuit, the digital circuit generates disturbance climaxes at clock edges that propagate through the substrate to the analog circuit. A clock generator circuit generates a plurality of clock signals, with each clock signal having a unique rate, wherein during a temporal gap, defined by the time between a last disturbance climax and a next sampling time of the clock signal, clock edges of any of the plurality of clock signals are avoided.

Abstract: A semiconductor integrated circuit comprises: a first signal delay circuit including a first precharge element configured to precharge a first node with a leakage current and a first signal output circuit configured to output a first signal; a second signal delay circuit including a second precharge element configured to precharge a second node with a leakage current and a second signal output circuit configured to output a second signal. The first signal delay circuit is configured to discharge the first node via a first discharge element, while the second signal delay circuit precharges the second node via the second precharge element and outputs the second signal. The second signal delay circuit is configured to discharge the second node via a second discharge element, while the first signal delay circuit precharges the first node via the first precharge element and outputs the first signal.

Abstract: A clock signal generation apparatus includes a clock signal generation circuit generating a plurality of clock signals, and a self-test circuit measuring a phase difference of one pair of clock signals. The self-test circuit includes a clock signal selection circuit selecting the pair of clock signals among the plurality of clock signals, a phase detection circuit generating a phase difference pulse signal, a test signal generation circuit generating a test signal having a frequency which is lower than the phase difference pulse signal, and a counter circuit counting the pulse number of the test signal.

Abstract: A clock signal generating circuit includes a main clock buffering unit and a sub clock buffering unit. The main clock buffering unit is capable of generating both a differential clock signal pair and a single clock signal. The main clock buffering unit selectively outputs either the differential clock signal pair or the single clock signal depending upon the frequency of an external clock signal. The sub clock buffering unit receives the output of the main clock buffering unit and generates first and second clock signals. The operation of the sub clock buffering unit depends upon whether the differential clock signal pair or the single clock signal is output by the main clock buffering unit.

Abstract: The present invention is applicable to an electronic device including a master, a slave, a bus coupling the master and the slave and a clock generator for providing a system clock to the master and slave. The clock generator determines whether the received data is correct on a cycle-by-cycle basis. The clock generator suppresses an edge of a next clock cycle of the system clock signal if the data is not to be correct. The clock generator allows the edge of a next clock cycle of the system clock signal if the data is correct.

Abstract: A phase detector includes a plurality of phase detectors located in a phase correction loop, each phase detector configured to receive as input a radio frequency (RF) input signal and an RF reference signal, each of the plurality of phase detectors also configured to provide a signal representing a different phase offset based on the phase difference between the RE input signal and the RF reference signal; and a switch configured to receive an output of each of the plurality of phase detectors and configured to select the output representing the phase offset, that is closest to a phase of an output of an amplifier.

Abstract: A method for generating a variable pulse width signal on an integrated circuit (IC) chip, includes receiving a first clock signal on the IC chip and receiving a second clock signal on the IC chip having a variable delay relative to the first clock signal. A signal having a rising edge triggered by a rising edge of the first clock signal and a falling edge triggered by a rising edge of the second clock signal is output. The output signal is provided to circuitry on the chip, such as a magnetoresistive junction (MTJ) cell of a spin torque transfer magnetic random access memory (STT-MRAM).

Abstract: Methods and apparatus for measuring magnetic field are provided. A resonator having a resonant frequency is that varies as a function of magnetic field is driven with a drive signal, and produces an output that is converted to electrical form. This output is then processed to isolate interference components due to the drive signal and to produce a sense signal. The sense signal is the processed to produce the drive signal. The sense signal is also processed to produce an output representative of the magnetic field.

Abstract: A system and method to establish the lock point of a digital synchronous circuit (e.g., a DLL) at the center of or close to the center of its delay line is disclosed. The synchronous circuit is configured to selectively use either a reference clock or its inverted version as the clock signal input to the delay line based on a relationship among the phases of the reference clock, the inverted reference clock, and a feedback clock may be used during determination of the phase relationship. The selective use of the opposite phase of the reference clock for the input of the delay line results in centralization of the lock point for most cases as well as improvement in the tuning range and the time to establish the initial lock, without requiring an additional delay line.

Abstract: An integrated circuit may include a plurality of circuit sub-systems that include at least one converter circuit operating in respective critical phases and non-critical phases of operation, a clock distribution circuit that has an input for an externally-supplied clock signal that is active during the non-critical phases and inactive during the critical phases, and a clock generator to generate an internal clock signal to the converter circuit that is active when the external-supplied clock signal is inactive.

Abstract: A control signal generation circuit includes a pulse signal generator configured to delay a column control signal by delay times different from each other and to generate first and second pulse signals, a reset signal generator configured to transfer alternatively the first and second pulse signals as a reset signal in response to a write/read flag signal, and a write-enable signal generator configured to generate a write-enable signal from the first pulse signal in response to the write/read flag signal.

Abstract: There is provided a small-size, low-power-consumption intermittent operation circuit capable of obtaining an output waveform having a rapid rise and fall. The intermittent operation circuit includes an active circuit (106), a first control signal generation circuit (101) for generating a first control signal (S1) for controlling the operation start and the operation end of the active circuit (106), a second control signal generation circuit (102) for generating a second control signal (S2) causing the active circuit (106) to perform ringing vibration and controlling the frequency and the amplitude value of the ringing vibration, and a timing adjusting circuit (103) for adjusting the input timing of the first and the second control signal (S1, S2) into the active circuit (106) so that the ringing vibration and the safety vibration are outputted continuously from the active circuit (106).

Abstract: Disclosed is an SSC controller that exercises control to supply a control signal to a phase interpolator which receives an input clock signal and varies the phase of an output clock signal in accordance with the control signal, and to frequency-modulate the output clock signal. In an SSC controller, a counting operation control circuit outputs a counting operation control signal that controls count enable and disable. A p-counter receives a frequency-divided clock signal from a frequency divider and counts the signal when the counting operation control signal from the counting operation control circuit indicates count enable. Upon counting up to a predetermined first value, the counting operation control circuit generates a first output signal and sets its count value to zero. When the counting operation control signal indicates count disable, the p-counter stops counting.

Abstract: A clock generating circuit generates a high frequency clock having a constant duty and the same period as that of an external clock. A clock generating circuit generates a clock signal (hereinafter “the clock”) used for outputting a data signal to a data pin. The clock generating circuit includes at least a dividing portion and a clock generating portion. A dividing portion divides an internal clock signal (hereinafter “the internal clock”) generated based on an external clock signal (hereinafter “the external clock”) and outputs a plurality of divided clock signals (hereinafter “the divided clocks”). The clock generating portion performs a predetermined logical operations combining the divided clocks to generate the clock having a constant duty and the same period as the external clock.

Abstract: A method for correcting gain imbalance error, phase imbalance error and DC offset errors in a transmitter having an OFDM-based I/Q modulator is disclosed. The method employs a compensator prior to the I/Q-modulator to compensate for the gain and phase imbalance and DC offset. The compensator is efficiently updated with the estimated values of gain and phase imbalance and DC offsets obtained by performing the DFT operation in the digital baseband domain while sending a pair of orthogonal test tones to the modulator's inputs from a digital baseband chip, then down converting the RF modulated signal through a nonlinear device and a bandpass filter to a baseband signal, and finally sampling it using an A/D. The delay mismatch, which is mainly generated by lowpass filters between the I and Q branches, is also minimized in this method.

Abstract: According to a spurious pulse generator of this invention, integrating circuits are provided at a plurality of stages for carrying out integrating operations about time and outputting a spurious pulse, the integrating circuits being constructed to input a voltage value for controlling a crest value which is a peak swing of the spurious pulse to an amplifier forming an integrating circuit at a most upstream stage when a switching element is ON, and to input a constant voltage value when the switching element is OFF. As a result, the voltage value before ON-state and after ON-state of the switching element does not change but remains a constant voltage value, thereby obtaining a desired spurious pulse.

Abstract: A pulse generator circuit. The pulse generator circuit includes a precharge circuit coupled to receive a clock signal alternating between a first logic level and a second logic level, a storage circuit having a storage node, wherein the precharge circuit is configured to precharge the storage node when the clock signal is at the first logic level, a logic circuit having an output, a first input node coupled to receive the clock signal, and a second input node coupled to the storage node and configured to produce a pulse at the second logic level responsive to the clock signal transitioning to the second logic level, and a discharge circuit configured to discharge the storage node at a predetermined delay time subsequent to the clock signal transitioning to the second logic level, wherein the output of the logic circuit transitions to the first logic level responsive to discharging the storage node.

Abstract: In a synchronous semiconductor device (250), an input/output control circuit is formed of a clock input I/O (260), a clock control signal input I/O (270) and a signal change detection circuit (280). The clock input I/O (260) includes a first input buffer (264) having a large threshold, a second input buffer (266) having a small threshold and an input selector (268). The signal change detection circuit (280) controls the input selector (268) so that a first input from the first input buffer (264) is normally selected and a second input from the second input buffer (266) is temporarily selected only when the signal change detection circuit (280) detects that a logic level of a clock control signal (279) is changed from a non-activated level to an activated level.

Abstract: A central reference clock is placed in a substantially middle chip of a 3-D chip-stack. The central reference clock is distributed to each child chip of the 3-D chip-stack, so that a plurality of clocks is generated for each individual chip in the 3-D-stack in a synchronous manner. A predetermined number of through-silicon-vias and on-chip wires are employed to form a delay element for each slave clock, ensuring that the clock generated for each child chip is substantially synchronized. Optionally, an on-chip clock trimming circuit is embedded for further precision tuning to eliminate local clock skews.

Abstract: A technique to mitigate noise spikes in an electronic circuit device such as an integrated circuit. The clock frequency of a clock signal used by the electronic circuit is controlled such that instantaneously large changes to the clock frequency are avoided by use of a frequency filter that is capable of generating frequency ramps having a linear slope which is used as a feedback signal in a digital phase-locked loop clock circuit in lieu of a discrete, stair-stepped feedback control signal.

Abstract: A duty cycle correction circuit includes a phase splitter configured to control a phase of a DLL clock signal to generate a rising clock signal and a falling clock signal, a clock delay unit configured to delay the rising clock signal and the falling clock signal in response to control signals to generate a delayed rising clock signal and a delayed falling clock signal, a duty ratio correction unit configured to generate a correction rising clock signal and a correction falling clock signal that toggle in response to an edge timing of the delayed rising clock signal and the delayed falling clock signal, and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal to generate the control signals.

Abstract: The described embodiments provide a circuit that can be configured as a pulse generator or as an oscillator. The circuit includes a pulse generator circuit and a test circuit that is coupled to the pulse generator circuit. In the described embodiments, an disable signal is coupled to the test circuit. When the disable signal is asserted, the test circuit is disabled, and the pulse generator circuit outputs pulses of a predetermined duration. In contrast, when the disable signal is deasserted, the test circuit is enabled, and the pulse generator circuit outputs an oscillating signal.

Abstract: Described herein is the method and apparatus for determining frequency of an oscillator coupled with one or more analog devices, and for determining within-die or across-die variations in an analog property associated with the one or more analog devices, the determining based on the oscillator frequency. The analog property includes output signal swing, bandwidth, offset, gain, and delay line linearity and range. The one or more analog devices include input-output (I/O) buffer, analog amplifier, and delay line. The method further comprises updating a simulation model file based on the determining of the within-die and/or across-die variations of the analog property.

Abstract: A driving controller for use in stabilizing transient voltages from power supplies is presented. The driving controller includes a first pulse generator, a second pulse generator, and a control signal generator. The first pulse generator is configured to generate a power-up pulse signal including a pulse activating at a time of terminating a power-up period. The second pulse generator is configured to generate a detection pulse signal including a pulse that is being active from a time when an internal voltage reaches a predetermined level. The control signal generator is configured to generate an operation control signal, which controls a driving controller activating the internal voltage, in response to the power-up pulse signal and the detection pulse signal.

Abstract: Clock generation circuitry is arranged in stages so as to convert a slow slew rate input signal into a high slew rate clock signal in a low power environment. Each stage includes a capacitor and an inverter, both fed by respective current mirrors. The capacitor is trickle-charged through its current mirror, and charge of the capacitor is dumped onto an output of the stage at a controlled timing. Two or more such stages may be provided, so as to improve the slew rate of both of the leading and trailing edges of the clock signal, and also so as to provide a convenient source of timing for dumping charge of each capacitor. Each stage might also include a diode switchably connected across the capacitor, so as to discharge the capacitor at appropriate timings, to reduce interference on succeeding stages that might otherwise be caused by residual charge on the capacitor.

Abstract: A setup/hold time control circuit includes a reference signal output unit that sets any one of multiple ports as a reference port and buffers a signal input through the reference port to output as a reference signal. The setup/hold time control circuit also includes a plurality of comparative signal output units that set the remaining ports as comparative ports. The comparative signal output unit synchronizes signals that are input from the comparative ports with the reference signal and outputs the signals as internal signals. The setup/hold time control circuit improves high speed operation of a semiconductor memory device by improving upon the setup/hold time difference between multiple ports.

Abstract: The timing of output signals can be controlled by coupling a digital signal through a signal distribution tree having a plurality of branches extending from an input node to respective clock inputs of a plurality of latches. A phase interpolator is included in a signal path common to all of the branches, and a respective delay line is included in each of the branches. Each of the latches couples a signal applied to its data input to an output terminal responsive to a transition of the digital signal applied to its clock input. The delay lines are adjusted so that the latches are simultaneously clocked. The delay of the phase interpolator is adjusted so that the signals are coupled to the output terminals of the latches with a predetermined timing relationship relative to signals coupled to output terminals of a second signal distribution tree.

Abstract: A pulse generator circuit that outputs pulses having a predetermined shape from an output terminal based on a start signal includes a timing generator circuit that generates (n+1) signals (n is an integer greater than or equal to 2), the phases of which sequentially change at predetermined time intervals from the point when the phase of the start signal changes, first and second power supplies that supply predetermined potentials, n impedance devices, and a switching circuit that connects the output terminal to the first or second power supply in a predetermined order according to the value of a logic function based on the (n+1) signals via the corresponding impedance device.

Abstract: External frequency adjustment methods and systems are provided. First, an external frequency of an electronic device is increased from an initial frequency until a processing unit fails to properly operate, and a maximum first frequency value at which the processing unit can properly operate is recorded as the external frequency. The electronic device is enabled to reboot, and at least one peripheral device is initiated and operated according to the first frequency value. It is determined whether the peripheral device is properly operating at the first frequency value. When the peripheral device can not properly operate at the first frequency value, the electronic device is enabled to reboot, the first frequency value is subtracted by a predefined value to obtain a second frequency value, and the second frequency value is set as the external frequency, wherein the second frequency value is the maximum frequency value at which the processing unit can properly operate.

Abstract: An internal precision oscillator (IPO) is trimmed within a microcontroller integrated circuit. The microcontroller integrated circuit receives a test program into flash memory on the microcontroller integrated circuit from a tester. The microcontroller integrated circuit also receives a reference signal from the tester. The IPO generates a clock signal having a frequency that depends upon a trim value. A general purpose timer on the microcontroller integrated circuit counts the number of cycles of the clock signal during a time period defined by the reference signal and outputs a digital value. A processor on the microcontroller integrated circuit executes the test program, reads the digital output, and adjusts the trim value such that the frequency of the clock signal is calibrated with respect to the reference signal. Test-time on the tester is reduced because the decision making during the frequency trimming process is made by the processor instead of the tester.

Abstract: A burst order control circuit includes a burst signal generating unit configured to receive a seed column address and to generate a first rising burst signal, a second rising burst signal, a first falling burst signal and a second falling burst signal in response to the seed column address, and a repeater unit configured to transfer the first rising burst signal, the second rising burst signal, the first falling burst signal and the second failing burst signal to a pipe latch.

Abstract: Methods and systems are provided for modifying a pulse sequence. In one embodiment, a determination is made whether an estimated peripheral nerve stimulation (PNS) associated with a pulse sequence exceeds a PNS limit. If the estimated PNS exceeds the PNS limit, a slew rate associated with one or more axes of the pulse sequence may be reduced and the maximum gradient amplitudes for each axis of the pulse sequence may be adjusted. In one embodiment, adjustment of the maximum gradient amplitudes or local slew rate may be based upon a cost analysis performed on the pulse sequence.

Abstract: A programmable delay clock buffer circuit, preferably implemented in a single IC, includes a clock circuit and a plurality of variable delay lines. The clock circuit receives an input clock and is clock feedback signal and generates an intermediate clock. Each of the delay lines is configured to receive the intermediate clock and to receive at least one delay control input. A first variable delay line of the plurality is configured to generate, based on a first delay control input, a first delay from the intermediate clock to produce a clock output signal. A second variable delay line of the plurality is configured to generate, based on a second delay control input, a second delay from the intermediate clock to produce a clock feedback signal. A method of distributing clock with through programmable delay lines is also presented.

Abstract: Duty cycle correction (DCC) methods and circuits are provided for improving the quality of clock signals and reducing or eliminating duty cycle distortion. The performance of known duty cycle correction circuits, such as cross-coupled inverter or transmission gate DCC circuits, may be improved by coupling two or more DCC circuits in series to form a multi-stage DCC circuit. In multi-stage DCC circuits, the performance and sizing requirements imposed on the individual circuit stages are reduced as compared to single-stage DCC circuit implementations. Good duty cycle correction performance over a wide range of input signal duty cycles may therefore be ensured regardless of the performance of individual stages. Clocked-CMOS DCC circuits are also presented, the circuits operative to produce duty cycle corrected output signals while consuming minimal current and power. The clocked-CMOS DCC circuits include as few as four transistors, and are operative over wide ranges of input signal duty cycles.

Abstract: There is provided a jitter injection apparatus that generates an output signal having an injected jitter. The jitter injection apparatus includes a first oscillator that generates a first periodic signal, a second oscillator that generates a second periodic signal having a period different from that of the first periodic signal, and a switching section that switches which of the first periodic signal and the second periodic signal is output at every predetermined timing and outputs the switched periodic signal as the output signal.

Abstract: A system and method to establish the lock point of a digital synchronous circuit (e.g., a DLL) at the center of or close to the center of its delay line is disclosed. The synchronous circuit is configured to selectively use either a reference clock or its inverted version as the clock signal input to the delay line based on a relationship among the phases of the reference clock, the inverted reference clock, and a feedback clock (generated at the output of the delay line). A delayed version of the feedback clock may be used during determination of the phase relationship. The selective use of the opposite phase of the reference clock for the input of the delay line results in centralization of the lock point for most cases as well as improvement in the tuning range and the time to establish the initial lock, without requiring an additional delay line.

Abstract: A frequency-control circuit, which is configured to receive a first signal having a first untuned frequency from a first oscillator, and to alter one or more pulses of the first signal to tune an output frequency of an output clock signal to have an average frequency at the desired target frequency. In some embodiments, the frequency-control circuit receives a signal from a single oscillator to generate a calibrated, precise, and temperature-stable clock.

Abstract: An adjustable chaotic signal generator using pulse modulation for UWB communications, and a chaotic signal generating method thereof are provided. The chaotic signal generator for UWB communications includes a plurality of pulse generators which generates pulses of different frequencies; at least one combiner which combines the pulses generated at the pulse generators; and a plurality of local oscillators which receives signals from the combiner, respectively, and generates a chaotic signal by increasing the received signals to different frequency bands. Accordingly, a plurality of users can conduct the radio communications in a specific wireless communication range at the same time by generating the chaotic signal that can be split to the multiple channels. Also, the chaotic signal generator is structured using devices integratable on an integrated circuit.

Abstract: In a method of generating clock signals for a level-sensitive scan design latch, at least one test input signal is transmitted to a plurality of splitter leaves. Once the test input signal is stabilized at each of the splitter leaves, generating a shaped oscillator clock signal having a predetermined pattern of pulses from a central root is generated. At the plurality of splitter leaves, the test input signal is logically combined with the shaped oscillator clock signal, thereby generating a first latch clock signal and a second latch clock signal. The logically combining action includes applying a delay of less than one clock cycle to the shaped oscillator clock signal to generate a delayed oscillator clock signal; logically combining the delayed oscillator clock signal with a second signal so as to generate the first latch clock signal; and logically combining the shaped oscillator clock signal with a third signal so as to generate the second latch clock signal.

Abstract: A clock generating apparatus includes a clock generator and a controllable delay line. The clock generator receives an external clock signal and generates multiple clock signals having different phases by delaying the external clock signal. The controllable delay line receives one of the multiple clock signals as a first clock signal and delays the first clock signal by a first interval in response to an externally applied control signal. The delayed first clock signal is input to the clock generator.

Abstract: A system includes an input device, an output device, a mechanical chassis, a printed circuit board, and a semiconductor device. The semiconductor device includes a mechanical package, and a semiconductor die. The semiconductor die includes a semiconductor layer, a plurality of metal layers, a clock distribution network that distributes a clock signal within the die, and an economy precision pulse generating circuit. The economy precision pulse generating circuit includes a pre-charge circuit, a gate-to-the-partial-jam-latch-keeper circuit, a partial-jam-latch-keeper circuit, and a pull-down-against-the-up-keeper circuit. A source clock signal is derived from the clock signal. The source clock signal is provided to a first input of a logical AND circuit, the pre-charge circuit, and the gate-to-the-partial-jam-latch-keeper circuit. A common storage node is connected to a second input of the logical AND circuit. The logical AND circuit outputs an output pulse.

Abstract: A system includes an input device, an output device, a mechanical chassis, a printed circuit board, and a semiconductor device. The semiconductor device includes a mechanical package, and a semiconductor die. The semiconductor die includes a semiconductor layer, a plurality of metal layers, a clock distribution network that distributes a clock signal within the die, and an economy precision pulse generating circuit. The economy precision pulse generating circuit includes a pre-charge circuit, a gate-to-the-partial-jam-latch-keeper circuit, a partial-jam-latch-keeper circuit, and a pull-down-against-the-up-keeper circuit. A source clock signal is derived from the clock signal. The source clock signal is provided to a first input of a logical AND circuit, the pre-charge circuit, and the gate-to-the-partial-jam-latch-keeper circuit. A common storage node is connected to a second input of the logical AND circuit. The logical AND circuit outputs an output pulse.

Abstract: An apparatus for generating a pulse having a pulse width substantially independent of process variation in resistive and capacitive values. The apparatus includes a PTAT current source to generate a first current to charge a capacitor to produce a first voltage; a ?VGS current source to generate a second current through a resistor to produce a second voltage V2; a comparator to generate the pulse in response to the first and second voltages; and a circuit to enable the charging and discharging of the capacitor. The use of the distinct current sources (e.g., PTAT and ?VGS) enables the pulse generator to be configured substantially process independent of resistive value. The use of a MOSFET capacitor for the capacitor enables the pulse generator to be made substantially process independent of capacitive value. An additional bandgap current source in parallel with the ?VGS current source reduces the pulse width dependency on temperature.