Abstract: The present invention provides a voltage boost driving circuit for LED backlight, which includes a first power input port, a second power input port, an LED light bar, a positive boost circuit, a negative boost circuit, and a luminance controlling circuit configured for controlling the luminance of the LED light bar; the first and second power input ports are respectively connected to the positive and negative poles of an external power supply; the positive boost circuit is connected between the first power input port and the positive pole of the LED light bar; the second power input port is connected to the ground; the negative boost circuit is connected to the positive boost circuit via the luminance controlling circuit, an output port of the negative boost circuit is connected to the negative pole of the LED light bar. An LCD device is further provided.

Abstract: A circuit for the compensation of an offset voltage in a measurement amplifier and/or of a DC-signal component contained in a measurement signal is provided. The circuit comprises a measurement-signal terminal for the measurement signal. The non-inverting input of the measurement amplifier serves for the feeding in of an AC-signal component of the measurement signal via a first capacitor. Additionally, the circuit contains a second amplifier for the addition of the DC-signal component in the measurement signal and of a signal corresponding to the negative offset voltage and to the negative DC-signal component, and a unit arranged at the input end or output end of the measurement amplifier for subtraction of an output signal of the second amplifier from the AC-signal component of the measurement signal.

Abstract: A slicer apparatus and a calibration method thereof are provided. A differential reference signal pair used for performing an error slicing operation is adjusted, so as to calibrate an offset voltage of the slicer apparatus.

Abstract: In accordance with embodiments of the present disclosure, a control circuit may be configured to, responsive to an indication to switch between gain modes of a signal path having an analog path portion and a digital signal path portion, switch a selectable analog gain of the analog path portion between a first analog gain and a second analog gain, switch a selectable digital gain of the digital signal path portion between a first digital gain and a second digital gain, wherein the product of the first analog gain and the first digital gain is approximately equal to the product of the second analog gain and the second digital gain, and control an analog response of the signal path to reduce the occurrence of audio artifacts present in the output signal as a result of the switch between gain modes of the signal path. A signal path may have an analog path portion and a digital signal path portion.

Abstract: An apparatus for adjusting an internal voltage includes a device characteristic detection circuit which detects a device characteristic, compares the device characteristic with an external clock, and generates a comparison signal, and an internal voltage adjustment circuit which receives an adjustment code generated based on the comparison signal, adjusts a level of an internal voltage, and generates a level-adjusted internal voltage.

Abstract: An electronic circuit arrangement for receiving low-frequency electromagnetic waves is proposed, having an inductor (L) acting as an antenna for generating a received signal, having a first receiver (2), connected to the inductor (L), for decoding a first component of the received signal and having a second receiver (3), connected to the inductor (L), for decoding a second component of the received signal, wherein at least the second receiver (3) is connected to the inductor (L) via an attenuator element (4) having adjustable attenuation, wherein at least one adjustment signal generation circuit (5, 6) is provided for generating an adjustment signal corresponding to a voltage of the received signal which is fed to the attenuator element (4) for adjusting the attenuation.

Abstract: A gain asymmetry characterizing circuit for determining characteristics of gain asymmetry possessed by a transmitter includes a baseband loopback path, a test signal generating unit and a gain asymmetry measuring unit. The baseband loopback path is coupled to a baseband node on a first transmission path of the transmitter. The test signal generating unit is arranged to generate a first differential baseband test signal pair to the first transmission path. The first differential baseband test signal pair includes a first baseband signal and a second baseband signal. During a first period, the first baseband signal and the second baseband signal are fed into a positive input node and a negative input node of the first transmission path, respectively. During a second period, the second baseband signal and the first baseband signal are fed into the positive input node and the negative input node of the first transmission path, respectively.

Abstract: A decoupling capacitor circuit design facilitates high operational frequency without sacrificing area efficiency. In order to disassociate the sometimes opposing design criteria of high operational frequency and area efficiency, a p-channel field effect transistor (PFET) and an n-channel field effect transistor are connected in a half-cross-coupled (HCC) fashion. The HCC circuit is then supplemented by at least one area efficient capacitance (AEC) device. The half-cross-coupled transistors address the high frequency design requirement, while the AEC device(s) address the high area efficiency requirement. The design eliminates the undesirable trade-off between operating frequency and area efficiency inherent in some conventional DCAP designs.

Abstract: A switch-mode DC-DC voltage converter including a boost stage in the form of a charge pump and a buck stage. Control circuitry is provided that enables the operation of the buck stage while the charge pump stage is also enabled, followed by disabling of the charge pump stage as the input voltage and output voltage increase. The buck converter stage is constructed so that it regulates the output voltage at a voltage above that which disables the charge pump stage. Conduction losses in the main current path, due to the necessity of a power FET or other switching device, are avoided.

Abstract: The invention is an internal power voltage generating circuit, adjusted such that an internal power voltage becomes the reference voltage. The internal power voltage generating circuit further includes: a charge share circuit, including a charging capacitor, an initial voltage adjusting circuit and a charge reset circuit. The charging capacitor is connected to a differential amplifier via a switch circuit, and is charged by charges of a control voltage. The initial voltage adjusting circuit adjusts and applies an initial voltage to the charging capacitor. The charge reset circuit discharges the charging capacitor. When the internal power voltage is lower than a reference voltage, the charging capacitor having the initial voltage is connected to the differential amplifier, and the charges of the control voltage are transferred to the charging capacitor during a transfer period.

Abstract: Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry.

Abstract: An electronic circuit for driving a resonator of a MEMS-type resonator device is provided. The resonator includes a mass connected to a spring and a damping element, an actuation element for actuating the mass via an actuation signal, and a detection element for detecting motion of the mass. The electronic circuit includes a conversion means connected to the detection element to supply a mass oscillation derivative signal, a means of comparing the derivative signal amplitude and a reference amplitude for supplying a control signal, and a decision unit for supplying a digital actuation signal. The actuation signal includes rectangular pulses determined on the basis of the derivative signal and of the control signal to adapt the mass oscillation amplitude according to the reference amplitude.

Abstract: A latching level shifter coupled to a first power supply voltage is driven by a logic circuit coupled to a second power supply voltage. The latching level shifter is driven in a first mode to store a state based on an input signal received by the logic circuit, the first and second power supply voltages are set at first and second initial voltage levels. The latching level shifter is driven in a second mode subsequent to the first mode, the first power supply voltage is set to an intermediate voltage level. The latching level shifter is driven in a high voltage protection mode to produce an output voltage based on the state, the first power supply voltage is set to a final voltage level that is greater than a final voltage level of the second power supply voltage. The high voltage protection mode is subsequent to the second mode.

Abstract: Reducing output voltage ripple of power supplies. In some embodiments, an electronic circuit may include a first node configured to receive an input signal proportional to an output voltage produced by a power supply, a second node configured to receive a reference voltage configured to alternate between two voltage values during operation of the power supply, and a third node configured to output an enabling signal configured to control the operation of the power supply in response to a comparison between the input signal and the reference voltage. In other embodiments, a method may include turning on a power supply in response to a falling ripple being smaller than a first reference voltage value, and turning off the power supply in response to a rising ripple being greater than a second reference voltage value, where the second reference voltage value is smaller than the first reference voltage value.

Abstract: A high voltage tolerant I/O circuit of an electronic device is disclosed, including a voltage reducing circuit, a first node, a first transistor, a second transistor, and a control logic. The voltage reducing circuit is coupled with a signal pad and utilized for generating a reduced voltage according to an external voltage. When an internal voltage generated by an internal circuit of the electronic device is greater than the reduced voltage, the first node outputs the internal voltage as a first voltage. When the internal voltage is less than the reduced voltage, the first node outputs the reduced voltage as the first voltage. The first transistor is coupled with the signal pad and the first node. The second transistor is coupled with a second terminal of the first transistor and a fixed-voltage terminal. The control logic operates according to the first voltage to control switching operations of the second transistor.

Abstract: A circuit having a first, second, and third capacitor. Capacitor plates of the capacitors are connected to a first circuit node. The circuit supplies a first time-dependent voltage to the first capacitor, a second time-dependent voltage to the second capacitor, and a third time-dependent voltage to the third capacitor. The first and second voltages are clocked in antiphase. The second and third voltages are clocked in phase. The circuit has an amplifier, a synchronous demodulator, and a comparator. Inputs of the amplifier are connected to the first circuit node and ground. The synchronous demodulator alternately applies an output signal of the amplifier to inputs of the comparator, synchronously with the clock frequency of the first voltage. The circuit generates a control value dependent on an output of the comparator. The circuit changes amplitudes of the first and third voltage and/or the second voltage dependent on the control value.

Abstract: Methods and apparatus for a dynamic bias generator are provided. In an example, a dynamic bias generator for a voltage regulator can include a slope generator and a peak detector coupled to the slope generator. In certain examples, the slope generator and the peak detector can receive a representation of output current of the voltage regulator and can adjust a bias control voltage at an output of the peak detector in response to a change in the output current of the voltage regulator.

Abstract: Various embodiments of circuits configured to improve second order harmonic distortion of Metal Oxide Semiconductor (MOS) transistors operating in linear region are provided. In one embodiment, a circuit includes an averaging circuit configured to average signals at a drain and a source of a MOS transistor and provide the averaged signal to a gate of the MOS transistor, and one or more current sources coupled with the gate; the circuit is configured to vary voltage at the gate so as to vary a resistance of the MOS transistor. The averaging circuit comprises a first MOS circuit coupled between the drain and the gate, a first capacitor coupled in parallel to the first MOS circuit between the drain and the gate, a second MOS circuit coupled between the source and the gate, and a second capacitor coupled in parallel to the second MOS circuit between the source and the gate.

Abstract: A receiver circuit for a differential input signal, may include a divider bridge having first and second ends, a midpoint therebetween, and intermediate points on either side of the midpoint. The divider bridge is coupled to receive the differential input signal at the first and second ends. A current generator is coupled to the divider bridge and configured to generate compensation currents associated respectively with components of the differential input signal. The divider bridge is configured to receive the compensation currents respectively at the intermediate points, and generate a compensated differential signal between the intermediate points.

Abstract: An equalizer circuit includes an input terminal, a pull-up driving unit suitable for pull-up driving an output terminal based on a signal of the input terminal, a pull-down driving unit suitable for pull-down driving the output terminal, and a capacitor connected between the input terminal and the output terminal.

Abstract: Methods, systems, and structures for generating a target reference voltage are provided. A circuit includes a voltage adjuster, a switch, and a current source. The switch selectively connects the current source to circuit paths in the voltage adjuster. A first of the circuit paths incrementally decreases the target reference voltage with respect to the input voltage. A second of the circuit paths incrementally increases the target voltage with respect to the input voltage.

Abstract: A bootstrap circuit of which the capacitance of a bootstrap capacitor is small and which requires a shorter precharge period is provided. The bootstrap circuit includes transistors M41 and M42, capacitors BSC1 and BSC2, an inverter INV41, and keeper circuits 43 and 44. A signal OSG with a high voltage is generated from an input signal OSG_IN. As the signal OSG_IN is made a high level, a node SWG is made a high level by BSC1. After a signal BSE1 is made a high level and the node SWG is made a low level by the keeper circuit 44, a signal BSE2 is made a high level. By the capacitance coupling of BSC2, a voltage of an output terminal 22 increases.

Abstract: A method for dealing with high inrush current when voltage is applied to mixed voltage logic integrated circuits is disclosed. A depletion N-Channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or junction Field Effect Transistor (JFET) is added to a linear voltage regulator in mixed voltage logic integrated circuits. The Field Effect Transistor (FET) is utilized to allow the core voltage to come up with Input/Output voltage prior to turn-on of linear voltage regulator. Turn-on state of FET allows the core voltage to rise with Input/Output voltage until the FET threshold is reached across the gate. When threshold is reached, the FET turns off to allow linear voltage regulator turn on and take over supply power.

Abstract: Methods and apparatus for lowering the capacitance of an interconnect, are disclosed. An example apparatus may include an interconnect formed in at least one integrated circuit and configured to pass a signal through at least a portion of the at least one integrated circuit. The apparatus may include a transmitter to operate at a first voltage and a second voltage, and to output to an end node of the interconnect a reduced swing signal ranging from the first voltage to a third voltage. The third voltage may be between the first and second voltages, and the reduced swing signal may operate to reduce a capacitance of the interconnect when compared to operating the transmitter at the second voltage. Additional apparatus and methods are disclosed.

Abstract: The application discloses a voltage regulation method, and a corresponding HPM, chip, and chip system. The method is used to regulate a working voltage of the chip, which includes an AVS module and at least one HPM. The method includes: outputting, by the AVS module, a clock signal to the HPM; generating, by the HPM, a corresponding pulse signal according to the clock signal and at least performing first delaying for the pulse signal to acquire a first actual output value and performing second delaying for the pulse signal to acquire a second actual output value; and fitting, by the AVS module, the first and second actual output values at least according to weights of the first and second actual output values to acquire a fitting output value and determine, by comparing the fitting output value with a predetermined reference value, whether to regulate the working voltage of the chip.

Abstract: A receiver circuit for a differential input signal, may include a divider bridge having first and second ends, a midpoint therebetween, and intermediate points on either side of the midpoint. The divider bridge is coupled to receive the differential input signal at the first and second ends. A current generator is coupled to the divider bridge and configured to generate compensation currents associated respectively with components of the differential input signal. The divider bridge is configured to receive the compensation currents respectively at the intermediate points, and generate a compensated differential signal between the intermediate points.

Abstract: A method for amplifying an echo signal, in which an analog echo signal suitable for detection of a vehicle's surroundings is amplified by a gain dependent on the transit time of the echo signal, the analog echo signal being amplified by an amplifier having a plurality of outputs, each having a different gain, and a downstream A/D converter having a time-variable reference voltage. In the process, there is a switch between the different outputs of the amplifier at predefined switching points in time, and the reference voltage of the A/D converter varies over time between the switching points in time in such a way that the echo signal is present at the output of the A/D converter with a transit time-dependent total gain having a predefined characteristic.

Abstract: Systems and methods are provided to regulate a supply voltage of a load circuit. For example, a system includes a voltage regulator circuit that includes a passgate device. The system includes a passgate strength calibration control module which is configured to (i) obtain information which specifies operating conditions of the voltage regulator circuit, (ii) access entries of one or more look-up tables using the obtained information, (iii) use information within the accessed entries to determine a maximum load current that could be demanded by the load circuit under the operating conditions specified by the obtained information, and to predict a passgate device width which is sufficient to supply the determined maximum load current, and (iv) set an active width of the passgate device according to the predicted passgate device width.

Abstract: A voltage clamp circuit includes a power supply, a first element connected with the power supply to output a constant current, a third element configured to allow a current to pass through when a voltage of a predetermined value or more is applied; and a second element configured to output a voltage according to a voltage generated by the first and third elements.

Abstract: An integrated circuit may include a digital output port including a buffer stage that includes subassemblies of MOSFET transistors. One subassembly may include two pull-up transistors having sources connected to a common high voltage, and having drains connected to a common node connected to the output terminal. Another subassembly may include pull-down transistors having sources connected to a common low voltage, and having drains connected to the common node. The pull-up and pull-down transistors are formed in a thin semiconductor layer of an FDSOI substrate. The substrate may include a thick semiconductor layer and an oxide layer separating the thin and thick semiconductor layers. Areas of the thick semiconductor layer facing the pull-up and pull-down transistors may be connected to a circuit configured to vary a threshold voltage of the pull-up and pull-down transistors.

Abstract: Systems and methods are provided to regulate a supply voltage of a load circuit. For example, a system includes a voltage regulator circuit that includes a passgate device. The system includes a passgate strength calibration control module which is configured to (i) obtain information which specifies operating conditions of the voltage regulator circuit, (ii) access entries of one or more look-up tables using the obtained information, (iii) use information within the accessed entries to determine a maximum load current that could be demanded by the load circuit under the operating conditions specified by the obtained information, and to predict a passgate device width which is sufficient to supply the determined maximum load current, and (iv) set an active width of the passgate device according to the predicted passgate device width.

Abstract: A buffer circuit includes a buffering unit suitable for buffering an input signal and outputting an output signal and a feedback control unit suitable for adjusting a slew rate of the input signal in response to the output signal.

Abstract: The application discloses a voltage regulation method, and a corresponding HPM, chip, and chip system. The method is used to regulate a working voltage of the chip, which includes an AVS module and at least one HPM. The method includes: outputting, by the AVS module, a clock signal to the HPM; generating, by the HPM, a corresponding pulse signal according to the clock signal and at least performing first delaying for the pulse signal to acquire a first actual output value and performing second delaying for the pulse signal to acquire a second actual output value; and fitting, by the AVS module, the first and second actual output values at least according to weights of the first and second actual output values to acquire a fitting output value and determine, by comparing the fitting output value with a predetermined reference value, whether to regulate the working voltage of the chip.

Abstract: The performance, thermal and power management system is configured to perform DVFS calibration, temperature compensation adjustment, aging calibration, and DC offset calibration in an IC. The initial voltage supplied to the IC may be set to an initial value which takes chip-to-chip process variations into account and then dynamically adjusted according to temperature variations, DC offset and/or aging effects. Therefore, the performance, thermal and power management system may achieve optimized thermal and power performance of the IC.

Abstract: A transmitter may include a first path configured to receive a signal, to attenuate the low frequency components of the signal, and to output the low frequency component attenuated signal. The transmitter may further include a second path configured to receive the signal, to amplify the signal, and to output the amplified signal. The transmitter may also include a node coupled to the first path and the second path and configured such that the low frequency component attenuated signal and the amplified signal combine at the node.

Abstract: A communication circuit facilitating communication between a first equipment and a second equipment including a conversion circuit, an input port, an output port, and a communication port is disclosed. The conversion circuit converts an input signal to a first intermediate signal, and converts a second intermediate signal to an output signal. The input port inputs the input signal to the first conversion circuit. The output port outputs the output signal to the control unit. The communication port inputs the second intermediate signal to the conversion circuit, and outputs the first intermediate signal to the second equipment. A voltage of the first intermediate signal is determined based on a voltage of a power source if the first intermediate signal is logic high, and a voltage of the second intermediate signal is determined based on the voltage of the power source if the second intermediate signal is logic high.

Abstract: A supply voltage generating circuit that enables a reduction in chip area includes: a booster for outputting a boosted voltage upon generating the boosted voltage by charge pumping of a capacitor element; a power-supply step-down unit for stepping down voltage of an external power supply to a voltage within a breakdown-voltage range of the capacitor element, and applying the stepped-down voltage to the power supply of the booster; and a switch element for switching between application of the external power supply to the power supply of the booster directly or via the power-supply step-down unit. The booster comprises multiple stages of booster circuits. The thicknesses of gate oxide films of capacitor elements constituted by MOS transistors included in respective ones of the booster circuits are the same and are made smaller than the thickness of a gate oxide film of a MOS transistor included in a load circuit having the output of the booster at its power supply.

Abstract: A system which may be implemented on an integrated circuit including a global supply bus, a gated supply bus, a functional circuit receiving voltage from the gated supply bus, and a digital power gating system. The digital power gating system includes gating devices, a power gating control system, and a global control adjuster. The gating devices are coupled between the global and gated supply buses and are controlled by a digital control value. The power gating control system performs power gating by successively adjusting the digital control value to reduce a voltage of the gated supply bus to a state retention voltage level. The global control adjuster performs a global adjustment of the digital control value to increase the voltage of the gated supply bus to prevent it from falling below the state retention voltage level in response to an impending change of a voltage of the global supply bus.

Abstract: An irrigation control device having a modulator that modulates data onto an alternating power signal by distorting amplitude of a first leading portion of selected cycles of the alternating power signal, and permit effectively a full amplitude of the alternating power signal on a following portion of the selected cycles, wherein the first leading portion and the following portion are either both on a high side of a cycle or both on a low side of a cycle of the alternating power signal. The irrigation control device further includes an interface configured to couple the modulator to a multi-wire interface coupled to a plurality of irrigation devices to permit the alternating power signal to be applied to the multi-wire interface.

Abstract: A method for utilizing heat includes steps: converting heat to electrical power, and converting the electrical power to a PWM voltage signal to power a function module. Obtaining an input voltage of the function module and comparing the input voltage with a reference voltage. Increasing a duty cycle of the PWM voltage signal when comparing the input voltage is grater than the reference voltage. And decreasing a duty cycle of the PWM voltage signal when comparing the input voltage is less than the reference voltage.

Abstract: An interface circuit for driving a fully-differential circuit has a first circuit configured to decrease the voltage at its output in response to an increase in an average value of first and second input voltages. A first network receives the first input voltage and the output voltage of the first circuit to provide a first output voltage for driving the fully-differential circuit. A second network receives the second input voltage and the output voltage of the first circuit to provide a second output voltage for driving the fully-differential circuit. An impedance ratio of the first network is substantially matched to an impedance ratio of the second network.

Abstract: An inverter circuit includes an input stage and an output stage, each including pairs of complementary transistors having low-voltage oxides. The transistors within the input stage are configured to receive the input signal and to provide control voltages in response to input signal voltage variations. The voltage level of one control voltage is clamped between an intermediate voltage and a high voltage, and the voltage level of the other control voltage is clamped between the intermediate voltage and a low voltage. The switching states of each complementary transistor in the output stage arc controlled by the control voltages, which results in an output signal voltage varying between the high and the low voltage. The voltage clamping advantageously allows the inverter circuit to switch between the high and the low voltage level without exceeding a maximum gate-source or a gate-drain voltage rating for any transistor, and without requiring additional passive components.

Abstract: A method for adaptively driving data transmission and a communication device using the same are provided. The proposed method includes following procedures. Detection result is generated after detecting a receiving signal on a receiving path of the communication device. Driving parameter is generated according to the detection result. Finally, a transmitting signal on a transmitting path is adjusted according to the driving parameter.

Abstract: In a controlling circuit, a photo coupler is used for isolating noises, and a general purpose amplifier is used for adjusting a gain, so that a logic tester may test analog signals in cooperation with relays having different specifications and operating voltage level differences in an analog measurement module. A shift register of each controlling circuit of a controlling module also transmits a test data signal to a next stage controlling circuit, so that a logic tester may simultaneously output a plurality of bits to multiple controlling circuits and multiple analog measurement modules by using merely one I/O port.

Abstract: A write driver for a memory circuit includes a control circuit configured to: operate a first push-pull driver to generate a first drive signal in a first voltage domain at a first node based on an input signal in a second domain and in response to a mode select signal being in a first mode, wherein the first drive signal is at a same logic level as the input signal; operate a second push-pull driver to generate a second drive signal in the first voltage domain at a second node based on the input signal and in response to the mode select signal being in the first mode, wherein the second drive signal is at a complement logic level with respect to the input signal; and operate the first and second push-pull drivers to float the first and second nodes in response to the mode select signal being in a second mode.

Abstract: A voltage regulator for controlling an output device in accordance with embodiments includes an error amplifier; a controlled conductance output device; and a load predicting circuit; wherein an output of the error amplifier and an output of the load predicting circuit are summed to control the output device.

Abstract: A battery management apparatus is provided. The battery management apparatus includes a switched capacitor level shifter having a first port and a second port. The first port is configured to couple to a cell in a battery stack and the second port is configured to couple to a voltage measurement device. The apparatus includes a discharge device coupled to the second port, wherein the discharge device is configured to discharge the cell via the switched capacitor level shifter. A method of managing a battery stack is also included.

Abstract: Systems and methods are provided for reducing jitter due to power supply noise in an integrated circuit by drawing additional current. The additional current causes the total current to generally have a frequency higher than a resonant frequency of the integrated circuit and/or a power distribution network of the integrated circuit. In one example, a power distribution network may supply power to components of an integrated circuit and data driver circuitry may draw first current to drive a data signal. Compensation circuitry may draw second current at times when the data driver circuitry is not drawing the first current, thereby causing a net of the first and second current to be higher than a resonant frequency range of the integrated circuit device and/or a component of the integrated circuit device (e.g., the power distribution network).

Abstract: Embodiments include an apparatus, system, and method related to a body-contacted partially depleted silicon on insulator (PDSOI) transistor that may be used in a switch circuit. In some embodiments, the switch circuit may include a discharge transistor to provide a discharge path for a body of a switch transistor. Other embodiments may be described and claimed.

Abstract: An apparatus comprises an integrated circuit (IC) and a resistor external to the IC. The IC includes a current output digital-to-analog converter (IDAC) circuit configured to provide an adjustable specified current to a resistor external to the apparatus, a voltage sensing circuit configured to sense the voltage of the external resistor, and an automatic gain control (AGC) circuit configured to receive threshold information using the adjustable specified current.