Abstract: A semiconductor device includes an amplifier section that receives a small-amplitude signal in which data is updated in synch with a clock, and an output section coupled to the output of the amplifier section. In synch with the clock, the amplifier section increases the current of a current source at timings at which the logic level of the small-amplitude signal is capable of undergoing a transition, and decreases the current at timings at which there is no transition. In synch with the clock, the output section drives a load by decreasing output impedance at timings at which the logic level of output data of the amplifier section is capable of undergoing a transition, and prevents flow of a through-current by increasing output impedance at timings at which the logic level does not undergo a transition.

Abstract: A power-supply sequence-free electronic circuit is realized without the increase of the number of power supply detectors for detecting the rising of the power supply. The electronic circuit operated by supplying three or more types of power supply voltages to the ground voltage of the circuit generates a first detection signal indicating whether any one of other power supply voltages does not rise by a first detection circuit which is operated with a predetermined power supply voltage as an operation power supply. The electronic circuit generates a second detection signal indicating whether the predetermined power supply voltage rises by a second detection circuit which is provided for each of the other power supply voltages and operated with one power supply voltage of the other power supply voltages as an operation power supply.

Abstract: Provided is a signal generating apparatus that outputs from an output end thereof an output voltage corresponding to input data supplied thereto, comprising: a DA converter that outputs a voltage corresponding to data supplied thereto; a capacitor section that is provided between the output end and a standard potential; a transmission switch that provides a connection or a disconnect between a voltage generating end of the DA converter and the output end; and a control section that causes the DA converter to charge the capacitor section with a voltage corresponding to the input data by repeatedly connecting and disconnecting the transmission switch, thereby causing the voltage of the capacitor section to gradually approach the output voltage corresponding to the input data.

Abstract: A method for automatic gain control of a front-end for a digital video receiver is provided. The method includes the following steps. First, a radio frequency signal is received and converted to an intermediate frequency signal. Then, the IF signal is amplified according to a gain. Next, the amplified IF signal is demodulated into a base-band signal, and the base-band signal is encoded into a transport stream. After that, a DC level of a pulse width modulation signal is controlled by at least one variable resistor to adjust the gain, the PWM signal being related to a setting of the gain. Afterwards, a BER measurement at each potential setting of the gain and the variable resistor under one or more power levels of the RF signal is read, and an optimum setting of the gain and the variable resistor is selected according to the BER measurements.

Abstract: An output circuit of a semiconductor device includes a signal selector configured to receive first and second input data signals and sequentially outputting the first and second input data signals in response to a phase signal; and an output level controller configured to control a voltage level of an output signal of the signal selector based on the first and second input data signals.

Abstract: A semiconductor device according to the present invention comprises a first semiconductor integrated circuit 11 having a predetermined function, the first semiconductor integrated circuit outputting a required output signal, a second semiconductor integrated circuit 12 in which a plurality of MOS elements (PMOS transistor or NMOS transistor) for independently switching to and from a conducted state and a non-conducted state in accordance with a plurality of gate signals each having a different timing is provided and the plurality of MOS elements is connected in parallel to an output or an input of the first semiconductor integrated circuit, and a pulse generating circuit 13 for generating and outputting the plurality of gate signals ?i (i=1, 2, 3) each having a different timing with respect to the plurality of MOS elements in the second semiconductor integrated circuit.

Abstract: Provided is a signal generating apparatus that outputs from an output end thereof an output voltage corresponding to input data supplied thereto, comprising: a DA converter that outputs a voltage corresponding to data supplied thereto; a capacitor section that is provided between the output end and a standard potential; a transmission switch that provides a connection or a disconnect between a voltage generating end of the DA converter and the output end; and a control section that causes the DA converter to charge the capacitor section with a voltage corresponding to the input data by repeatedly connecting and disconnecting the transmission switch, thereby causing the voltage of the capacitor section to gradually approach the output voltage corresponding to the input data.

Abstract: An oscillator circuit increases and reduces signal levels of first and second oscillation signals in a complementary manner in response to a transition of a signal level of a reference clock. An oscillation control circuit compares each of the signal levels of the first and second oscillation signals to a comparison voltage, and causes the signal level of the reference clock to transition according to results of the comparison. A reference control circuit increases or reduces the comparison voltage so that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced.

Abstract: Provided is method for automatic audio gain modulation and a related apparatus. In order to prevent the unstable signals as continuously increasing or decreasing the gain when the signals hover around an upper threshold, it's featured that the method is to predict the signal intensity as pre-adding a predict gain in a hold time before outputting signals. By determining whether the prediction exceeds a predetermined threshold or not, the suitable and adjustable gains can be obtained without exceeding the predetermined threshold. In the automatic gain control mechanism, it's to decrease the gain gradually as automatically entering an attack time, or to increase the gain gradually as performing a conventional auto-gain control procedure including entering a release time. The claimed method can modulate the gain automatically by predicting the gain, and confine the signals under a threshold. In addition to avoid sawtooth phenomena, the method can stabilize the signals.

Abstract: A trim circuit comprises a trim code storage unit, a global latch unit and a local latch unit. The trim code storage unit stores a plurality of trim codes and outputs a sensing code in response to an address signal. The global latch unit latches a calibrated code or the sensing code to generate a global output signal. The calibrated code is generated by performing a calibration on the sensing code. The local latch unit repeatedly latches the global output signal in response to the address signal to generate a plurality of trim output signals.

Abstract: A circuit for converting the state of a sensor into a signal interpretable by an electronic circuit, including: a comparator of the voltage level of an input terminal with respect to a reference level, the sensor being intended to be connected between a terminal of application of a first power supply voltage and the input terminal; a current-limiting element between said input terminal and the ground; and a switching element in series with the current source and intended to be controlled by a pulse train.

Abstract: A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of an IO receiver, and controllably generating a second bias voltage from an external voltage supplied through an IO pad to be within the upper tolerable limit of the operating voltage of the IO receiver. The method also includes deriving an output voltage from the first bias voltage during a normal condition and a tolerant condition, and deriving the output voltage from the second bias voltage during a failsafe condition. The tolerant condition is a mode of operation where the external voltage supplied through the IO pad varies from zero to a value higher than the supply voltage, and the failsafe condition is a mode of operation where the supply voltage is zero.

Abstract: In one form, a power detector includes first and third transistors of a first conductivity type, and second and fourth transistors of a second conductivity type. A control electrode of the first transistor receives a first bias voltage plus a positive component of a differential input signal. The second transistor is coupled in series with the first transistor and has a control electrode receiving a second bias voltage plus a negative component of the differential input signal. The third transistor is biased using the first bias voltage plus the negative component. The fourth transistor is coupled in series with the third transistor and is biased using the second bias voltage plus the positive component. A common interconnection point of the first and third transistors forms an output node. In another form, a power detector compares an output of a power detector core to multiple threshold voltages in corresponding comparators.

Abstract: A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of one or more constituent active circuit element(s) of an Input/Output (IO) core device of an integrated circuit (IC) to be interfaced with an IO pad, and controllably generating a second bias voltage from an external voltage supplied through the IO pad to be within the upper tolerable limit of the operating voltage of the one or more constituent active circuit element(s) of the IO core device to be interfaced with the IO pad. The method also includes controllably utilizing a control signal generated by the IO core to derive an output bias voltage from the first bias voltage during a driver mode of operation or the second bias voltage during a failsafe mode of operation and a tolerant mode of operation.

Abstract: A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of one or more constituent active circuit element(s) of an Input/Output (IO) core device of an integrated circuit (IC) to be interfaced with an IO pad, and controllably generating a second bias voltage from an external voltage supplied through the IO pad to be within the upper tolerable limit of the operating voltage of the one or more constituent active circuit element(s) of the IO core device to be interfaced with the IO pad. The method also includes controllably utilizing a control signal generated by the IO core to derive an output bias voltage from the first bias voltage during a driver mode of operation or the second bias voltage during a failsafe mode of operation and a tolerant mode of operation.

Abstract: A sense amplifier circuit, which is connected to a bit line and to an inverted bit line to which a voltage, inverted alternatively from a high level or a low level of a voltage applied to the bit line, is applied, includes a first resistance section reducing a voltage output from a memory cell through the inverted bit line, a second resistance section reducing a voltage output from a memory cell through the bit line, and an amplification section amplifying the first voltage reduced by the first resistance section and amplifying the second voltage reduced by the second resistance section.

Abstract: A method and apparatus are provided for calibrating a ladder circuit. The apparatus includes: a logic unit for receiving a first logical signal, a second logical signal, and N control bits and for outputting N alternative control bits and an additional control bit, where N is an integer greater than 1; a core circuit for receiving the N alternative control bits, the additional control bit, and a tuning word, and for outputting an output signal, wherein the core circuit comprises N?1 series elements, N shunt elements with a connectivity controlled by the N alternative control bits, respectively, and a termination element with a connectivity controlled by the additional control bit; and a calibration circuit for receiving the first logical signal, the second logical signal, and the output signal and for outputting the tuning word.

Abstract: A broadband active circuit with a feedback structure includes: an active load unit providing a load varied according to a control voltage; an active circuit unit connected between the active load unit and a ground and outputting a signal corresponding to a pre-set bandwidth, among input signals; and a feedback circuit unit formed between an output terminal of the active circuit unit and the active load unit and providing a signal from the output terminal of the active circuit unit to the active load unit.

Abstract: The invention relates to an interfacing device for transmission through interconnections used for sending a plurality of electrical signals. The interfacing device of the invention comprises signal terminals and a common terminal. A transmitting circuit receives the input signals of the transmitting circuit coming from a source and delivers, when the transmitting circuit is in the activated state, currents to the signal terminals, each of the currents being mainly determined by one or more of the input signals of the transmitting circuit, one or more of the currents being not mainly determined by only one of the input signals of the transmitting circuit. The balancing circuit is such that, when the transmitting circuit is in the activated state, the current flowing out of the common terminal approximates the opposite of the sum of the currents flowing out of the signal terminals.

Abstract: A logic signal isolator comprising a transformer having a primary winding and a secondary winding; a transmitter circuit which drives said primary winding in response to a received logic signal, such that in response to a first type of edge in the logic signal, a signal of a first predetermined type is supplied to the primary winding and in response to a second type of edge in the logic signal, a signal of a second predetermined type is supplied to said primary winding, the primary winding and the transmitter being referenced to a first ground; and the secondary winding being referenced to a second ground which is galvanically isolated from the first ground and said secondary winding supplying to a receiver circuit signals received in correspondence to the signals provided to the primary winding, the receiver reconstructing the received logic signal from the received signals.

Abstract: A voltage trimming circuit is provided. The voltage trimming circuit has an input stage, an up-trimming resistor ladder, a down-trimming resistor ladder and a control means. The input stage has a first input, a second input and an output, wherein the first output is to receive an input voltage, the second input is connected to a connection point and the output is to provide an output voltage based on a difference between the voltage of the first and the second input. The up-trimming resistor ladder is connected between the output of the input stage and the connection point and the down-trimming resistor ladder connected between a ground potential and the connection point. The control means controls the resistance of the up-trimming and the down-trimming resistor ladder to up-trim or down-trim the output voltage.

Abstract: A signal input circuit includes an input unit, a first compensation circuit, a second compensation circuit, and an enable circuit. The input unit receives a first input signal to output an output signal to an output node. The first compensation circuit is connected to the output node and discharges the output node in response to a second input signal. The second compensation circuit is connected to the output node and supplies a current to the output node in response to the second input signal. The enable circuit enables the input unit and the first and second compensation circuits in response to at least one operation mode selection signal.

Abstract: A method is provided for improving clock recovery signal jitter in digital communication based on a phase adjustment technique in a phase interpolation. A clock signal is expressed as the combination of two sinusoidal signals. The phase interpolating process determines the amplitude of the first sinusoidal signal, and the amplitude of the second sinusoidal signal that is 90° out of phase from the first sinusoidal signal. The clock signal is then formed by combining first sinusoidal signal with the second sinusoidal signal by choosing the first and second amplitude such that the amplitude of the clock signal is substantially a constant. Modulation of the clock signal amplitude is significantly improved by the disclosed technique over the conventional technique when the sum of the first and second amplitudes of the two sinusoidal functions is kept a constant.

Abstract: A circuit includes a differential circuit having at least to two inputs, a first variable impedance circuit, and a second variable impedance circuit. The first variable impedance circuit is between a first branch of the differential circuit and an output. The first variable impedance circuit provides a first variable impedance. The a second variable impedance circuit is between a second branch of the differential circuit and the output. The second variable impedance circuit provides a second variable impedance. The first variable impedance and the second variable impedance vary in accordance with a voltage difference between the two inputs.

Abstract: A voltage trimming circuit is provided. The voltage trimming circuit has an input stage, an up-trimming resistor ladder, a down-trimming resistor ladder and a control means. The input stage has a first input, a second input and an output, wherein the first output is to receive an input voltage, the second input is connected to a connection point and the output is to provide an output voltage based on a difference between the voltage of the first and the second input. The up-trimming resistor ladder is connected between the output of the input stage and the connection point and the down-trimming resistor ladder connected between a ground potential and the connection point. The control means controls the resistance of the up-trimming and the down-trimming resistor ladder to up-trim or down-trim the output voltage.

Abstract: Apparatus for generating a first signal (e.g., a pulse) including a current source adapted to generate a current based on a second signal that defines an amplitude of the current and a third signal that defines the timing of an amplitude change of the current, and an impedance element through which the current flows to generate the first signal. The impedance element may comprise a resonator having a resonant frequency approximate the center of the first signal frequency spectrum. An LO may be used to generate the third signal to control the timing of the amplitude change of the current. A detector may enable the current source in response to detecting a defined steady-state condition of the LO clock signal, and may disable the current source in response to the completion of the first signal. A controller may generate the second signal to control the current amplitude so as to perform power control and/or other functions.

Abstract: A semiconductor device includes an internal circuit to perform a predetermined function at a plurality of different supply power voltages, a power supply voltage region detector to detect a supply power voltage to output a detection signal, a latch to store the signal output from the power supply voltage region detector and output the stored signal as a power supply voltage region signal, and a reset circuit to generate a reset signal to perform a predetermined reset operation on the internal circuit. The latch stores the output signal from the power supply voltage region detector just after the reset operation for the internal circuit is released, and the internal circuit changes an internal setting according to the power supply voltage region signal output from the latch.

Abstract: The invention concerns in general measurement of the transfer function of linear time invariant systems, more particular the calibration of such systems based on a measured transfer function. According to a first aspect the present invention an arrangement for measuring the transfer function of a linear time-invariant system is disclosed. According to a second aspect of the present invention the arrangement is implemented into a linear time-invariant circuitry having a transfer function representing the amplitude and phase characteristic of the circuitry, where by means of the arrangement for measuring the transfer function the transfer function can be optimized in accordance with certain criteria on-the-fly, i.e. in or before operation of the circuit. Finally, an effective and simple method for measuring of the transfer function of a linear time-invariant system together with the use or application of the method is shown.

Abstract: A buffering circuit with reduced power consumption is provided. The output buffering circuit includes first and second amplifier circuits. The first amplifier circuit includes a first input stage and a first output stage both coupled between a first power voltage and a second power voltage lower than the first power voltage, and an assistant discharging unit configured to provide a discharging current flowing from a first output node to a first intermediate power voltage during a discharging operation of the first amplifier circuit. The second amplifier circuit includes a second input stage and a second output stage both coupled between the first power voltage and the second power voltage, and an assistant charging unit configured to provide a charging current flowing from a second intermediate power voltage to a second output node during a charging operation of the second amplifier circuit.

Abstract: Apparatuses, systems, and methods are disclosed for generating, regulating, and modifying various voltage levels on a semiconductor device using a current mirroring digital-to-analog voltage regulator. The voltage regulator operates by mirroring a reference current onto a selectable current level and controlling the selectable current level with a digital input to a plurality of switched CMOS devices connected in parallel. The switched CMOS devices generate the selectable current level responsive to the digital input and proportional to the reference current. The selectable current level is combined with an output of a voltage divider to generate a monitor signal. The monitor signal is compared to a reference voltage and the results of the comparison controls a charge pump to generate a pumped voltage. The pumped voltage is fed back to the voltage divider, which includes a feedback resistor and a reference resistor connected in series between the pumped voltage and ground.

Abstract: A method to provide a low-power clock signal or a low-noise clock signal is described herein. It is determined whether a low-power mode or a low-noise mode is in use. A voltage reference input of a low-dropout voltage regulator (LDO) is switched to a low-power voltage reference for low-power mode and to a low-noise voltage reference for low-noise mode. The LDO provides a constant voltage output to a crystal oscillator. A clock signal is generated using the crystal oscillator. The clock signal is limited using a low-power limiter to generate a low-power output clock signal and/or is limited using a low-noise limiter to generate a low-noise clock signal. The low-power output clock signal or the low-noise output clock signal is selected using a mux.

Abstract: Methods and circuitry for lowering the capacitance of interconnects, particularly Through Wafer Interconnects (TWIs), using signal level adjustment are disclosed. Embodiments of the invention seek to bias the midpoint voltage level of the signals on the TWIs towards inversion, where at high frequencies capacitance is at its minimum. In one embodiment, reduced swing signals are used for the data states transmitted across the TWIs, in which the reduced swing signals use a midpoint voltage level tending to bias the TWI capacitance towards inversion. In another embodiment, signals are AC coupled to the TWI where they are referenced to an explicit bias voltage directly connected to the TWI. This allows signals to propagate through the TWI while the TWI is biased towards inversion. In a third embodiment, the potential of the substrate is explicitly lowered with respect to the TWI potential.

Abstract: A clock signal amplifier circuit includes: an inverter; a coupling capacitor connected to the input of the inverter; two resistors connected in series between the power supply potential and the ground potential, a connection node of the two resistors being connected to the input of the inverter; a feedback resistor provided between the input and output of the inverter; and two switches configured to perform a same open/close operation according to a control signal, the two switches being provided on any two of a supply path of the power supply potential to the inverter, a supply path of the ground potential to the inverter, and a feedback path of the inverter via the feedback resistor.

Abstract: A semiconductor integrated circuit includes: a first flip-flop, a combined circuit and a second flip-flop that form a critical path; a first delay circuit and a third flip-flop that are provided in the post-stage of the combined circuit; a second delay circuit and a fourth flip-flop that are provided in the post-stage of the combined circuit; a first comparison circuit that compares the output of the second flip-flop with the output of the third flip-flop; a second comparison circuit that compares the output of the second flip-flop with the output of the fourth flip-flop: and a control circuit that controls a source voltage supplied to the combined circuit in accordance with the outputs of the comparison circuits. A delay time by the first delay circuit is different from a delay time by the second delay circuit.

Abstract: The common-mode voltage of a switched-capacitor system is controlled by determining a current common-mode voltage of the switched-capacitor system, converting (in a flow-through conduction cell) the difference between the current common-mode voltage and a desired common-mode voltage into a resultant current, and reinjecting this resultant current into the switched-capacitor system via a resistive path.

Abstract: A method, device and computer program product for providing increased reliability in the processing of digital signals. The device includes a module for performing analog measurement of a received signal intended to occupy two logical states at various instances in time, a module for determining if there is a change in the analog signal level, a module for determining if the change fulfills at least one logical state change condition, wherein a first logical state change condition is based on the speed of change of the analog signal level, and a module for determining that there is a change from one logical state to the other if at least one logical state change condition is fulfilled. The invention provides secure detection of unreliable digital signals that may be generated in harsh environments that are polluted or moist.

Abstract: The invention relates to an electronic circuit for transmitting high-frequency signals. Said electronic circuit comprises an amplification circuit featuring frequency-dependent amplification which remains the same or drops in a vicinity of a threshold frequency (fth) towards higher frequencies. The electronic circuit further comprises an equalizer circuit which is mounted behind the amplification circuit and has a frequency pass that increases in the vicinity of the threshold frequency (fth) towards higher frequencies.

Abstract: A signal receiver circuit includes a first level detector for offset-controlling a first output node in response to a pair of first reference signals. A second level detector offset-controls a second output node in response to a pair of second reference signals.

Abstract: Provided is a semiconductor integrated circuit including: a differential driver that is, disposed between a first power supply and a second power supply and drives differential input signals to generate differential output signals; and a control signal generation circuit that generates a first control signal for controlling a voltage level of each of the differential output signals. When each of a pair of output signals forming the differential output signals is changed from a voltage level corresponding to the first power supply to a voltage level corresponding to the second power supply, an amount of change in the voltage level of the corresponding output signal is controlled based on the first power supply.

Abstract: A digital signal detector detects digital signals by only sensing the rising and falling edges of a received digital signal and latches the logic state between the detected edges. Such edges contain very high frequencies that are much higher than the fundamental frequency of the digital signal train. A small high pass filter filters out at least the DC component and the fundamental frequency of the received digital signal. A filtered edge appears as a spike that goes either positive or negative depending on whether the edge is a rising or falling edge. A memory element, such as comprising an RS flip flop, is triggered by the positive and negative spikes. A positive spike triggers the flip flop to output a logical one, and a negative spike triggers the latch to output a logical zero. In this way, the digital signal is recreated without the original digital signal itself being required to pass through the high pass filter.

Abstract: A semiconductor integrated circuit includes a first clock pin controller that receives a mirror function signal and a test mode signal to generate a first input buffer control signal in response to the mirror function signal in a normal mode. A second clock pin controller receives the mirror function signal and the test mode signal to generate a second input buffer control signal, which is an inverted signal of the first input buffer control signal, in response to the mirror function signal in the normal mode. An input buffer unit generates output signals of first and second pins in response to the first input buffer control signal and the second input buffer control signal, respectively.

Abstract: Systems and methods are provided for calibrating the control mechanism in a communication circuit to allow the communication circuit to maintain a desired output power level. The communication circuit includes a variable gain adjustment circuit and a power amplifier, which operate together to provide an output power level. A control circuit controls the variable gain adjustment circuit based on a default gain parameter, a high power threshold, and a low power threshold. A calibration circuit in the control circuit calibrates a default gain parameter to provide a desired output power. A power detector can detect the desired output power level to provide an output power measurement. The calibration circuit calibrates upper and lower power thresholds to provide an acceptable range of power variation around the output power measurement.

Abstract: A method and system for synchronizing an input signal for a power system. The method comprises: extracting from the input signal, three substantially equidistant samples from a fundamental component of the input signal; determining a frequency (f1), an amplitude (A1), and a phase-difference (?Diff) of the input signal from the three equidistant samples and a tracking signal corresponding to a steady-state of the fundamental component of the input signal characterized by a frequency (fTS) and an amplitude (ATS) with a phase-difference that is the phase angle between the tracking signal and the input signal; and generating and outputting a frequency, amplitude, and phase-difference signals corresponding to the determined frequency (f1), amplitude (A1), and phase-difference (?Diff) of the input signal to one or more components of the power system.

Abstract: A semiconductor device according to the present invention comprises a first semiconductor integrated circuit 11 having a predetermined function, the first semiconductor integrated circuit outputting a required output signal, a second semiconductor integrated circuit 12 in which a plurality of MOS elements (PMOS transistor or NMOS transistor) for independently switching to and from a conducted state and a non-conducted state in accordance with a plurality of gate signals each having a different timing is provided and the plurality of MOS elements is connected in parallel to an output or an input of the first semiconductor integrated circuit, and a pulse generating circuit 13 for generating and outputting the plurality of gate signals ?i (i=1, 2, 3) each having a different timing with respect to the plurality of MOS elements in the second semiconductor integrated circuit.

Abstract: The invention discloses a signal converting device, and more particularly, to a signal converting device that improves the signal quality. The signal converting device comprises a first input end, a second input end, an output end, a first circuit and a second circuit. The first circuit is coupled between the first input end and the output end. The first circuit determines whether to charge up the output end to generate an output signal or not according to a first differential input signal. The second circuit is coupled between the second input end and the output end. The second circuit determines whether to discharge the output end to generate the output signal or not according to a second differential input signal.

Abstract: Disclosed are various embodiments of pulse generation and automatic gain control (“AGC”) circuits and corresponding methods that are especially well suited for use in motion encoding systems. Analog output signals provided by a motion encoder serve as inputs to the pulse generation circuit, where peaks, valleys and/or crosspoints corresponding to such analog signals are first detected and then employed to generate output pulses corresponding thereto. These output pulses are next provided to an AGC circuit as self-generated clock signals which control the time windows over which the analog signals of the motion encoder are sampled and processed by the AGC circuit so as to adjust the gains applied to such analog signals.

Abstract: A level shift circuit comprises a first input terminal, a second input terminal, a first output terminal, a second output terminal, a level shifter and an equalization unit. The first and second input terminals receive an input signal and an inverted input signal respectively. The first and second output terminals output an output signal and an inverted output signal respectively. The level shifter is connected to the first and second input terminals, the first and the second output terminals. The equalization unit is coupled between the first and second output terminals. Wherein, at a reset phase, the input signal and the inverted input signal are inputted to the level shifter, and the equalization unit is turned on. After the reset phase, the equalization unit is turned off and the level shifter starts to shift a level of the input signal.

Abstract: Locked loops, bias generators, charge pumps and methods for generating control voltages are disclosed, such as a bias generator that generates bias voltages for use by a clock signal generator, such as a voltage controlled delay line, in a locked loop having a phase detector and a charge pump. The charge pump can either charge or discharge a capacitor as a function of a signal from the phase detector to generate a control voltage. The bias generator can receive the control voltage from the capacitor, and it generates bias voltages corresponding thereto. A portion of the bias generator can have a topography that is substantially the same as at least a portion of the topography of the charge pump. As a result, it can cause the charge pump to charge the capacitor at the same rate that it discharges the capacitor over a relatively wide range of control voltages. The charge pump and the bias generator can also include circuitry for limiting the charging of the capacitor when the control voltage is relatively low.

Abstract: The present invention sets forth a controllable resistive circuit which comprises a transistor, a capacitor, a charging unit and a discharging unit. The transistor is capable of providing a variable resistance which is controlled to vary continuously and smoothly. The charging and discharging units are used to respectively charge and discharge the capacitor in different periods. As a result, the capacitor can provide a variable voltage which is controlled to vary continuously and smoothly to control the equivalent resistance of the transistor during the period the capacitor is discharging. Therefore, the controllable resistive circuit in accordance with the present invention is capable of being used in any kind of circuit which requires a variable resistance varied continuously and smoothly.

Abstract: The present invention relates to a gain control circuit, which detects an output signal of a front-end circuit to produce a detection signal. An operation unit performs an accumulation operation to the detection signal and thereby produces an operation signal. In addition, the operation unit also resets the operation unit according to a reset signal. A reset unit produces the reset signal for every predetermined interval of time. A control unit produces a control signal according to the operation signal and a first threshold value for controlling an output gain of the front-end circuit.