Abstract: A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor having a first electrode layer, a second electrode layer, and an insulating layer between the first electrode layer and the second electrode layer. At least three dielectric layers are between a bottom surface of the capacitor and the active region.

Abstract: Some implementations provide an interposer that includes a substrate, a first passive device in the substrate, and a second passive device. The first passive device includes a first set of through substrate vias (TSVs) in the substrate. The second passive device is configured to wirelessly couple to the first passive device. In some implementations, the second passive device includes a second set of through substrate vias (TSVs) in the substrate. In some implementations, the second passive device is configured to inductively couple to the first passive device. In some implementations, the first passive device is a first inductor and the second passive device is a second inductor. In some implementations, the interposer further includes a first set of interconnects coupled to the first set of TSVs, and a second set of interconnects coupled to the second set of TSVs.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers stacked alternately with a plurality of insulating layers on the substrate, a channel body provided inside a hole piercing the stacked body, and a memory portion provided between the channel body and each of the plurality of electrode layers. The hole has a large diameter portion and a small diameter portion. The diameter of the hole is smaller at the small diameter portion than at the large diameter portion. A thickness of the electrode layer adjacent to the small diameter portion is thicker than a thickness of the electrode layer adjacent to the large diameter portion.

Abstract: A variable capacitance sensor includes a first conductive electrode comprising electrically interconnected first conductive sheets; a second conductive electrode comprising electrically interconnected second conductive sheets, wherein the first conductive sheets are at least partially interleaved with the second conductive sheets, and wherein the second conductive electrode is electrically insulated from the first conductive electrode; and microporous dielectric material at least partially disposed between and contacting the first conductive sheets and the second conductive sheets. A method of making a variable capacitance sensor by replacing ceramic in a ceramic capacitor with a microporous material is also disclosed.

Abstract: A method of manufacturing a semiconductor device includes forming a first conductive layer on a substrate, partially removing the first conductive layer and an upper portion of the substrate to form a recess, forming a second conductive layer pattern to fill the recess, forming a third conductive layer on the second conductive layer pattern and the first conductive layer, and patterning the third conductive layer and the second conductive layer pattern to form a bit line structure and a bit line contact, respectively.

Abstract: Semiconductor devices and methods of formation are provided herein. A semiconductor device includes a first inductor, a patterned ground shielding (PGS) proximate the first inductor comprising one or more portions and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. The semiconductor device also has a configuration including a first inductor on a first side of the PGS, a second inductor on a second side of the PGS and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. Selective coupling of portions of the PGS by activating or deactivating switches alters the behavior of the first inductor, or the behavior and interaction between the first inductor and the second inductor. A mechanism is thus provided for selectively configuring a PGS to control inductive or other properties of a circuit.

Abstract: According to one embodiment, a scalable integrated MIM capacitor in a semiconductor die includes a high-k dielectric segment over a substrate and a metal segment over the high-k dielectric segment, where the metal segment forms a capacitor terminal of the integrated MIM capacitor. The capacitor further includes a filler laterally separating consecutive capacitor terminals, where the filler can be used as a capacitor dielectric of the integrated MIM capacitor. In one embodiment, the metal segment comprises a gate metal. In another embodiment, the integrated MIM capacitor is formed substantially concurrently with one or more transistors without requiring additional fabrication process steps.

Abstract: Electronic chip comprising: an electronic circuit located at a front face of a substrate; a capacitive element placed at a back face of the substrate and facing the electronic circuit, and electrically connected to the electronic circuit by a first electrical connection and a second electrical connection, the first electrical connection including at least a first electrically conducting via passing through the substrate, the electronic circuit being capable of measuring the value of the electrical capacitance of the capacitive element between the first and the second electronic connections, and at least one second via or a trench passing through the back face of the substrate and a part of the thickness of the substrate, and facing the electronic circuit such that a bottom wall of the second via or of the trench are separated from the electronic circuit by a non-zero distance.

Abstract: A method for fabricating semiconductor memory device, includes providing a semiconductor substrate; forming a lower region which includes a first data storage device, which is carried by the semiconductor substrate; forming a switching device which is carried by the first data storage device; and forming an upper region which includes a second data storage device, which is carried by the switching device. The step of forming the first storage device includes forming a first electrode having a cylindrical or pillar shape, the first electrode being connected to the switching device.

Abstract: A method of forming a two terminal device. The method includes forming a first dielectric material overlying a surface region of a substrate. A bottom wiring material is formed overlying the first dielectric material and a switching material is deposited overlying the bottom wiring material. The bottom wiring material and the switching material is subjected to a first patterning and etching process to form a first structure having a top surface region and a side region. The first structure includes at least a bottom wiring structure and a switching element having a first side region, and a top surface region including an exposed region of the switching element. A second dielectric material is formed overlying at least the first structure including the exposed region of the switching element. The method forms an opening region in a portion of the second dielectric layer to expose a portion of the top surface region of the switching element.

Abstract: A TFT array substrate is disclosed. The TFT array substrate includes a TFT area, which includes a TFT first electrode layer, a TFT second electrode layer, a TFT insulation layer, and a TFT etching stop layer. The TFT array substrate also includes also includes a storage capacitor, which includes a capacitor first electrode layer, a capacitor second electrode layer, a capacitor insulation layer, and a capacitor etching stop layer. The TFT first electrode layer and the capacitor first electrode layer are formed in a shared first electrode layer, the TFT second electrode layer and the capacitor second electrode layer are formed in a shared second electrode layer, the TFT insulation layer and the capacitor insulation layer are formed in a shared insulation layer, and the TFT etching stop layer and the capacitor etching stop layer are formed in a shared etching stop layer.

Abstract: A semiconductor structure may include a first electrode over a substrate, a high-K dielectric material over the first electrode, and a second electrode over the high-K dielectric material, wherein at least one of the first electrode and the second electrode may include a material selected from the group consisting of a molybdenum nitride (MoxNy) material, a molybdenum oxynitride (MoOxNy) material, a molybdenum oxide (MoOx) material, and a molybdenum-based alloy material comprising molybdenum and nitrogen.

Abstract: The present invention provides a method and apparatus for fabricating piezoresistive polysilicon on a substrate by low-temperature metal induced crystallization by: (1) providing the substrate having a passivation layer; (2) performing, at or near room temperature in a chamber without breaking a vacuum or near-vacuum within the chamber, the steps of: (a) creating a metal layer on the passivation layer, and (b) creating an amorphous silicon layer on the metal layer, wherein the metal layer and the amorphous silicon layer have approximately the same thickness; (3) annealing the substrate, the passivation layer, the metal layer and the amorphous silicon layer at a temperature equal to or less than 600° C. and a period of time equal to or less than three hours to form a doped polysilicon layer below a residual metal layer; and (4) removing the residual metal layer to expose the doped polysilicon layer.

Abstract: A semiconductor memory device and a fabrication method thereof capable of improving electric contact characteristic between an access device and a lower electrode are provided. The semiconductor memory device includes an access device formed in a pillar shape on a semiconductor substrate, a first conductive layer formed over the access device, a protection layer formed on an edge of the first conductive layer to a predetermined thickness, and a lower electrode connected to the first conductive layer.

Abstract: An integrated circuit includes isolation capacitors which include a silicon dioxide dielectric layer and a polymer dielectric layer over the layer of silicon dioxide. The silicon dioxide dielectric layer and the polymer dielectric layer extend across the integrated circuit. Top plates of the isolation capacitors have bond pads for wire bonds or bump bonds. Bottom plates of the isolation capacitors are connected to components of the integrated circuit. Other bond pads are connected to components in the integrated circuit through vias through the silicon dioxide dielectric layer and the polymer dielectric layer.

Abstract: An inductor structure includes a substrate, a protection layer, a patterned first conductive layer, copper bumps, a passivation layer, a diffusion barrier layer, and an oxidation barrier layer. The protection layer is located on the substrate. The bond pads of the substrate are respectively exposed through protection layer openings. The first conductive layer is located on the surfaces of the bond pads and the protection layer adjacent to the protection layer openings. The copper bumps are located on the first conductive layer. The passivation layer is located on the protection layer and the copper bumps. At least one of the copper bumps is exposed through a passivation layer opening. The diffusion barrier layer is located on the copper bump that is exposed through the passivation layer opening. The oxidation barrier layer is located on the diffusion barrier layer.

Abstract: A capacitor of a semiconductor device includes a capacitor structure configured to include electrode layers and dielectric layers alternately stacked, edge regions each stepwise patterned, and a central region disposed between the edge regions, sacrificial layers disposed within the respective electrode layers in the edge regions of the capacitor structure, and support plugs formed in the central region of the capacitor structure and configured to penetrate the electrode layers and the dielectric layers.

Abstract: A semiconductor component and methods for manufacturing the semiconductor component that includes a monolithically integrated common mode choke. In accordance with embodiments, a transient voltage suppression device may be coupled to the monolithically integrated common mode choke.

Abstract: Methods of forming a capacitor including forming a titanium nitride material within at least one aperture defined by a support material, forming a ruthenium material within the at least one aperture over the titanium nitride material, and forming a first conductive material over the ruthenium material within the at least one aperture. The titanium nitride material may be oxidized to a titanium dioxide material. A second conductive material may be formed over a surface of the titanium dioxide material. A semiconductor device may include at least one capacitor, wherein a major longitudinal portion of the at least one capacitor is not surrounded by a solid material. The capacitor may include a first electrode; a ruthenium oxide material laterally adjacent the first electrode; a rutile titanium dioxide material laterally adjacent the ruthenium oxide material; and a second electrode laterally adjacent the rutile titanium dioxide material.

Abstract: Various embodiments provide inductor devices and fabrication methods. An exemplary inductor device can include a plurality of planar spiral wirings isolated by a dielectric layer. The planar spiral wirings can be connected by conductive pads formed over the dielectric layer and by conductive plugs formed in the dielectric layer. In one embodiment, a third planar spiral wiring can be formed over a second planar spiral wirings that is formed over a first planar spiral wiring. The third planar spiral wiring can be configured in parallel with the first third planar spiral wiring. The second planar spiral wiring can be configured in series with the first and third planar spiral wirings configured in parallel.

Abstract: The semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein, semiconductor memory elements formed over the semiconductor substrate in the cell region, an interlayer insulating layer formed over the semiconductor substrate in the peripheral circuit region, first conductive layers substantially vertically passing through the interlayer insulating layer, and arranged in a matrix, and second conductive layers coupling the first conductive layers in rows or columns, each pair of the second conductive layers and the first conductive layers coupled to the each pair of the second conductive layers, respectively, forming electrodes of a capacitor.

Abstract: The present invention provides a socket by which a capacitor element can be produced without causing contamination of chemical conversion treatment liquid or semiconductor layer forming liquid even if the chemical conversion treatment liquid or the semiconductor layer forming liquid has a corrosive property, and a lead wire of a positive electrode can be stably retained even if diameters of the lead wires are difference. The socket (1) of the present invention is provided with a conductive socket body portion (2) having an insertion port, a resin insulation portion (5) covering a part of the socket body portion (2) so as not to close an insertion port (37), and a resin coating portion (3) coating at least the insertion portion (37) of the socket body portion (2).

Abstract: A thin film transistor array substrate capable of reducing degradation of a device due to degradation of an oxide semiconductor pattern and a method of fabricating the same are provided. The thin film transistor array substrate may include an insulating substrate on which a gate electrode is formed, a gate insulating film formed on the insulating substrate, an oxide semiconductor pattern disposed on the gate insulating film, an anti-etching pattern formed on the oxide semiconductor pattern, and a source electrode and a drain electrode formed on the anti-etching pattern. The oxide semiconductor pattern may include an edge portion positioned between the source electrode and the drain electrode, and the edge portion may include at least one conductive region and at least one non-conductive region.

Abstract: Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element at a location other than between the memory element and the switch element. A lateral dimension of the middle electrode is different than a lateral dimension of the outside electrode.

Abstract: The present invention is capable of suppressing a variation in the characteristics of a semiconductor device. In a conductor pattern CPA and a conductor pattern CPB arranged so as to run side by side with each other, the conductor pattern CPA is divided into a first portion P1 (A) and a second portion P2 (A), and the conductor pattern CPB is also divided into a first portion P1 (B) and a second portion P2 (B). The first portion P1 (A) of the conductor pattern CPA and the second portion P2 (B) of the conductor pattern CPB are formed by first patterning using the same first mask, while the second portion P2 (A) of the conductor pattern CPA and the first portion P1 (B) of the conductor pattern CPB are formed by second patterning using the same second mask.

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device has a laminated insulating film formed above a lower-layer inductor. This laminated insulating film includes a first polyimide film, and a second polyimide film formed on the first polyimide film and having a second step between the first polyimide film and the second polyimide film. An upper-layer inductor is formed on the laminated insulating film. Since such a laminated structure of the first and second polyimide films is adopted, the film thickness of the insulating film between the lower-layer and upper-layer inductors can be increased, so that withstand voltage can be improved. Further, the occurrence of a depression or peeling-off due to defective exposure can be reduced, and step disconnection of a Cu (copper) seed layer or a plating defect due to the step disconnection can also be reduced.

Abstract: In one general aspect, a semiconductor processing method can include forming an N-type silicon region disposed within a P-type silicon substrate. The method can also include forming a field oxide (FOX) layer in the P-type silicon substrate where the FOX layer includes an opening exposing at least a portion of the N-type silicon region. The method can further include forming a reduced surface field (RESURF) oxide (ROX) layer having a first portion disposed on the exposed N-type silicon region and a second portion disposed on the FOX layer where the ROX layer includes a first dielectric layer in contact with the exposed N-type silicon region and a second dielectric layer disposed on the first dielectric layer. The method can further include forming a doped polysilicon layer having a first portion disposed on the first portion of the ROX layer and a second portion disposed on the second portion of the ROX layer.

Abstract: A device for one-time-programmable (OTP) memory may include a capacitor formed by a conductive layer, an oxide layer, and a semiconductor well, and a diode that is formed after programing the device. The device may be programmable by applying a voltage between the conductive layer and the semiconductor well. The applied voltage may be capable of rupturing the oxide layer at one or more points. The conductive layer, the oxide layer, and the semiconductor well may be native CMOS process formations.

Abstract: The semiconductor device fabrication method of the present invention includes: laminating a plurality of amorphous silicon films on a semiconductor substrate, forming through-holes that pass through the plurality of amorphous silicon films, and subjecting the plurality of amorphous silicon films 301 that include the through-holes to an etching process that uses an alkaline aqueous solution; wherein the plurality of amorphous silicon films is formed to include a first amorphous silicon film and a second amorphous silicon film in which the rate of etching by using the alkaline aqueous solution is slower than that of the first amorphous silicon film and the first amorphous silicon film is interposed between the semiconductor substrate and the second amorphous silicon film.

Abstract: An improved eFuse and method of fabrication is disclosed. A cavity is formed in a substrate, which results in a polysilicon line having an increased depth in the area of the fuse, while having a reduced depth in areas outside of the fuse. The increased depth reduces the chance of the polysilicon line entering the fully silicided state. The cavity may be formed with a wet or dry etch.

Abstract: A resistive random access memory cell formed in an integrated circuit includes first and second resistive random access memory devices, each including an anode and a cathode. The anode of the second resistive random access memory device is connected to the anode of the first resistive random access memory device. A programming transistor has a first source/drain terminal connected to a programming potential node, a second source/drain terminal connected to the anodes of the first and second resistive random access memory devices, and a gate connected to a program-enable node.

Abstract: An e-fuse is provided in one area of a semiconductor substrate. The E-fuse includes a vertical stack of from, bottom to top, base metal semiconductor alloy portion, a first metal semiconductor alloy portion, a second metal semiconductor portion, a third metal semiconductor alloy portion and a fourth metal semiconductor alloy portion, wherein the first metal semiconductor alloy portion and the third metal semiconductor portion have outer edges that are vertically offset and do not extend beyond vertical edges of the second metal semiconductor alloy portion and the fourth metal semiconductor alloy portion.

Abstract: Some embodiments include methods of forming memory cells. A stack includes ovonic material over an electrically conductive region. The stack is patterned into rails that extend along a first direction. The rails are patterned into pillars. Electrically conductive lines are formed over the ovonic material. The electrically conductive lines extend along a second direction that intersects the first direction. The electrically conductive lines interconnect the pillars along the second direction. Some embodiments include a memory array having first electrically conductive lines extending along a first direction. The lines contain n-type doped regions of semiconductor material. Pillars are over the first conductive lines and contain mesas of the n-type doped regions together with p-type doped regions and ovonic material. Second electrically conductive lines are over the ovonic material and extend along a second direction that intersects the first direction.

Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.

Abstract: A doped fullerene-based conductive material can be used as an electrode, which can contact a dielectric such as a high k dielectric. By aligning the dielectric with the band gap of the doped fullerene-based electrode, e.g., the conduction band minimum of the dielectric falls into one of the band gaps of the doped fullerene-based material, thermionic leakage through the dielectric can be reduced, since the excited electrons or holes in the electrode would need higher thermal excitation energy to overcome the band gap before passing through the dielectric layer.

Abstract: An ESD protection device is manufactured such that its ESD characteristics are easily adjusted and stabilized. The ESD protection device includes an insulating substrate, a cavity provided in the insulating substrate, at least one pair of discharge electrodes each including a portion exposed in the cavity, the exposed portions being arranged to face each other, and external electrodes provided on a surface of the insulating substrate and connected to the at least one pair of discharge electrodes. A particulate supporting electrode material having conductivity is dispersed between the exposed portions of the at least one pair of discharge electrodes in the cavity.

Abstract: This disclosure provides systems, methods and apparatus for combining devices deposited on a first substrate, with integrated circuits formed on a second substrate such as a semiconducting substrate or a glass substrate. The first substrate may be a glass substrate. The first substrate may include conductive vias. A power combiner circuit may be deposited on a first side of the first substrate. The power combiner circuit may include passive devices deposited on at least the first side of the first substrate. The integrated circuit may include a power amplifier circuit disposed on and configured for electrical connection with the power combiner circuit, to form a power amplification system. The conductive vias may include thermal vias configured for conducting heat from the power amplification system and/or interconnect vias configured for electrical connection between the power amplification system and a conductor on a second side of the first substrate.

Abstract: A method of fabricating a semiconductor device with capacitors may include forming a mold structure on a lower structure, patterning the mold structure to form a plurality of holes exposing the lower structure, forming a protection layer on sidewalls of the mold structure exposed by the holes, forming lower electrodes in the holes provided with the protection layer, removing the mold structure to expose the protection layer, removing the protection layer to expose sidewalls of the lower electrodes, and sequentially forming a dielectric film and an upper electrode on the lower electrodes.

Abstract: A semiconductor device includes a semiconductor substrate divided into a cell region and a peripheral circuit region defined in a first direction, wherein the peripheral circuit region is divided into a first region and a second region defined in a second direction substantially orthogonal to the first direction; gate lines formed over the semiconductor substrate in the cell region and arranged in the second direction; and a capacitor including lower electrodes over the semiconductor substrate, a dielectric layer and an upper electrode, wherein the lower electrodes in the first and second regions, separated from each other in the first direction and coupled to each other in the first region, the dielectric layer is formed along surfaces of the lower electrodes in the second region, and the upper electrode is formed over the dielectric layer.

Abstract: A tunable buffer circuit has a first tunable buffer cell receiving an input signal. A first transmission line is coupled to the first tunable buffer cell. A second tunable buffer cell is coupled to the first transmission line. A center frequency and bandwidth of the second tunable buffer cell is matched to a center frequency and bandwidth of the first tunable buffer cell to achieve low phase noise with low power. Additional transmission lines and tunable buffer cells can be cascaded in the tunable buffer circuit. Each tunable buffer cell has first and second transistors including first and second conduction terminals and control terminal coupled for receiving the input signal. An inductor and tunable capacitor are coupled between the first conduction terminals of the first and second transistor. A digital signal adjusts the tunable buffer cells in response to an RSSI which monitors the output for proper signal strength.

Abstract: Methods and systems for a metal finger capacitor with a triplet repeating sequence incorporating a metal underpass may comprise repeating triplet capacitors integrated on a semiconductor die. The capacitors may comprise a first set of interconnected metal fingers comprising a first terminal of a first capacitor, a second set of interconnected metal fingers comprising a first terminal of a second capacitor, and a third set of interconnected metal fingers comprising a common node that surrounds the first and second sets of interconnected metal fingers. The common node may comprise a second terminal of the capacitors. A repeating pattern of fingers may be: (third set/second set/third set/first set . . . ). The repeating pattern of metal fingers may be arranged in two parallel rows to mitigate variations in the semiconductor die. The interconnected metal fingers may comprise first and second metal layers formed on the semiconductor die.

Abstract: A semiconductor device includes: a multilayer wiring layer located over a substrate and in which multiple wiring layers configured by a wiring and an insulating layer are stacked; a memory circuit which is formed in a memory circuit region in the substrate and has a capacitance element embedded in a concave part located in the multilayer wiring layer; a logic circuit which is formed in a logic circuit region in the substrate; an upper part coupling wiring which is stacked over the capacitance element configured by a lower part electrode, a capacitor insulating film and an upper part electrode; and a cap layer which is formed on the upper surface of the wiring configuring the logic circuit. The upper surface of the upper part coupling wiring and the upper surface of the cap film are provided on the same plane.

Abstract: A manufacturing method of an inductor structure includes the following steps. A protection layer is formed on a substrate, such that bond pads of the substrate are respectively exposed form protection layer openings of the protection layer. A conductive layer is formed on the bond pads and the protection layer. A patterned first photoresist layer is formed on the conductive layer. Copper bumps are respectively formed on the conductive layer located in the first photoresist layer openings. A patterned second photoresist layer is formed on the first photoresist layer, such that at least one of the copper bumps is exposed through second photoresist layer opening and the corresponding first photoresist layer opening. A diffusion barrier layer and an oxidation barrier layer are formed on the copper bump. The first and second photoresist layers, and the conductive layer not covered by the copper bumps are removed.

Abstract: A ferroelectric capacitor formed above a semiconductor substrate includes a lower electrode, a dielectric film (ferroelectric film) having ferroelectric characteristics, and an upper electrode. The upper electrode includes a conductive oxide film made of a ferroelectric material to which conductivity is provided by adding a conductive material such as Ir, and the conductive oxide film is in contact with the dielectric film.

Abstract: A method for fabricating a capacitor includes: forming a first silicon layer over a semiconductor substrate, where the first silicon layer is doped with a dopant; forming an undoped second silicon layer over the first silicon layer; forming an opening by etching the second silicon layer and the first silicon layer; forming a storage node in the opening; and removing the first silicon layer and the second silicon layer.

Abstract: Some embodiments include methods of forming memory cells in which a metal oxide material is formed over a first electrode material, an oxygen-sink material is formed over and directly against the metal oxide material, and a second electrode material is formed over the oxygen-sink material. The second electrode material is of a different composition than the oxygen-sink material. The metal oxide material is treated to transfer oxygen from a region of the metal oxide material to the oxygen-sink material and thereby subdivide the metal oxide material into at least two regions, with one of the regions nearest the oxygen-sink material being relatively oxygen depleted relative to another of the regions.

Abstract: A metal insulator metal (MIM) capacitor includes a base layer and a copper bulk layer in the base layer. The MIM capacitor further includes an etch stop layer over the base layer and the copper bulk layer and an oxide-based dielectric layer over the etch stop layer. The MIM capacitor further includes a capacitor bottom layer over the oxide-based dielectric layer, an insulator layer over the capacitor bottom layer, and a capacitor top layer over the insulator layer.

Abstract: Some novel features pertain to a semiconductor device that includes a substrate, a first cavity that traverses the substrate. The first cavity is configured to be occupied by a interconnect material (e.g., solder ball). The substrate also includes a first metal layer coupled to a first side wall of the first cavity. The substrate further includes a first integrated passive device (IPD) on a first surface of the substrate, the first IPD coupled to the first metal layer. In some implementations, the substrate is a glass substrate. In some implementations, the first IPD is one of at least a capacitor, an inductor and/or a resistor. In some implementations, the semiconductor device further includes a second integrated passive device (IPD) on a second surface of the substrate. The second IPD is coupled to the first metal layer.

Abstract: An integrated circuit includes isolation capacitors which include a silicon dioxide dielectric layer and a polymer dielectric layer over the layer of silicon dioxide. The silicon dioxide dielectric layer and the polymer dielectric layer extend across the integrated circuit. Top plates of the isolation capacitors have bond pads for wire bonds or bump bonds. Bottom plates of the isolation capacitors are connected to components of the integrated circuit. Other bond pads are connected to components in the integrated circuit through vias through the silicon dioxide dielectric layer and the polymer dielectric layer.

Abstract: In accordance with an embodiment, a semiconductor component, includes a common mode filter monolithically integrated with a protection device. The common mode filter includes a plurality of coils and the protection device has a terminal coupled to a first coil and another terminal coupled to a second coil.