Abstract: A method for forming a field oxide of a semiconductor device and the semiconductor device. In order to form the field oxide, first, an element isolation mask is constructed on a semiconductor substrate. Then, a nitride spacer is formed at the side wall of the mask. At this time, a nitrogen-containing polymer is produced on the field region. The exposed region of the semiconductor substrate is oxidized at a temperature of 1,050-1,200.degree. C. to grow a recess-oxide while transforming the nitrogen-containing polymer into a nitride. Thereafter, the recess oxide is removed, together with the nitride, to create a trench in which the field oxide is formed through thermal oxidation. Therefore, the method can prevent an FOU phenomenon upon the growth of a field oxide and improve the field oxide thinning effect, thereby bringing a significant improvement to the production yield and the reliability of a semiconductor device.

Abstract: A static random access memory cell comprising a first invertor including a first p-channel pullup transistor, and a first n-channel pulldown transistor in series with the first p-channel pullup transistor; a second invertor including a second p-channel pullup transistor, and a second n-channel pulldown transistor in series with the second n-channel pullup transistor, the first invertor being cross-coupled with the second invertor, the first and second pullup transistors sharing a common active area; a first access transistor having an active terminal connected to the first invertor; a second access transistor having an active terminal connected to the second invertor; and an isolator isolating the first pullup transistor from the second pullup transistor.

Abstract: A method for controlling the mask bias of a photoresist mask is described whereby a polymer coating is formed over the patterned photoresist mask immediately prior to etching the mask's pattern into a subjacent layer. The polymer coating is formed by treatment of the photoresist mask with a plasma, struck in within a reactive ion etching tool, in a gas mixture containing chlorine and helium. The etch durability and the thickness of the polymer coating determines the dimensional bias of the mask with respect to the pattern formed in the subjacent layer. By varying the polymer formation parameters a controllable etch bias between -0.01 and +0.03 microns can be achieved. This capability is particularly useful for patterning in integrated circuits where critical dimensions approach the resolution limits of the photolithography. The method is applied to the patterning of a silicon nitride hardmask employed in the formation of field oxide isolation (LOCOS) where a zero bias condition is achieved.

Abstract: In a DRAM adopting a self-aligned contact structure, an opening portion of predetermined size is formed in advance in an insulation film which surrounds an on-field gate electrode formed on an element isolating insulation film. The on-field gate electrode contacts a gate contact through the opening portion. A contact hole for the gate contact can thus be formed in self-alignment as can be the contact holes for a bit-line contact and an active contact. Consequently, the contact hole for the gate contact reaching the on-field gate can be formed simultaneously with the contact holes for the bit-line contact and active contact, thereby greatly reducing the number of manufacturing steps.

Abstract: In forming an element isolating region in a silicon semiconductor layer of an SOI substrate, a silicon nitride film of a predetermined thickness is deposited over an oxide film formed on a SOI layer. The silicon nitride film is patterned in a design size of active regions, and side walls of a silicon nitride film are formed on the side surfaces of the patterned silicon nitride film. A first LOCOS process is carried out using the nitride film as an oxidation mask. A LOCOS film formed by the first LOCOS process is removed to form narrower concavities under the side walls. Then, another silicon nitride film is deposited, and is removed leaving portions thereof forming the concavities. Then, a second LOCOS process is carried out to form a LOCOS film as an element isolating region. The second LOCOS process uses the oxidation mask having the narrow cavities, so that stress at the boundary of the active region and the element isolation region is reduced, and the growth of bird's beaks can be suppressed.

Abstract: The present invention proposes a method for fabricating field oxide regions for isolation by an improved poly-buffered local oxidation of silicon (PBLOCOS) process. A polysilicon layer is utilized to reduce the bird's beak, and a thin thermal oxide film is formed on the buffered polysilicon film to prevent pitting formation. Forming a thin pad oxide and a silicon layer, a thermal oxidation is carried out to grow another pad oxide on the silicon layer and crystallize the silicon into polysilicon. The buffered layer of stacked oxide-polysilicon-oxide layer is thus formed. The silicon nitride layer is then deposited on the stacked buffered layer and the active areas are defined. A thermal oxidation is now performed, and thick field oxide regions are grown. After the masking nitride layer and the stacked buffered layer are stripped, the MOS devices are fabricated, and thus complete the present invention.

Abstract: An isolation method in the fabrication process of a semiconductor device is provided. The method forms an oxide layer as a buffer layer for reducing stress through chemical vapor deposition (CVD). By the method, a first pad oxide layer and a silicon nitride layer are formed on a semiconductor substrate, and then an silicon nitride layer pattern is formed by patterning, and undercuts are formed in the first pad oxide layer pattern. Subsequently, a second pad oxide layer is formed on the entire surface of the semiconductor substrate through CVD, and then spacers are formed on the sidewalls of both the patterned first pad oxide layer and silicon nitride layer and a field oxide layer is formed through thermal oxidation. Alternatively, a silicon layer is deposited without the spacers to form the field oxide layer. The second pad oxide layer is a buffer layer for buffering stress during formation of the field oxide layer.

Abstract: A method of fabricating semiconductor memory devices which has sufficient cell isolation to achieve miniaturization at the 0.3 to 0.4 .mu.m level. In the semiconductor memory devices of the present application miniaturization is achieved by removing overlap allowances between each gate and each LOCOS and those between each diffusion layer and each LOCOS used to separate the above-described semiconductor memory elements.

Abstract: A method for forming field oxide comprises the steps of forming a pad oxide layer over a semiconductor substrate, then forming a silicon layer over the pad oxide layer. A patterned mask is formed over the silicon layer and the silicon layer is etched to form openings in the silicon layer. Next, a blanket nitride layer is formed over the silicon and within the openings, and the nitride layer is then planarized to remove the nitride which overlies the silicon which leaves the nitride in the openings. Subsequent to the step of planarizing the nitride, the silicon layer is removed thereby forming openings in the nitride layer. The substrate is oxidized at the openings in the nitride layer to form field oxide from the substrate.

Abstract: The present invention provides methods of manufacturing a field oxide isolation structure over a semiconductor. One of the methods includes the steps of: (1) depositing a first stack-nitride sublayer over the semiconductor at a first deposition rate and (2) subsequently depositing a second stack-nitride sublayer over the first stack-sublayer at a second deposition rate that is either greater or less than the first deposition rate. The first and second deposition rates provide first and second stack-nitride sublayers that cooperate to form a relatively thin, uniform thickness of the field oxide isolation structure over the semiconductor and provide a stress-accommodating system within the semiconductor. The varying rates of deposition and accompanying changes in mixture ratio, produce a stack that is better able to absorb stress, has greater uniformity and is far less subject to the disadvantageous phenomenon of stack-lifting, particularly encountered in semiconductor having a PADOX layer deposited thereon.

Abstract: Disclosed are an isolation film of a semiconductor device and a method for fabricating the same, which prevent the isolation film from being damaged due to misalignment when forming a contact hole in a region adjacent to the isolation film, to ensure stable effective isolation distance. The isolation film of a semiconductor device includes a semiconductor substrate, a lower isolation film formed in the semiconductor substrate, and an upper isolation film formed on the lower isolation film, with a material having etching selectivity different from the lower isolation film.

Abstract: A method is disclosed for forming narrow thermal silicon dioxide side isolation regions in a semiconductor substrate and MOS or CMOS semiconductor devices fabricated by this method. A thin stress relief layer is used in conjunction with a polysilicon buffering stress relief layer on the surface of a semiconductor substrate prior to the field oxidation process to restrict lateral silicon dioxide expansion thereby permitting the creation of narrow thermal silicon dioxide side isolation regions in the semiconductor substrate. A silicon dioxide layer is also used between an amorphous polysilicon (buffering stress relief) layer and a silicon nitride layer to function as an oxide cap, to avoid undesired pitting of the amorphous polysilicon layer, and to avoid interaction between the silicon nitride and amorphous polysilicon layers in areas of high stress.

Abstract: A method of fabricating a semiconductor device and the device which includes initially providing a layer of silicon having a thin oxide layer thereon and a patterned layer of a masking material not permeable to at least selected oxygen-bearing species and having a sidewall disposed over said oxide layer to provide an exposed intersection of the masking material and the oxide layer. An oxygen-bearing species conductive path is then formed on the sidewall of the masking material extending to the exposed intersection for conducting the selected oxygen-bearing species. A sidewall layer of a material different from the conductive path is formed on the conductive path. An oxygen-bearing species is then applied to the exposed intersection through the path and a thick oxide surrounding the masking material is fabricated concurrently or as a separate step. The masking material is preferably silicon nitride, the path is preferably silicon oxide and the sidewall layer is preferably silicon nitride.

Abstract: A novel design of an oxidation mask for improved control of birds beak and more specifically for tailoring and smoothing the field oxide isolation profile in the vicinity of the birds beak. The mask design is particularly advantageous for narrow field isolation spacings found in sub half-micron integrated circuit technology. The mask uses a thin tapered silicon nitride foot along its lower edge to allow nominal expansion of the oxide during the early stages of oxidation, thereby permitting in-situ stress relief as well as a smoothing of the oxide profile. The taper of the foot provides a gradual increase in mask stiffness as oxidation proceeds under the mask edge, allowing greatest flexibility during the early rapid growth period followed by increasing stiffness during the later stages when the growth rate has slowed, thereby inhibiting the penetration of birds beak. Shear stresses responsible for dislocation generation are reduced by as much as fifty fold.

Abstract: A technique for reducing active area encroachment (birdsbeak) by using a polysilicon hard mask combined with both wet and dry etch for the isolation nitride. This process forms a thinner layer of nitride adjacent the openings for oxide growth, which reduces stress at the silicon/nitride interface. The advantages include control over birdsbeak, reliable gate oxide quality, low junction leakage current, an improved active area, improved isolation, low peripheral junction leakage, and higher field transistor threshold voltage.

Abstract: In a method of manufacturing a semiconductor device, diffusion layers are formed on a semiconductor substrate using a mask. The diffusion layers has a conductive type different from that of the semiconductor substrate. Then, insulating films are formed on the diffusion layers using the mask and the mask is removed. Subsequently, a floating gate is formed between the insulating films on the semiconductor substrate via a first gate insulating film. Next, a second gate insulating film is formed on the floating gate and the insulating films, and a word line is formed to cover the floating gate via the second gate insulating film.

Abstract: A method for forming field oxide isolation regions using oxygen implantation is described. An oxidation resistant layer such as silicon nitride is formed on a silicon substrate, and acts as an oxidation mask. An opening is then formed in the nitride layer, where field oxide is desired. In one embodiment of the invention, oxygen is implanted into this opening, followed by thermal oxidation. In a second embodiment of the invention, the opening is thermally oxidized, followed by a deep oxygen implant and anneal. Encroachment of the field oxide under the nitride layer is decreased, resulting in a minimum "birds' beak" length.

Abstract: A method of preparing a semiconductor wafer includes the step of forming first and second layers of a first material on opposing respective first and second faces of the semiconductor wafer. The second layer of the first material is then removed from the second face of the semiconductor wafer. More particularly, the first material can be polysilicon. Warping of the semiconductor wafer can thus be reduced.

Abstract: A method for making self-aligned sub-micrometer bipolar transistors and FETs on a substrate for BiFET and BiCMOS circuits was achieved using a novel LOCOS structure as a self-aligned implant mask. This LOCOS structure uses a silicon nitride mask comprised of stripes with well defined widths and spacings to form a punchthrough oxide mask of varying thicknesses over the emitter, base, and collector of the bipolar transistor, while providing a thick field oxide elsewhere on the substrate. The oxide mask serves as a self-aligned implant mask for implanting the emitter, base, and collector of the bipolar transistor. The nitride mask can be patterned concurrently to form an implant mask for the FET. A series of ion implants is then used to form the emitter, base, and collector without requiring separate photoresist masks. An array of nitride stripes with well defined widths and spacings can be used to make larger transistors, such as bipolar power transistors.

Abstract: A semiconductor processing method of forming field oxide regions includes, a) providing a sacrificial pad oxide layer over a semiconductor substrate; b) providing a Ge.sub.x Si.sub.y layer over the pad oxide layer, where x is greater than 0.2, y is from 0 to 0.8, and x+y=1.0; c) providing a patterned nitride oxidation masking layer over the Ge.sub.x Si.sub.y layer to define at least one pair of adjacent nitride masking blocks overlying desired active area regions of the substrate; d) etching exposed portions of the Ge.sub.x Si.sub.y layer and thereby defining exposed sidewall edges of the Ge.sub.x Si.sub.y layer; e) providing an oxidation restriction layer over the respective Ge.sub.x Si.sub.y sidewalls, the oxidation restriction layer restricting rate of oxidation of the Ge.sub.x Si.sub.y layer from what would otherwise occur if the oxidation restriction layer were not present; f) oxidizing portions of the substrate unmasked by the masking layer to form at least one pair of adjacent SiO.sub.

Abstract: A method for forming a field oxide film of a highly integrated semiconductor device, in which an annealing step is carried out during a field oxide film formation step for growing the field oxide film adapted to isolate elements of the semiconductor device. By the annealing step, it is possible to prevent a stress concentration phenomenon from occurring in a semiconductor substrate on which the field oxide film is formed, thereby reducing or eliminating a field oxide thinning phenomenon.

Abstract: A semiconductor device comprising at least two thin film transistors on a substrate having an insulating surface thereon, provided that the thin film transistors are isolated by oxidizing the outer periphery of the active layer of each of the thin film transistors to the bottom to provide an oxide insulating film.

Abstract: A method for use in the fabrication of semiconductor devices in accordance with the present invention includes providing a silicon nitride region and oxidizing a region of material in proximity to the silicon nitride region. The silicon nitride region is then hydrogenated and thereafter, the hydrogenated silicon nitride region is removed. The hydrogenation step may include immersing the silicon nitride region into pressurized boiling water and/or treating the silicon nitride region with pressurized water vapor and the removing step includes removing the hydrogenated silicon nitride region with hot phosphoric acid. The method may be used in a local oxidation of silicon process. Further, the oxidation of the material and the hydrogenation of the silicon nitride may be performed in the same pressurizable unit.

Abstract: A plasma etch method for forming a patterned silicon nitride layer within an integrated circuit. There is first provided a substrate having formed thereover a blanket silicon nitride layer. There is then formed upon the blanket silicon nitride layer a patterned photoresist layer. Finally, there is etched through a plasma etch method while employing the patterned photoresist layer as an etch mask layer the blanket silicon nitride layer to form a patterned silicon nitride layer. The plasma etch method employs an etchant gas composition comprising a perfluorocarbon etchant gas, a hydrofluorocarbon etchant gas and an oxygen etchant gas at a perfluorocarbon etchant gas flow rate, a hydrofluorocarbon etchant gas flow rate and an oxygen etchant gas flow rate which yields substantially no plasma etch bias of the patterned silicon nitride layer with respect to the patterned photoresist layer.

Abstract: A new polysilicon-buffered field isolation process provides reduced stress during field oxidation and reduced bird's beak. Prior to forming the LOCOS masking stack conventionally used for field isolation, a polysilicon buffer layer is first formed on the semiconductor wafer. The polysilicon buffer layer relieves stress between the masking stack and semiconductor wafer similar to conventional Poly-buffered LOCOS processes, but additionally provides sacrificial silicon into which the bird's beak region extends. Subsequent deprocessing of mask and buffer layers removes a significant portion of the bird's beak region, thereby providing active areas having improved physical and electrical characteristics.

Abstract: A novel anisotropic plasma etching process for forming patterned silicon nitride (Si.sub.3 N.sub.4) layers with improved critical dimension (CD) control while minimizing the Si.sub.3 N.sub.4 footing at the bottom edge of the Si.sub.3 N.sub.4 pattern is achieved. A pad oxide/silicon nitride layer is deposited on a silicon substrate. A patterned photoresist layer is used as an etching mask for etching the silicon nitride layer. By this invention, a chlorine (Cl.sub.2) breakthrough plasma pre-etch forms a protective polymer layer on the sidewalls of the patterned photoresist and removes residue in the open areas prior to etching the Si.sub.3 N.sub.4. The Si.sub.3 N.sub.4 is then aniso-tropically plasma etched using an etch gas containing SF.sub.6. The polymer layer, formed during the Cl.sub.2 pre-etch, reduces the lateral recessing of the photoresist when the Si.sub.3 N.sub.4 is etched, and results in improved patterned Si.sub.3 N.sub.4 profiles with reduced CD bias, and minimizes Si.sub.3 N.sub.

Abstract: A method for forming a field oxide of a semiconductor device is disclosed, which takes advantage of wet oxidation at an early stage of field oxidation to prevent the ungrowth of field oxide and dry oxidation at a later stage of field oxidation to make the slope of field oxide positive, thereby improving the production yield and the reliability of semiconductor device.

Abstract: A semiconductor device is disclosed, together with a fabricating method therefor. The semiconductor device has an etch barrier structure, made with SiN or SiON, which is formed on an element-isolating region alongside an active region. Although there is an alignment error which causes the element-isolating region to be exposed, the etch barrier structure protects the element-isolating region from being etched when carrying out the etching processes for contact holes in a semiconductor memory cell. Thus, while preventing the deterioration of element-isolation properties, the etch barrier structure can affords a larger allowable alignment error in the etching processes for contact holes, so it is possible to make a small active region and thus, highly integrate semiconductor devices.

Abstract: Disclosed is a method of manufacturing a semiconductor device having a reliable element isolation insulating film on an SOI substrate having an SOI layer. That is, the step of forming a semiconductor device on an SOI substrate includes the steps of sequentially depositing a silicon oxide film and an insulating film resistant to oxidation on the surface of the SOI layer of the SOI substrate to form a stacked film, etching the stacked film into a predetermined pattern shape to expose the SOI layer, selectively forming a thin silicon layer on the exposed SOI layer, and selectively thermally oxidizing the thin silicon layer and the exposed SOI layer by using the stacked film as a thermal oxidization mask. In the thermal oxidization step, all the thin silicon layer and the exposed SOI layer are thermally oxidized to be converted into an element isolation insulating film, and the element isolation insulating film is formed in contact with a buried oxide film below the region.

Abstract: The present invention provides a fabrication process for fabricating an integrated circuit substrate structure having LOCOS isolation areas formed such that oxidation encroachment at an active surface region patterned on the substrate is less than 0.1 .mu.m. The fabrication process includes various process steps for forming a 0.75 .mu.m. to 1.0 .mu.m layer of silicon dioxide (SiO.sub.2) over thin layers of silicon dioxide (0.01 .mu.m. to 0.05 .mu.m) and silicon nitride (0.05 .mu.m. to 0.10 .mu.m) over a surface region of the substrate to form a protective stack/passivation layers over a surface region of the silicon substrate. The protected substrate surface region is useable for fabricating a microelectronic circuit device, such as a MOS transistor, or a flash memory device. Adjacent the protective stack, a silicon nitride spacer region is formed to effectively widen the protected substrate surface region.

Abstract: A semiconductor process in which oxygen is selectively implanted into isolation regions of a semiconductor substrate and subsequently annealed to form isolation structures within the isolation regions. Preferably, a semiconductor substrate is provided and a pad oxide layer is deposited on the semiconductor substrate. A barrier layer is then deposited on the pad oxide layer and a photoresist layer is formed over the barrier layer and patterned to form a photoresist mask. The photoresist mask is aligned over active regions of the semiconductor substrate. An oxygen bearing species is then introduced to an isolation region of the semiconductor substrate. The isolation region is laterally displaced between the active regions. The introducing of the oxygen bearing species into the isolation region results in the formation of an oxygenated region of the semiconductor substrate.

Abstract: A method for forming a field oxide isolation regions of a memory array is described. The field isolation regions comprise a rectangular array of oxide islands. The oxide islands are formed by a two mask process wherein the first mask is a LOCOS hardmask which defines an array of parallel field oxide stripes. The field oxide stripes are thermally grown by a LOCOS oxidation process. A second mask, which has an array of parallel stripes perpendicular to the field oxide stripes is then patterned over the wafer. The stripes of the second mask expose a plurality of narrow sections of the field oxide stripes which are then etched by a directional plasma etch having a high selectivity of silicon oxide over silicon. The anisotropic etch segments each of the longer oxide stripes into a string of islands space apart by a narrow gap through which a robust common source line passes unencumbered by birdsbeak oxide.

Abstract: A method of fabricating a semiconductor device, including the steps of (a) forming a channel at a surface of a semiconductor substrate only in the center of a region X which physically and electrically isolates adjacent regions Y in each of which a device is to be fabricated, and (b) forming a silicon oxide layer over the region X for physically and electrically isolating the adjacent regions Y from each other. The method suppresses dimensional shift and occurrence of a stress, and further makes it difficult for the reverse narrow channel effect to occur only by adding the small number of additional steps thereto.

Abstract: A method for increasing the thickness of field oxide layer is provided. At first, a layer of pad oxide and a layer of silicon nitride mask are defined on a semiconductor substrate, and then a field oxide layer, which isolates active device regions, is formed. After the layer of pad oxide and the layer of silicon nitride are removed, a layer of silicon oxide is formed overlying the field oxide layer. The mentioned silicon oxide layer can increase the thickness of field oxide layer for effectively isolating active device regions without enlarging Bird's Beak. The present invention can also effectively improve the Gate Coupling Ratio in a Flash EEPROM.

Abstract: A method for forming an isolation region in an integrated circuit is disclosed. The method includes forming a pad layer on a semiconductor substrate, and forming an oxidation masking layer on the pad layer, wherein the pad layer relieves stress from the oxidation masking layer. Next, portions of the oxidation masking layer and the pad layer are patterned and etched. A first oxide layer is thermally grown on the substrate, and a second oxide spacer is formed on a sidewall of the pad layer and the oxidation masking layer. After forming a nitride spacer on a surface of the second oxide spacer, the substrate is thermally oxidized to form the isolation region in the substrate.

Abstract: A semiconductor processing method of forming field isolation oxide relative to a silicon substrate includes, i) rapid thermal nitridizing an exposed silicon substrate surface to form a base silicon nitride layer on the silicon substrate; ii) providing a silicon nitride masking layer over the nitride base layer, the base and masking silicon nitride layers comprising a composite of said layers of a combined thickness effective to restrict appreciable oxidation of silicon substrate thereunder when the substrate is exposed to LOCOS conditions; and iii) exposing the substrate to oxidizing conditions effective to form field isolation oxide on substrate areas not masked by the base and masking silicon nitride layers composite.

Abstract: A method for forming buried oxide regions below a single crystal semiconductor layer incorporating the steps of forming epitaxial layers having different rates of oxidation with the lower layer having a faster rate of oxidation and oxidizing the layers through an opening in a mask. A plurality of oxide isolated FET's may be formed. The invention reduces the problem of source/drain parasitic capacitance and short channel effects while isolating FET's and eliminating floating body effects of an FET by selectively oxidizing semiconductor layers.

Abstract: A method of fabricating a MOS device with a localized punchthrough stopper. In the process, a dummy layer is employed to define a well for implanting the localized punchthrough stopper. The dummy layer is preferably made of silicon nitride, which has a high etching selectivity with respect to the oxide material forming sidewall spacers of MOS devices. The localized punchthrough stopper is formed at the boundary of the lightly-doped regions and the channel by implanting impurities through the well resulting from the removal of a portion of the dummy layer adjacent to the gate structure.

Abstract: A process for producing a layered structure in which a silicide layer on a silicon substrate is subjected to local oxidation to cause the boundary layer side of the silicide layer to grow into the silicon substrate.

Abstract: A semiconductor device manufacturing method capable of realizing a fine device isolation by stably suppressing the narrow channel effect and the reverse narrow channel effect in an N-channel MOS transistor. A patterned silicon nitride film 102 is formed, and after a P-type ion implanted layer 103 is formed, a field oxide film 105a is formed. In this process, re-distribution of the P-type impurity is caused by segregation, so that a P-type impurity concentration adjusting region 104a is formed at the surface of a P-type silicon substrate 101 in the proximity of a bird's beak of the field oxide film 105a.

Abstract: A method of forming an isolation region exerts no adverse influence upon steps after forming the isolation region and is, besides, capable of forming the isolation region having a narrow isolation width. After a mask has been formed of an oxidationproof material such as Si.sub.3 N.sub.4 on a silicon substrate, a field oxide is formed by effecting selective oxidation in a high-pressure dry oxygen atmosphere. Thereafter, a portion, protruded from the silicon substrate, of the formed field oxide is removed, thereby forming the isolation region.

Abstract: Generation of parasitic transistor in active layer edge is prevented. In an NMOS region of a semiconductor layer (21) on an insulating film (20), boron ions are implanted by rotary oblique injection, using a nitride film (23) and a resist (253a) as mask. In the vicinity of a region for separating element by LOCOS method, that is, only in the edge region of the semiconductor layer (21) as the active layer of NMOS transistor, boron ions are implanted by about 3.times.10.sup.13 /cm.sup.2. After LOCOS oxidation, the impurity concentration is heightened to such a level as the boron ions may not be sucked up into the oxide film.

Abstract: A method of forming a device isolation layer of a semiconductor device includes the steps of forming a first buffer layer on the active region of a semiconductor substrate and forming an oxidation preventive layer on the first buffer layer. A second buffer layer is formed on the semiconductor substrate, and an oxidation preventive side wall is formed on the side parts of the first buffer layer and the oxidation preventive layer. A recess or a trench is formed next to the sidewall, and a device isolation layer is formed in the recess or the trench by oxidation.

Abstract: A semiconductor processing method of forming a static random access memory cell having an n-channel access transistor includes, providing a bulk semiconductor substrate; patterning the substrate for definition of field oxide regions and active area regions for the n-channel access transistor; subjecting the patterned substrate to oxidizing conditions to form a pair of field oxide regions and an intervening n-channel access transistor active area therebetween, the field oxide regions having respective bird's beak regions extending into the n-channel access transistor active area, the n-channel access transistor active area defining a central region away from the bird's beak regions; and conducting a p-type V.sub.T ion implant into the n-channel active area using the field oxide bird's beak regions as an implant mask to concentrate the V.sub.T implant in the central region of the active area.

Abstract: A method is provided for forming an improved device dielectric of a semiconductor integrated circuit, and an integrated circuit formed according to the same. For scaling geometries for use in the submicron regime, a composite dielectric layer used as a device dielectric is formed over a plurality of active areas adjacent to a field oxide region. The composite dielectric layer is formed before the field oxide region is formed and comprises a non-porous silicon nitride layer. The non-porous silicon nitride layer preferably comprises a thin deposited silicon nitride layer overlying a thin nitridized region of the substrate. The silicon nitride layer is partially oxidized during the subsequent formation of a field oxide region between the plurality of active areas. An oxide layer may be formed over the silicon nitride layer before the formation of the field oxide region which will then be densified during the field oxide formation.

Abstract: A first conductor for a field shield and a first insulating film are sequentially formed in a predetermined shape on a major surface of a P-type semiconductor substrate through an insulating film. A third insulating film is formed over the semiconductor substrate so as to cover the first conductor and a second insulating film thereon. The third insulating film is anisotropically etched, so that a sidewall insulating film is formed on sidewalls of the first conductor. Second and third conductors respectively serving as gate electrodes of field effect transistors are formed through a fourth insulating film. n-type impurities are implanted into the major surface of the semiconductor substrate utilizing as masks the first insulating film, the sidewall oxide film, the second conductor and the third conductor and are diffused, to form impurity regions.

Abstract: Disclosed is a device isolation technology for defining active region of a semiconductor device. An oxide is formed on a semiconductor substrate in a first reaction chamber where a first gas containing silicon and a purge gas exist therein. Afterwards, the first temperature of the first reaction chamber is changed to second temperature by injection of a purge gas. A buffer film is formed on the oxide film in the first reaction chamber at the second temperature by injection of a silicon gas. Thereafter, a silicon nitride layer is formed on the buffer film in a second reaction chamber by injecting a second gas containing silicon. Lastly, field oxides are formed by a LOCOS technique through pattering of the three layers and thermal oxidation of exposed portions.

Abstract: A selective oxidation process includes conducting a former phase of an oxidation process employing a thick mask layer to produce an oxide layer having a thickness less than the finished thickness of a desired semiconductor device isolation insulator. Then the thickness of the mask layer is reduced and a latter phase of the oxidation process using the reducing thickness mask layer is performed to produce the desired semiconductor device isolation insulator having the ultimate thickness. The use of both a thick mask layer and a reduced thickness mask layer for various phases of the oxidation process limits both the growth of the bird's beak and the growth of crystalline defects in the bird's beak.

Abstract: An isolation layer forming method for a semiconductor device which prevents damage of an isolation layer due to a misalignment of a mask when a contact hole is formed. An anti-oxidative pattern for exposing an isolation region is formed on a semiconductor substrate, and an undercut portion on a lower sidewall of the anti-oxidative pattern is formed by selectively removing the exposed semiconductor substrate by an isotropic etching process. Thereafter, the isolation layer is formed by an oxidation process so that an edge portion of the isolation layer which is placed in the undercut portion is not exposed to a surface of the semiconductor substrate.

Abstract: Disclosed herein is a method for forming an interconnect line having low conductor line capacitance between devices formed on an integrated circuit.