Abstract: A method for forming a self-align insulation of a passing gate is disclosed. First, a substrate is provided. A deep trench filled with silicon material and a shallow trench isolation adjacent to the deep trench are formed in the substrate. A patterned pad oxide and a patterned hard mask are sequentially formed on the substrate. The patterned pad oxide and the patterned hard mask together define the opening of the deep trench. Then, an oxidation step is carried out to form a first oxide layer serving as the insulation of a passing gate on the top surface of the silicon material of the deep trench. Later, a first Si layer is formed to cover the first oxide layer. Afterwards, the hard mask is removed.

Abstract: A method for forming multiple self-aligned gate stacks, the method comprising, forming a first group of gate stack layers on a first portion of a substrate, forming a second group of gate stack layers on a second portion of the substrate adjacent to the first portion of the substrate, etching to form a trench disposed between the first portion and the second portion of the substrate, and filling the trench with an insulating material.

Abstract: A semiconductor device includes a substrate including a cavity and a first material layer over at least a portion of sidewalls of the cavity. The semiconductor device includes an oxide layer over the substrate and at least a portion of the sidewalls of the cavity such that the oxide layer lifts off a top portion of the first material layer toward a center of the cavity.

Abstract: A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, a first and a second control gate electrode layer, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture, a third and a fourth control gate electrode layer, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on the second tunneling insulating film, a third inter-gate insulating film having an aperture, a fifth and a sixth control gate electrode layer, and a third metallic silicide film; and a liner insulating film directly disposed on a first source and drain region of the memory cell transistor, a second source and drain region of the low voltage transistor, and a third source and drain region

Abstract: The invention enhances the accuracy of an end point detection when an insulation film formed on a semiconductor substrate is dry-etched. Gate layers made of polysilicon are formed, and an end point detection dummy layer made of polysilicon is formed on a LOCOS. After the gate layers and the dummy layer are formed, a TEOS film is formed on a silicon substrate so as to cover the gate layers and the dummy layer. The TEOS film, a thin gate oxide film and a thick gate oxide film are then dry-etched to form sidewalls on the sidewalls of the gate layers and also expose the front surface of the P well of the silicon substrate in a region surrounded by the LOCOS. The end point detection dummy layer helps the end point detection by being exposed during this dry-etching to enhance the accuracy of the end point detection.

Abstract: A method of manufacturing a photodiode sensor and an associated charge transfer transistor includes forming an insulation region on a substrate, forming the diode on a first side of the insulation region with the diode being self-aligned on the insulation region, and replacing the insulation region by a gate of the charge transfer transistor. The invention has particular utility in the manufacture of CMOS or CCD image sensors.

Abstract: The present invention provides a method for manufacturing a semiconductor device, comprising the steps of preparing a substrate having a quartz support substrate and a silicon layer, forming a base or substrate silicon oxide film over the entire upper surface of the silicon layer, forming a silicon nitride film over the entire upper surface of the substrate silicon oxide film by a plasma CVD method, patterning the silicon nitride film thereby to form a mask pattern having a circumferential exposure portion that exposes the substrate silicon oxide film in a circumferential area, a first opening pattern that exposes the substrate silicon oxide film in an element isolation area, and a second opening pattern that exposes the substrate silicon oxide film within a peripheral area, and thermally oxidizing the substrate using the mask pattern as a mask thereby to form an element isolation structure portion in the element isolation area.

Abstract: A method of forming a silicon germanium conduction channel under a gate stack of a semiconductor device, the gate stack being formed on a silicon layer on an insulating layer, the method including growing a silicon germanium layer over said silicon layer and heating the device such that germanium condenses in the silicon layer such that a silicon germanium channel is formed between the gate stack and the insulating layer.

Abstract: There is a method of forming a contact post and surrounding isolation trench in a semiconductor-on-insulator (SOI) substrate. The method comprises etching a contact hole and surrounding isolation trench from an active layer of the substrate to the insulating layer, masking the trench and further etching the contact hole to the base substrate layer, filling the trench and contact hole with undoped intrinsic polysilicon and then performing a doping process in respect of the polysilicon material filling the contact hole so as to form in situ a highly doped contact post, while the material filling the isolation trench remains non-conductive. The isolation trench and contact post are formed substantially simultaneously so as to avoid undue interference with the device fabrication process.

Abstract: A silicon-on-insulator wafer (10). The SOI wafer (10) comprises a top silicon layer (6), a silicon substrate (4), and an oxide insulator layer (2) disposed across the wafer (10) and between the silicon substrate (4) and the top silicon layer (6). The oxide insulator layer (2) has at least one of a contoured top surface (8a, 8b, 8c, 8d, 8e) and a contoured bottom surface (12e). Also provided are processes for manufacturing such a SOI wafer (10).

Abstract: A pad oxide layer is formed on a substrate. A pad nitride layer is formed on the pad oxide layer. The pad nitride layer and the pad oxide layer are patterned. Predetermined portions of the substrate are etched using the pad nitride layer as an etch barrier to thereby form trenches used as device isolation regions. The trenches are filled with an insulation layer to thereby form device isolation regions. The pad nitride layer is removed. Recesses are formed by etching predetermined portions of the pad oxide layer and the substrate. The pad oxide layer is removed. A gate oxide layer is formed on the recesses and on the substrate. Gate structures of which bottom portions are buried in the recesses on the gate oxide layer are formed.

Abstract: Disclosed is a method of manufacturing an isolation layer pattern in a semiconductor device and an isolation layer pattern in a semiconductor device. A device at a low voltage device formation region may be substantially immune to electric fields from a high voltage device formation region. A field insulation film pattern in a low voltage device formation region (e.g. a logic region) may implement a relatively small design rule at an isolation layer pattern. A method of manufacturing an isolation layer pattern in a semiconductor device (e.g. which may embody a device relatively immune to an electric field from a high voltage device formation region) may include field insulation film patterns with a relatively small design rule in a low voltage device formation region (e.g. a logic region).

Abstract: A method for manufacturing a semiconductor device is disclosed. The method includes: forming a LDMOS region, an offset drain MOS region, and a CMOS region; simultaneously forming a first well in the LDMOS region and the offset drain MOS region; simultaneously forming a second well in the first well of the LDMOS region and the CMOS region; and forming a second well in the CMOS region, wherein a depth of the first well is larger than a depth of the second well and the second well is a retrograde well formed by a high energy ion implantation method.

Abstract: One aspect of a semiconductor device includes an active region located in a semiconductor substrate and having an isolation region located therebetween. The active regions have corners adjacent the isolation region. An oxide layer is located over the active regions and the corners, which may also include edges of the active regions, and a ratio of a thickness of the oxide layer over the corners to a thickness of the oxide layer over the active regions ranges from about 0.6:1 to about 0.8:1. A gate is located over the active region and the oxide layer.

Abstract: A vertical transistor with integrated isolation is provided. The vertical transistor includes a vertical semiconductor structure and an isolation layer on a bottom surface of the vertical semiconductor structure. The vertical transistor further includes a plurality of terminals on a top surface of the vertical semiconductor structure.

Abstract: A method by which generation of leak current can be suppressed and also a fine element can be formed by performing element isolation at a temperature at which a glass substrate can be used is provided. The method includes a first step of forming a base film over a glass substrate; a second step of forming a semiconductor film over the base film; a third step of forming, over the semiconductor film, a film preventing oxidation or nitridation of the semiconductor film into a predetermined pattern; and a fourth step of performing element isolation by radical oxidation or radical nitridation of a region of the semiconductor film, which is not covered with the predetermined pattern, at a temperature of the glass substrate lower than a strain point thereof by 100° C. or more, where radical oxidation or radical nitridation is performed over a semiconductor film placed apart from a plasma generation region, in a plasma treatment chamber with an electron temperature within the range of 0.5 to 1.

Abstract: A silicon oxide film formation method includes generating plasma inside a process chamber of a plasma processing apparatus, by use of a process gas having an oxygen ratio of 1% or more, and a process pressure of 133.3 Pa or less; and oxidizing by the plasma a silicon surface exposed inside a recessed part formed in a silicon layer on a target object, thereby forming a silicon oxide film.

Abstract: The present invention provides a method for manufacturing a semiconductor device, comprising the steps of preparing a substrate having a quartz support substrate and a silicon layer, forming a base or substrate silicon oxide film over the entire upper surface of the silicon layer, forming a silicon nitride film over the entire upper surface of the substrate silicon oxide film by a plasma CVD method, patterning the silicon nitride film thereby to form a mask pattern having a circumferential exposure portion that exposes the substrate silicon oxide film in a circumferential area, a first opening pattern that exposes the substrate silicon oxide film in an element isolation area, and a second opening pattern that exposes the substrate silicon oxide film within a peripheral area, and thermally oxidizing the substrate using the mask pattern as a mask thereby to form an element isolation structure portion in the element isolation area.

Abstract: The present invention relates to an image sensor applied with a device isolation technique for reducing dark signals and a fabrication method thereof. The image sensor includes: a logic unit; and a light collection unit in which a plurality of photodiodes is formed, wherein the photodiodes are isolated from each other by a field ion-implantation region formed under a surface of a substrate and an insulation layer formed on the surface of the substrate.

Abstract: A method for fabricating a semiconductor element on a semiconductor substrate having a support substrate and a semiconductor layer above the support substrate. The method includes preparing the semiconductor substrate having a transistor formation region and an element isolation region both defined thereon; forming a pad oxide film on the semiconductor layer of the semiconductor substrate; forming an oxidation-resistant mask layer on the pad oxide film; forming a resist mask to cover the transistor formation region on the oxidation-resistant mask layer; performing a first etching process for etching the oxidation-resistant mask layer using the resist mask as a mask to expose the pad oxide film of the element isolation region; and removing the resist mask and oxidizing the semiconductor layer below the exposed pad oxide film by LOCOS using the exposed oxidation-resistant mask layer as a mask to form an element isolation layer.

Abstract: A method of electrically isolating a MEMS device is provided. In one example, a piezo-resistive pressure sensor having an exposed silicon region undergoes a Local Oxidation of Silicon (LOCOS) process. An electrically insulating structure is created in the LOCOS process. The insulating structure has a rounded, or curved, interface with the piezo-resistive pressure sensor. The curved interface mitigates stresses associated with exposure to high temperatures and pressures. Additionally, the electrically insulating line may be patterned so that it has curved angles, further mitigating stress.

Abstract: A method for fabricating a semiconductor device with a step gated asymmetric recess is provided.

Abstract: The invention is directed to a structure and method of forming a structure having a sealed gate oxide layer. The structure includes a gate oxide layer formed on a substrate and a gate formed on the gate oxide layer. The structure further includes a material abutting walls of the gate and formed within an undercut underneath the gate to protect regions of the gate oxide layer exposed by the undercut. Source and drain regions are isolated from the gate by the material.

Abstract: A system and method is disclosed that prevents the formation of a vertical bird's beak structure in the manufacture of a semiconductor device. A polysilicon filled trench is formed in a substrate of the semiconductor device. One or more composite layers are then applied over the trench and the substrate. A mask and etch process is then applied to etch the composite layers adjacent to the polysilicon filled trench. A field oxide process is applied to form field oxide portions in the substrate adjacent to the trench. Because no field oxide is placed over the trench there is no formation of a vertical bird's beak structure. A gate oxide layer is applied and a protection cap is formed over the polysilicon filled trench to protect the trench from unwanted effects of subsequent processing steps.

Abstract: One aspect disclosed herein relates to a method for forming a strained semiconductor structure. In various embodiments of the method, a number of recesses are formed in a surface of a silicon substrate using a Local Oxidation of Silicon (LOCOS) process, and a silicon membrane is bonded to the substrate. The membrane has a thickness less than 2000 ? and a mechanical strain greater than 0.5% where the membrane is bonded to the substrate in the number of recesses. Other aspects are provided herein.

Abstract: A structure for electrically isolating semiconductor devices includes a semiconducting layer and a layer of aluminum oxide formed in a pattern over the semiconducting layer, where the pattern exposes a portion of the semiconducting layer. The structure further includes an electrical isolation region formed in the exposed portion of the semiconducting layer, where the isolation region does not substantially encroach a region beneath the layer of aluminum oxide.

Abstract: A gate structure in a transistor and method for fabricating the structure. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure.

Abstract: A method for manufacturing a semiconductor substrate, including: forming a first semiconductor layer on a semiconductive base; forming a second semiconductor layer, having a smaller etching selection ratio than that of the first semiconductor layer, on the first semiconductor layer; removing part of the first semiconductor layer and the second semiconductor layer in the vicinity of device region, so as to form a support hole that exposes the semiconductive base; forming a support forming layer on the semiconductive base, so that the support hole is buried and the second semiconductor layer is covered; leaving an region that includes the support hole and the element region, etching the rest, so that an exposed surface is formed, where a part of edges of a support, the first semiconductor layer, and of the second semiconductor layer located at the lower side of the support are exposed; forming a cavity between the second semiconductor layer and the semiconductive base by etching the first semiconductor layer th

Abstract: The invention provides methods for forming isolation structures and STI trenches in a semiconductor device, which may be carried out in a variety of semiconductor manufacturing processes. One embodiment of the invention relates to a method of forming a semiconductor device having isolation structures. In this method, trench regions are formed within a semiconductor body, and then surfaces of the trench regions are nitrided. Then the nitrided surfaces are subjected to a condition that limits nitrogen desorption from the nitrided surfaces. The nitrided surfaces of the trench regions are then oxidized to form nitrogen containing liners, after which the isolation trench is filled with a dielectric material. Other methods and systems are also disclosed.

Abstract: A semiconductor device includes: a first element isolation film that is formed by a LOCOS oxidation method on a semiconductor substrate for isolating a first element region from other regions; a second element isolation film embedded in a groove formed in the semiconductor substrate for isolating a second element region from other regions; a first semiconductor element formed in the first element region; a second semiconductor element formed in the second element region; and a resistance element formed on the first element isolation film.

Abstract: The invention is directed to a structure and method of forming a structure having a sealed gate oxide layer. The structure includes a gate oxide layer formed on a substrate and a gate formed on the gate oxide layer. The structure further includes a material abutting walls of the gate and formed within an undercut underneath the gate to protect regions of the gate oxide layer exposed by the undercut. Source and drain regions are isolated from the gate by the material.

Abstract: A method for manufacturing a semiconductor element includes preparing an SOI layer having a transistor forming area and an element isolation area, forming an oxidation-resistant mask layer on the SOI layer, forming a resist mask over the transistor forming area on the oxidation-resistant mask layer, a first etching that etches the oxidation-resistant mask layer using the resist mask so that a predetermined thickness of the oxidation-resistant mask layer remains, a second etching that etches the remaining oxidation-resistant mask layer, using the resist mask and exposing the SOI layer at the element isolation area, and oxidizing the exposed SOI layer using the remaining oxidation-resistant mask layer, to form an element isolation layer. An etching rate during the first etching is higher than during the second etching and a silicon-to-etching selection ratio during the second etching is higher than during the first etching.

Abstract: Enhanced silicon-on-insulator transistors and methods are provided for implementing enhanced silicon-on-insulator transistors. The enhanced silicon-on-insulator (SOI) transistors include a thin buried oxide (BOX) layer under a device channel and a thick self-aligned buried oxide (BOX) region under SOI source/drain diffusions. A selective epitaxial growth is utilized in the source/drain regions to implement appropriate strain to enhance both PFET and NFET devices simultaneously.

Abstract: A method for forming a buried diffusion layer with reducing topography in a surface of a semiconductor substrate is provided. A patterned first dielectric layer is formed on a semiconductor substrate for being used as a first hard mask. A thermal oxidation process is performed to form field oxides on the exposed potions of the semiconductor substrate. The patterned first dielectric layer is then removed. A second patterned dielectric layer is formed on the field oxides and the semiconductor substrate for being used as a second hard mask. An isotropic etching process is performed to etch the exposed portions of the field oxides and the semiconductor substrate. The patterned second dielectric layer and the underlying field oxides are removed to form a plurality of trenches on the surface of the semiconductor substrate. A buried diffusion layer is formed along surroundings of the trenches in the semiconductor substrate.

Abstract: A method of forming a device isolation region in a semiconductor device is capable of completely removing an oxide layer for trench formation in a central region of the semiconductor device without forming a moat in an edge region. The method begins with forming a sacrificial oxide and sacrificial nitride layer over a semiconductor substrate. Trenches are etched in the nitride layer, the oxide layer and the substrate in the central and edge regions, respectively. The trenches are filled with an oxide layer. The oxide layer is then polished until the sacrificial nitride layer formed in the edge region is exposed, to form a first device isolation region filling a first trench and a second device isolation region pattern filling a second trench and covering the second region. A photoresist pattern is formed over the first device isolation region and the second device isolation region pattern.

Abstract: Provided are a semiconductor device and a method for its manufacture. In one example, the method includes forming an isolation structure having a first refraction index over a sensor embedded in a substrate. A first layer having a second refraction index that is different from the first refraction index is formed over the isolation structure. The first layer is removed from at least a portion of the isolation structure. A second layer having a third refraction index is formed over the isolation structure after the first layer is removed. The third refraction index is substantially similar to the first refraction index.

Abstract: A dielectric film containing atomic layer deposited HfSiON and a method of fabricating such a dielectric film produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. The HfSiON layer thickness is controlled by repeating for a number of cycles a sequence including pulsing a hafnium containing precursor into a reaction chamber, pulsing an oxygen containing precursor into the reaction chamber, pulsing a silicon containing precursor into the reaction chamber, and pulsing a nitrogen containing precursor until a desired thickness is formed. Dielectric films containing atomic layer deposited HfSiON are thermodynamically stable such that the HfSiON will have minimal reactions with a silicon substrate or other structures during processing.

Abstract: A method of fabricating a semiconductor device having a silicon layer disposed on an insulating film. Oxygen ions are implanted into selected parts of the silicon layer, which are then oxidized to form isolation regions dividing the silicon layer into a plurality of mutually isolated active regions. As the oxidation process does not create steep vertical discontinuities, fine patterns can be formed easily on the combined surface of the active and isolation regions. The implanted oxygen ions cause oxidation to proceed quickly, finishing before a pronounced bird's beak is formed. The isolation regions themselves can therefore be narrow and finely patterned.

Abstract: A method of improving transistor carrier mobility by adjusting stress through recessing shallow trench isolation is presented. A trench is formed in a substrate. The trench is filled with a dielectric. A CMOS transistor is formed adjacent to the trench. A silicide layer is formed on the source/drain region. A recess is formed by etching the dielectric so that the surface of the dielectric is substantially lower than the surface of the substrate. Recessing the STI removes the compressive stress applied to the channel region by the STI material. A contact etch stop layer (CESL) is formed over the gate electrode, spacers, source/drain regions and the dielectric. The CESL applies a desired stress to the channel region. Trench liners are optionally formed to provide a stress to the channel region. A spacer can optionally be formed in the STI recess.

Abstract: A STI (shallow trench isolation) structure is formed with a liner layer that is converted from an initial material to a subsequent material. For example, the liner layer is initially comprised of nitride during wet etch-back of a dielectric fill material comprised of oxide to protect an oxide layer on a semiconductor substrate. Thereafter, an exposed portion of the liner layer is converted into the subsequent material of oxide to protect the dielectric fill material within the STI opening during etching away of masking layers to prevent formation of dents in the STI structure.

Abstract: A method for integrating a metal-insulator-metal (MIM) capacitor in back end of line (BEOL) wiring levels of a semiconductor device includes forming an isolating layer over a lower wiring level, forming a bottom electrode of the capacitor on the isolating layer, and forming an interlevel dielectric material on the isolating layer and the bottom electrode. A capacitor dielectric is formed on the bottom electrode and a top electrode of the capacitor is formed on the capacitor dielectric, wherein the top electrode is formed concurrently with an upper wiring level, the upper level being the next successive wiring level with respect to the lower wiring level.

Abstract: A strained silicon semiconductor arrangement with a shallow trench isolation (STI) structure has a strained silicon (Si) layer formed on a silicon germanium (SiGe) layer. A trench extends through the Si layer into the SiGe layer, and sidewall spacers are employed that cover the entirety of the sidewalls within the trench in the SiGe layer. Following STI fill, polish and nitride stripping process steps, further processing can be performed without concern of the SiGe layer being exposed to a silicide formation process.

Abstract: One aspect disclosed herein relates to a method for forming a strained semiconductor structure. In various embodiments of the method, a number of recesses are formed in a surface of a first semiconductor wafer such that the surface of the first semiconductor wafer has a number of raised areas and a number of recessed areas. A surface of a second semiconductor wafer is bonded to the raised areas of the first semiconductor wafer in an environment having a first pressure. The surface of the second semiconductor wafer is bonded to the recessed areas of the first semiconductor wafer in an environment having a second pressure. The second pressure is greater than the first pressure to influence the second semiconductor wafer into contact with the first semiconductor wafer in the recesses in the surface of the first semiconductor wafer. Other aspects are provided herein.

Abstract: Disclosed herein are various methods for preventing bending of a patterned SOI layer during trench sidewall oxidation, the methods comprising providing a patterned SOI layer having at least one trench, said patterned SOI layer disposed upon an underlying buried silicon oxide layer; and blocking diffusion of oxygen between said patterned SOI and buried silicon oxide layer.

Abstract: A semiconductor device has an STI oxide film (106), of which surface is positioned higher than the surface of the silicon substrate (100) to prevent a pointed portion and a thin film thickness of a gate oxide film (108). The gate oxide film (106) becomes thicker toward a side wall (112) of the STI oxide film (106) to prevent the leakage current and increase the gate breakdown voltage.

Abstract: A method (100) of forming a transistor includes forming a gate structure (108) over a semiconductor body and forming recesses (112) using an isotropic etch using the gate structure as an etch mask. The isotropic etch forms a recess in the semiconductor body that extends laterally in the semiconductor body toward a channel portion of the semiconductor body underlying the gate structure. The method further includes epitaxially growing silicon (114) comprising stress-inducing species in the recesses. The source and drain regions are then implanted (120) in the semiconductor body on opposing sides of the gate structure.

Abstract: A method of fabricating a read only memory cell array is described. A patterned film is formed over the substrate to define the predetermined positions of bit lines on the substrate and exposing a plurality of predetermined portions of the substrate. A plurality of field oxide layers is formed on the exposed portions of the substrate to define the positions of channels. After removing the patterned film, ions are implanted into the substrate to form the bit lines by using the field oxide layer as implanting mask. The field oxide layer is removed to form several recesses on the substrate. Thereafter, a gate insulating layer and word lines are formed over the substrate, and the recess channels are formed underneath the gate-insulating layer. The length of the recess channel is large enough to reduce the short channel effect.

Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.

Abstract: The present invention relates to a shallow trench isolation method of a semiconductor wafer which fills dielectric material into shallow trenches between components on the surface of the semiconductor wafer to electrically isolate the components. This method can prevent dishing phenomenon from occurring over the surface of some wider shallow trenches when a chemical-mechanical polishing method is used to polish the surface of the dielectric material filled in each shallow trench.

Abstract: The present invention provides a semiconductor device that reduces the junction leak current and achieves an improvement in the reliability of the gate oxide film by minimizing divot formation and the occurrence of a kink and a method of manufacturing such a semiconductor device. A pad oxide film and a silicon nitride film are formed on an Si substrate and a groove-like trench is formed through photolithography and etching. The liner oxide of the trench are oxidized through oxidizing/nitriding. Then, the trench is filled with an insulating film, the insulating film is planarized and the silicon nitride film and the pad oxide film are removed. Next, a field area is formed and a transistor is formed by following specific steps. By forming a trench liner oxide film containing nitrogen, stress is reduced.