Making Electromagnetic Responsive Array Patents (Class 438/73)
  • Publication number: 20140096816
    Abstract: A heterojunction semiconductor device including an array of microstructures, each microstructure including a microwire of a first semiconductor material and a coating of a second semiconductor material forming a heterojunction with the microwire; a first electrical contact and a second electrical contact, one of which is connected to the microwire and the other of which is connected to the coating, is described. Also described are considerations for configuring the array of microstructures, and methods of forming the array of microstructures.
    Type: Application
    Filed: December 22, 2011
    Publication date: April 10, 2014
    Inventors: Harry A. Atwater, Nathan S. Lewis, Andrey D. Poletayev, Morgan C. Putnam, Michael D. Kelzenberg
  • Patent number: 8691694
    Abstract: In order to better and more efficiently assemble back contact solar cells into modules, the cell to cell soldering and other soldered connections are replaced by electro and/or electroless plating. Back contact solar cells, diodes and external leads can be first laminated to the module front glass for support and stability. Conductive materials are deposited selectively to create a plating seed pattern for the entire module circuit. Subsequent plating steps create an integrated cell and module metallization. This avoids stringing and tabbing and the associated soldering steps. This process is easier for mass manufacturing and is advantageous for handling fragile silicon solar cells. Additionally, since highly corrosion resistant metals can be plated, the moisture barrier requirements of the back side materials can be greatly relaxed. This can simplify and reduce the cost of the back side of the module.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: April 8, 2014
    Inventor: Henry Hieslmair
  • Patent number: 8691615
    Abstract: An image sensor and a method of manufacturing the same. The image sensor includes a plurality of photoelectric conversion units that are horizontally arranged and selectively emit electric signals by absorbing color beams.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: April 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyu-sik Kim
  • Publication number: 20140090685
    Abstract: Solar cells use as substrates glass (23) coated with a transparent conductive layer (21), able to collect the electric power generated by the solar cell. This layer (21), normally a TCO, have limited conductivity, implying the use of current collector lines applied in a complex manner. The conductivity of the conductive layer (21) is increased by the application of a structure, in particular a grid, of thin conductive lines (22) inserted in grooves on the glass surface (23) or directly applied on this, followed by a TCO layer coating (21). This highly conductive grid (22) collects the electricity from the TCO layer (21) and directs it to the periphery of the cell. Both glass substrates are sealed by a process employing a precursor of glass surrounding the entire perimeter of the substrate. The glass precursor is heated to its melting point, by a laser, completely sealing the two substrates of the module.
    Type: Application
    Filed: March 22, 2012
    Publication date: April 3, 2014
    Applicant: EFACEC ENGENHARIA E SISTEMAS, S.A.
    Inventors: Adélio Miguel Magalhães Mendes, Luisa Manuela Madurejra Andrade, Joaquim Gabriel Magalhães Mendes, José Miguel Lopes Macaira Nogueira, Fernando Manuel Da Silva Ribeiro
  • Publication number: 20140093994
    Abstract: The present application is a photodiode detector array for use in computerized tomography (CT) and non-CT applications. Specifically, the present application is a high-density photodiode arrays, with low dark current, low capacitance, high signal to noise ratio, high speed, and low crosstalk that can be fabricated on relatively large substrate wafers. More specifically the photodiode array of the present application is fabricated such that the PN-junctions are located on both the front side and back side surfaces of the array, and wherein the front side PN-junction is in electrical communication with the back side PN-junction. Still more specifically, the present application is a photodiode array having PN-junctions that are electrically connected from the front to back surfaces and which can be operated in a fully depleted mode at low reverse bias.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Peter Steven Bui, Narayan Dass Taneja
  • Patent number: 8686481
    Abstract: Disclosed are embodiments of a semiconductor device comprising a semiconductor body with a semiconductor image sensor comprising a two-dimensional matrix of picture elements, each picture element comprising a radiation-sensitive element coupled to MOS field effect transistors for reading the radiation-sensitive elements, wherein a semiconductor region is sunken in the surface of the body having the same conductivity type as the body and having an increased doping concentration, the semiconductor region being disposed between the radiation-sensitive elements of neighboring picture elements.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: April 1, 2014
    Assignee: Trixell
    Inventors: Joris Pieter Valentijn Maas, Willem-Jan Toren, Hein Otto Folkerts, Willem Hendrik Maes, Willem Hoekstra, Daniel Wilhelmus Elisabeth Verbugt, Daniel Hendrik Jan Maria Hermes
  • Patent number: 8686408
    Abstract: A photoelectric conversion device is provided and includes: a first electrode, a second electrode, and a photoelectric conversion layer between the first and second electrodes, the photoelectric conversion layer containing a mixture of an organic photoelectric conversion dye, a fullerene or a fullerene derivative, and a fullerene polymer; various embodiments of the device, a photosensor, an imaging device, and production methods for these devices.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: April 1, 2014
    Assignee: FUJIFILM Corporation
    Inventors: Katsuyuki Yofu, Daigo Sawaki
  • Patent number: 8679870
    Abstract: Provided is a method of manufacturing a semiconductor element having at a cut portion with excellent quality, which minimizes a region on a silicon substrate necessary for cutting, and which prevents cutting water used when cutting by dicing is carried out from entering the semiconductor element. The method of manufacturing a semiconductor element includes: arranging, on the silicon substrate, multiple semiconductor element portions so as to be adjacent to one another; bonding the silicon substrate and a glass substrate together using the resin; and cutting the silicon substrate and the glass substrate, respectively, in a region in which the resin is provided, the cutting the silicon substrate and the glass substrate including: half-cutting the silicon substrate by dicing; cutting the glass substrate by scribing; and dividing the silicon substrate, the glass substrate, and the resin.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: March 25, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Ichiro Kataoka, Kazuya Igarashi
  • Patent number: 8679890
    Abstract: A method includes: forming a transfer gate on a semiconductor substrate; forming a first ion implantation region on a first side of the transfer gate; forming a second ion implantation region on the first side of the transfer gate such that the second ion implantation region encloses the first ion implantation region; forming a third ion implantation region along a surface of the semiconductor substrate; and forming a floating diffusion region at a second side of the transfer gate.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: March 25, 2014
    Assignee: Intellectual Ventures II LLC
    Inventor: Youn-Sub Lim
  • Patent number: 8679933
    Abstract: Methods for fabricating semiconductor devices, such as complementary metal-oxide-semiconductor (CMOS) imagers, include fabricating transistors and other low-elevation features on an active surface of a fabrication substrate, and fabricating contact plugs, conductive lines, external contacts, and other higher-elevation features on the back side of the fabrication substrate. Semiconductor devices with transistors on the active surface and contact plugs that extend through the substrate are also disclosed, as are electronic devices including such semiconductor devices.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: March 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Steve Oliver
  • Publication number: 20140077212
    Abstract: Embodiments of the present invention disclose a sensor and a method for manufacturing the same, the sensor comprising a plurality of sensing units arranged in array, each of which comprises a thin film transistor device and a photodiode sensor device and the photodiode sensor device comprising: a receiving electrode connected with a drain of the thin film transistor device, a photodiode located on the receiving electrode and covering the thin film transistor device, a transparent electrode on the photodiode and a biasing line connected with the transparent electrode.
    Type: Application
    Filed: November 15, 2012
    Publication date: March 20, 2014
    Applicant: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Tiansheng Li, Changjiang Yan, Shaoying Xu, Zhenyu Xie
  • Publication number: 20140080247
    Abstract: The present invention provides a method of more efficiently producing a semiconductor epitaxial wafer, which can suppress metal contamination by achieving higher gettering capability. A method of producing a semiconductor epitaxial wafer 100 according to the present invention includes a first step of irradiating a semiconductor wafer 10 with cluster ions 16 to form a modifying layer 18 formed from a constituent element of the cluster ions 16 in a surface portion 10A of the semiconductor wafer; and a second step of forming an epitaxial layer 20 on the modifying layer 18 of the semiconductor wafer 10.
    Type: Application
    Filed: March 19, 2012
    Publication date: March 20, 2014
    Applicant: SUMCO CORPORATION
    Inventors: Takeshi Kadono, Kazunari Kurita
  • Patent number: 8673793
    Abstract: A method for calculating an offset value for aligned deposition of a second pattern onto a first pattern, comprising steps of: (a) loading a substrate with the first pattern on a surface of the substrate into a pattern recognition device at an original position inside the pattern recognition device; (b) determining a coordinate of a prescribed point of the first pattern by the pattern recognition device; (c) superimposing the second pattern onto the first pattern on the surface of the substrate; (d) bringing back the substrate with the first pattern and the second pattern into the original position inside the pattern recognition device; (e) determining a coordinate of a prescribed point of the second pattern by the pattern recognition device; wherein the prescribed point of the first pattern corresponds to the prescribed point of the second pattern; and (f) calculating the offset value between the first pattern and the second pattern.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: March 18, 2014
    Inventor: Andreas Meisel
  • Publication number: 20140070352
    Abstract: An embodiment semiconductor device includes a substrate such as a silicon or silicon-containing film, a pixel array supported by the substrate, and a metal stress release feature arranged around a periphery of the pixel array. The metal stress release feature may be formed from metal strips or discrete metal elements. The metal stress release feature may be arranged in a stress release pattern that uses a single line or a plurality of lines. The metal stress release pattern may also use metal corner elements at ends of the lines.
    Type: Application
    Filed: December 7, 2012
    Publication date: March 13, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Han Tsai, Allen Tseng, Yen-Hsung Ho, Chun-Hao Chou, Kuo-Cheng Lee, Volume Chien, Chi-Cherng Jeng
  • Patent number: 8669464
    Abstract: A thermophotovoltaic system is described. The thermophotovoltaic system includes a chamber body, an emitter, a filter and a photovoltaic cell. The chamber body has an ellipsoid chamber including a first focus and a second focus. The emitter is disposed on the first focus, and the emitter is suitable for emitting a plurality of electromagnetic waves. The filter is surrounding the emitter to filter the electromagnetic waves and to pass the electromagnetic waves with a predetermined wavelength band. The photovoltaic cell is disposed on the second focus and is suitable for receiving the electromagnetic waves with the predetermined wavelength band.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: March 11, 2014
    Assignee: National Cheng Kung University
    Inventors: Wen-Chi Hou, Tung-Hsien Wu, Chih-Jui Ni, Chih-Lien Chiang, Chau-Nan Hong
  • Publication number: 20140065758
    Abstract: A removable cover system for protecting solar cells from exposure to moisture during fabrication processes. The cover system includes a cover having a configuration that complements the configuration of a solar cell substrate to be processed in an apparatus where moisture is present. A resiliently deformable seal member attached to the cover is positionable with the cover to engage and seal the top surface of the substrate. In one embodiment, the cover is dimensioned and arranged so that the seal member engages the peripheral angled edges and corners of the substrate for preventing the ingress of moisture beneath the cover. An apparatus for fabricating a solar cell using the cover and associated method are also disclosed.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 6, 2014
    Applicant: TSMC SOLAR, LTD.
    Inventors: Chih-Wei HUANG, Keng-Hsin CHI, Chien-Nan LIN, Hua-Tso WEI
  • Publication number: 20140061842
    Abstract: A method includes forming an opening extending from a back surface of a semiconductor substrate to a metal pad on a front side of the semiconductor substrate, and forming a first conductive layer including a first portion overlapping active image sensors in the semiconductor substrate, a second portion overlapping black reference image sensors in the semiconductor substrate, and a third portion in the opening to contact the metal pad. A second conductive layer is formed over and contacting the first conductive layer. A first patterning step is performed to remove the first and the second portions of the second conductive layer, wherein the first conductive layer is used as an etch stop layer. A second patterning step is performed to remove a portion of the first portion of the first conductive layer. The second and the third portions of the first conductive layer remain after the second patterning step.
    Type: Application
    Filed: September 5, 2012
    Publication date: March 6, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shyh-Fann Ting, Jiech-Fun Lu, Ming-I Wang, Yeur-Luen Tu, Ching-Chun Wang
  • Publication number: 20140061738
    Abstract: The present disclosure relates to a method and composition to limit crystalline defects introduced in a semiconductor device during ion implantation. A high-temperature low dosage implant is performed utilizing a tri-layer photoresist which maintains the crystalline structure of the semiconductor device while limiting defect formation within the semiconductor device. The tri-layer photoresist comprises a layer of spin-on carbon deposited onto a substrate, a layer of silicon containing hard-mask formed above the layer of spin-on carbon, and a layer of photoresist formed above the layer of silicon containing hard-mask. A pattern formed in the layer of photoresist is sequentially transferred to the silicon containing hard-mask, then to the spin-on carbon, and defines an area of the substrate to be selectively implanted with ions.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung Chien Wang, Yeur-Luen Tu, Cheng-Ta Wu, Jiech-Fun Lu, Chun-Wei Chang, Wang-Pen Mo, Jhy-Jyi Sze, Chia-Shiung Tsai
  • Publication number: 20140065759
    Abstract: A method for bonding first and second wafers by molecular adhesion. The method includes placing the wafers in an environment having a first pressure (P1) greater than a predetermined threshold pressure above which initiation of bonding wave propagation is prevented, bringing the first wafer and the second wafer into alignment and contact, and spontaneously initiating the propagation of a bonding wave between the wafers after they are in contact solely by reducing the pressure within the environment to a second pressure (P2) below the threshold pressure.
    Type: Application
    Filed: October 30, 2013
    Publication date: March 6, 2014
    Applicant: Soitec
    Inventor: Marcel BROEKAART
  • Publication number: 20140054662
    Abstract: The present technology relates to a solid-state imaging device, manufacturing method of a solid-state imaging device, and an electronic device, which can provide a solid-state imaging device having further improved features such as reduced optical color mixing and the like. Also, an electronic device using the solid-state imaging device thereof is provided. According to a solid-state imaging device having a substrate 12 and multiple photoelectric converters 40 that are formed on the substrate 12, an insulating film 21 forms an embedded element separating unit 19. The element separating unit 19 is configured of an insulating film 20 having a fixed charge that is formed so as to coat the inner wall face of a groove portion 30, within the groove portion 30 which is formed in the depth direction from the light input side of the substrate 12.
    Type: Application
    Filed: February 23, 2012
    Publication date: February 27, 2014
    Applicant: SONY CORPORATION
    Inventors: Takeshi Yanagita, Itaru Oshiyama, Takayuki Enomoto, Harumi Ikeda, Shinichiro Izawa, Atsuhiko Yamamoto, Kazunobu Ota
  • Publication number: 20140054737
    Abstract: A solid-state imaging device includes: a substrate; an insulator layer formed on the substrate; a semiconductor layer formed on the insulator layer; and a silicon layer formed on the semiconductor layer. The silicon layer includes a plurality of pixels each including a photoelectric converter configured to convert light into signal charge, and a circuit configured to read the signal charge, and a refractive index of the insulator layer is lower than a refractive index of the semiconductor layer.
    Type: Application
    Filed: October 30, 2013
    Publication date: February 27, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Toru OKINO, Mitsuyoshi MORI, Yutaka HIROSE, Yoshihisa KATO, Tsuyoshi TANAKA
  • Patent number: 8658457
    Abstract: There is provided a method of producing a semiconductor device. The method includes the steps of: forming a first hard mask having an opening above a substrate; forming a sacrificial film above a side surface of the opening of the first hard mask; forming a second hard mask in the opening having the sacrificial film above the side surface; removing the sacrificial film after the second hard mask is formed; ion implanting a first conductivity-type impurity through the first hard mask; and ion implanting a second conductivity-type impurity through the first and second hard masks.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: February 25, 2014
    Assignee: Sony Corporation
    Inventor: Yasufumi Miyoshi
  • Publication number: 20140051203
    Abstract: A single crystal silicon layer is formed on a principal surface of a first wafer by epitaxial growth. A silicon oxide layer is formed on the single crystal silicon layer. Next, a defect layer is formed inside the single crystal silicon layer by ion implantation, and then, the second wafer is bonded to the silicon oxide layer on the first wafer. After that, an SOI wafer including the silicon oxide layer formed on the second wafer and the single crystal silicon layer formed on the silicon oxide layer is formed by separating the first wafer including the single crystal silicon layer from the second wafer including the single crystal silicon layer in the defect layer. Then, a photodiode is formed in the single crystal silicon layer. An interconnect layer is formed on a surface of the single crystal silicon layer which is opposite to the silicon oxide layer.
    Type: Application
    Filed: October 23, 2013
    Publication date: February 20, 2014
    Applicant: PANASONIC CORPORATION
    Inventor: Akira TSUKAMOTO
  • Publication number: 20140051204
    Abstract: A solid-state imaging device includes a photoelectric conversion section which is disposed on a semiconductor substrate and which photoelectrically converts incident light into signal charges, a pixel transistor section which is disposed on the semiconductor substrate and which converts signal charges read out from the photoelectric conversion section into a voltage, and an element isolation region which is disposed on the semiconductor substrate and which isolates the photoelectric conversion section from an active region in which the pixel transistor section is disposed. The pixel transistor section includes a plurality of transistors. Among the plurality of transistors, in at least one transistor in which the gate width direction of its gate electrode is oriented toward the photoelectric conversion section, at least a photoelectric conversion section side portion of the gate electrode is disposed within and on the active region with a gate insulating film therebetween.
    Type: Application
    Filed: October 25, 2013
    Publication date: February 20, 2014
    Applicant: Sony Corporation
    Inventors: Takuji Matsumoto, Keiji Tatani, Tetsuji Yamaguchi, Masashi Nakata
  • Patent number: 8652863
    Abstract: According to the method of manufacturing an optical matrix device of this invention, semiconductor films and gate insulating films which influence the characteristics of thin-film transistors most are formed in a vacuum (S12, S13), whereby the interfaces between the semiconductor films and gate insulating films are not contaminated. The semiconductor films and gate insulating films are formed in a vacuum, but wires need not be formed in a vacuum (S03). Thus, the semiconductor films and gate insulating films formed in a vacuum are transferred onto the wires formed beforehand (S21). Even if a substrate has a large area, the wires, semiconductor films and gate insulating films of the thin-film transistors can be formed efficiently.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: February 18, 2014
    Assignee: Shimadzu Corporation
    Inventor: Susumu Adachi
  • Patent number: 8652868
    Abstract: An implanting method for forming a photodiode comprises providing a substrate with a first conductivity, growing an epitaxial layer on the substrate, implanting ions with a second conductivity in the epitaxial layer from a front side of the substrate and implanting ions with the first conductivity in the epitaxial layer from the front side of the substrate to form a photo active region adjacent to the front side and a photo inactive region underneath the photo active region. By employing the implanting method, an average doping density of the photo active region is approximately ten times more than an average doping density of the photo inactive region.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: February 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Shen Shih, Ching-Hwanq Su, Wei-Ming You, Chih-Cherng Jeng, Kuo-Cheng Lee, Yen-Hsung Ho
  • Publication number: 20140042416
    Abstract: Pixel electrodes have end portions inclined at inclination angles ?, where 30°???85°, relative to a substrate surface of a substrate. An organic layer disposed on the pixel electrodes is formed by vapor deposition using deposition beams that enter the substrate surface at incident angles ? smaller than 90°??max, where ?max is the maximum inclination angle among the inclination angles of the end portions of the pixel electrodes, under a deposition substrate temperature condition lower than the glass transition temperature of the organic layer.
    Type: Application
    Filed: October 18, 2013
    Publication date: February 13, 2014
    Applicant: FUJIFILM CORPORATION
    Inventor: Shinji IMAI
  • Publication number: 20140041711
    Abstract: An apparatus comprising a plurality of solar cells that each comprise a nanowire titanium oxide core having graphene disposed thereon. By one approach this plurality of solar cells can comprise, at least in part, a titanium foil having the plurality of solar cells disposed thereon wherein at least a majority of the solar cells are aligned substantially parallel to one another and substantially perpendicular to the titanium foil. Such a plurality of solar cells can be disposed between a source of light and another modality of solar energy conversion such that both the solar cells and the another modality of solar energy conversion generate electricity using a same source of light.
    Type: Application
    Filed: August 7, 2013
    Publication date: February 13, 2014
    Applicant: Dimerond Technologies, LLC
    Inventor: Dieter M. Gruen
  • Patent number: 8649483
    Abstract: A method is described for producing a grating, in particular an absorption grating, having a grating constant of less than 100 ?m, by using a solution of superparamagnetic colloidal nanocrystal clusters (CNCs), a solvent liquid and a photocurable resin, with the following steps: —alignment of the CNCs in the solution by an external magnetic field, —exposure of the solution, so that the resin is cured and grating structures of an intended grating constant are formed, and —removal of the magnetic field.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: February 11, 2014
    Assignee: Siemens Aktiengesellschaft
    Inventor: Martin Hoheisel
  • Publication number: 20140035087
    Abstract: Methods of forming isolation structures are disclosed. A method of forming isolation structures for an image sensor array of one aspect may include forming a dielectric layer over a semiconductor substrate. Narrow, tall dielectric isolation structures may be formed from the dielectric layer. The narrow, tall dielectric isolation structures may have a width that is no more than 0.3 micrometers and a height that is at least 1.5 micrometers. A semiconductor material may be epitaxially grown around the narrow, tall dielectric isolation structures. Other methods and apparatus are also disclosed.
    Type: Application
    Filed: August 2, 2012
    Publication date: February 6, 2014
    Inventors: Chia-Ying Liu, Keh-Chiang Ku, Wu-Zhang Yang
  • Publication number: 20140038341
    Abstract: There is provided a method of producing a semiconductor device. The method includes the steps of: forming a first hard mask having an opening above a substrate; forming a sacrificial film above a side surface of the opening of the first hard mask; forming a second hard mask in the opening having the sacrificial film above the side surface; removing the sacrificial film after the second hard mask is formed; ion implanting a first conductivity-type impurity through the first hard mask; and ion implanting a second conductivity-type impurity through the first and second hard masks.
    Type: Application
    Filed: October 11, 2013
    Publication date: February 6, 2014
    Applicant: Sony Corporation
    Inventor: Yasufumi Miyoshi
  • Publication number: 20140035082
    Abstract: A device includes a plurality of isolation spacers, and a plurality of bottom electrodes, wherein adjacent ones of the plurality of bottom electrodes are insulated from each other by respective ones of the plurality of isolation spacers. A plurality of photoelectrical conversion regions overlaps the plurality of bottom electrodes, wherein adjacent ones of the plurality of photoelectrical conversion regions are insulated from each other by respective ones of the plurality of isolation spacers. A top electrode overlies the plurality of photoelectrical conversion regions and the plurality of isolation spacers.
    Type: Application
    Filed: October 17, 2012
    Publication date: February 6, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Shin Chu, Cheng-Tao Lin, Meng-Hsun Wan, Szu-Ying Chen, Jen-Cheng Liu, Dun-Nian Yaung
  • Publication number: 20140038342
    Abstract: A method for manufacturing a back-illuminated type solid-state imaging device by (a) providing a substrate having, on a front surface side thereof, a semiconductor film on a semiconductor substrate with an insulation film therebetween; (b) forming in the semiconductor substrate a charge accumulation portion of a photoelectric conversion element that constitutes a pixel; (c) forming in the semiconductor film at least some transistors that constitute the pixel; and (d) forming on a rear surface side of the semiconductor substrate a rear surface electrode to which a voltage can be applied.
    Type: Application
    Filed: October 11, 2013
    Publication date: February 6, 2014
    Applicant: Sony Corporation
    Inventor: Keiji Mabuchi
  • Publication number: 20140034836
    Abstract: A radiation detection apparatus includes a sensor panel configured to detect light; and a scintillator layer arranged on the sensor panel. The scintillator layer has a scintillator configured to convert radiation into light of a wavelength that is detectable by the sensor panel. The scintillator layer also has particles that have a property of generating a bubble and expanding so as to weaken adhesive force between the sensor panel and the scintillator layer. The scintillator layer also a resin that holds the scintillator and the particles so as to be mixed together. The scintillator layer is adhered to the sensor panel with use of the resin.
    Type: Application
    Filed: July 18, 2013
    Publication date: February 6, 2014
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Taiki Takei, Masato Inoue, Shinichi Takeda, Satoru Sawada, Takamasa Ishii, Kota Nishibe, Shoshiro Saruta, Kazumi Nagano, Satoshi Okada, Yohei Ishida
  • Publication number: 20140038340
    Abstract: The solar cell module having a preferable edge space that prevents characteristics of a solar cell such as conversion efficiency from being deteriorated without making processes complicated is provided. In a method for manufacturing a solar cell module including a substrate glass, a first layer formed on the substrate glass and a second layer formed on the first layer, the method includes a step of forming a first edge space having a first width by removing the first layer and the second layer by the first width from an end part of the glass substrate and a step of forming a second edge space by removing only the second layer by a second width from the end part of the glass substrate, and the width of the second edge space is larger than the width of the first edge space.
    Type: Application
    Filed: October 11, 2013
    Publication date: February 6, 2014
    Applicant: SHOWA SHELL SEKIYU K.K.
    Inventors: Hirofumi NISHI, Hirohisa SUZUKI
  • Patent number: 8642943
    Abstract: A light-receiving element includes an InP substrate 1, a light-receiving layer 3 having an MQW and located on the InP substrate 1, a contact layer 5 located on the light-receiving layer 3, a p-type region 6 extending from a surface of the contact layer 5 to the light-receiving layer, and a p-side electrode 11 that forms an ohmic contact with the p-type region. The light-receiving element is characterized in that the MQW has a laminated structure including pairs of an InxGa1-xAs (0.38?x?0.68) layer and a GaAs1-ySby (0.25?y?0.73) layer, and in the GaAs1-ySby layer, the Sb content y in a portion on the InP substrate side is larger than the Sb content y in a portion on the opposite side.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: February 4, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiroki Mori, Yasuhiro Iguchi, Hiroshi Inada, Youichi Nagai, Kouhei Miura, Hideaki Nakahata, Katsushi Akita, Takashi Ishizuka, Kei Fujii
  • Patent number: 8642373
    Abstract: Disclosed is a method for manufacturing a photovoltaic device that includes: providing a substrate having a first electrode formed thereon; forming a first unit cell, the first unit cell including a first conductive silicon layer, an intrinsic silicon layer and a second conductive silicon layer, which are sequentially stacked from the first electrode; exposing to the air either a portion of an intermediate reflector formed on the first unit cell or the second conductive silicon layer of the first unit cell; forming the rest of the intermediate reflector or the entire intermediate reflector on the second conductive silicon layer of the first unit cell in a second manufacturing system; and forming a second unit cell on the intermediate reflector in the second manufacturing system, the second unit cell including a first conductive silicon layer, an intrinsic silicon layer and a second conductive silicon layer, sequentially stacked.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: February 4, 2014
    Assignee: Intellectual Discovery Co., Ltd.
    Inventor: Seung-Yeop Myong
  • Patent number: 8643064
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: February 4, 2014
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Publication number: 20140026935
    Abstract: The present invention provides a method for manufacturing array substrate with embedded photovoltaic cell and an array substrate manufactured with same. The method includes: (1) providing a substrate; (2) forming a transparent conductive layer on the substrate; (3) forming a conductivity enhancing layer on the transparent conductive layer; (4) forming a photovoltaic layer on the conductivity enhancing layer; (5) forming a metal layer on the photovoltaic layer; (6) applying a masking process to form an opening in the metal layer, the photovoltaic layer, the conductivity enhancing layer, and the transparent conductive layer; (7) forming a transparent insulation layer on the metal layer; and (8) forming a TFT array on the transparent insulation layer. The present invention allows a photovoltaic cell to be embedded in an array substrate through a simple process and allows a full use of the photo energy from a backlight module.
    Type: Application
    Filed: August 10, 2012
    Publication date: January 30, 2014
    Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Xindi Zhang
  • Patent number: 8637399
    Abstract: An etching composition for a copper-containing layer includes about 0.1% to about 30% by weight of ammonium persulfate, about 0.1% to about 10% by weight of a sulfate, about 0.01% to about 5% by weight of an acetate and about 55% to about 99.79% by weight of water. The etching composition having improved stability during storage and an increased capacity for etching.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: January 28, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hong-Sick Park, Bong-Kyun Kim, Wang-Woo Lee, Ki-Beom Lee, Sam-Young Cho, Won-Guk Seo, Gyu-Po Kim
  • Publication number: 20140024166
    Abstract: A simple method that makes it possible to manufacture a highly-workable organic solar cell module having a plurality of connected organic solar cells is provided. The method includes: a first electrode substrate forming step of forming a plurality of first electrode layers on a first substrate to form a first electrode substrate; preparing a single piece of second electrode substrate-forming base material having at least a second electrode layer and capable of being cut into a plurality of second electrode substrates; a functional layer forming step; a cutting step to form a plurality of second electrode substrates; a bonding step so that the first and second electrode substrates are bonded together; and a connecting step of electrically connecting the first electrode layer of one of the organic solar cells to the second electrode layer of another organic solar cell which is adjacent to the one organic solar cell.
    Type: Application
    Filed: April 6, 2012
    Publication date: January 23, 2014
    Applicant: DAI NIPPON PRINTING CO., LTD.
    Inventors: Kenta Sekikawa, Satoshi Mitsuzuka, Miho Sasaki
  • Patent number: 8633051
    Abstract: An object is to prevent a reduction of definition (or resolution) (a peripheral blur) caused when reflected light enters a photoelectric conversion element arranged at a periphery of a photoelectric conversion element arranged at a predetermined address. A semiconductor device is manufactured through the steps of: forming a structure having a first light-transmitting substrate, a plurality of photoelectric conversion elements over the first light-transmitting substrate, a second light-transmitting substrate provided so as to face the plurality of photoelectric conversion elements, a sealant arranged so as to bond the first light-transmitting substrate and the second light-transmitting substrate and surround the plurality of photoelectric conversion elements; and thinning the first light-transmitting substrate by wet etching.
    Type: Grant
    Filed: August 19, 2010
    Date of Patent: January 21, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Takayuki Ikeda, Munehiro Kozuma, Hikaru Tamura, Kazuko Yamawaki, Takashi Hamada, Shunpei Yamazaki
  • Publication number: 20140014182
    Abstract: The present invention relates to a solar cell module which is characterized in that: a light-transmitting elastomer member and a solar cell element are arranged in a space between a panel of a transparent member upon which sunlight is incident and a panel of a thermally conductive member which is arranged on the side opposite to the sunlight incidence side in such a manner that the light-transmitting elastomer member is closer to the sunlight incidence side; and the solar cell element is pressed by the light-transmitting elastomer member toward the panel of a thermally conductive member so that the solar cell element is compression bonded thereto. This solar cell module is most suitable as a solar cell module that has excellent heat dissipation of a cell, the temperature of which is increased due to sunlight or a hot spot, and a structure that suppresses the production cost.
    Type: Application
    Filed: May 31, 2012
    Publication date: January 16, 2014
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Tomoyoshi Furihata, Atsuo Ito, Hyung-Bae Kim, Minoru Igarashi, Masakatsu Hotta, Tsutomu Nakamura
  • Publication number: 20140014156
    Abstract: A method for manufacturing two series-connected photovoltaic cells includes: forming an insulating substrate; forming a stack including; a first conductive layer formed on the substrate; a semiconductor layer comprising a first absorption layer and a second semiconductor layer forming a junction with the first absorption layer; and a second transparent conductive layer, formed on the absorption layer; forming an area dividing the stack into two cells series-connected by an electric path. The forming of said path comprises: forming a first trench all the way to the substrate; forming a second trench all the way to the first conductive layer; and depositing a conductive solution on the first trench and at last a portion of the second trench, so that the solution does not penetrate into the first trench all the way to the first conductive layer and penetrates into the second trench all the way to the first conductive layer.
    Type: Application
    Filed: August 15, 2013
    Publication date: January 16, 2014
    Applicant: Commissariat A L'Energie Atomique Et Aux Energies Alternatives
    Inventors: Anne-Laure SEILER, Philippe CORONEL, Joël DUFOURCQ
  • Publication number: 20140015013
    Abstract: There is provided a solid-state image pickup device including a semiconductor substrate, and a plurality of pixel portions that are provided on the semiconductor substrate. Each of the pixel portions includes a photoelectric converting unit that generates a charge on the basis of incident light, a memory unit that accumulates the charge generated by the photoelectric converting unit, a light shielding portion that shields at least the memory unit from light, a digging portion that digs into the semiconductor substrate between the photoelectric converting unit and the memory unit and is formed of a light shielding material, and a transmitting unit that transmits the charge from the photoelectric converting unit to the memory unit, by forming a channel for transmission in the digging portion.
    Type: Application
    Filed: June 26, 2013
    Publication date: January 16, 2014
    Inventor: Shinichi Arakawa
  • Publication number: 20140008708
    Abstract: A CMOS image sensor includes a substrate, a gate electrode formed over the substrate, a photodiode formed over the substrate to be substantially aligned with one side of the gate electrode, a floating diffusion region formed over the substrate to be substantially aligned with the other side of the gate electrode, and a blooming pass region formed below the photodiode.
    Type: Application
    Filed: August 30, 2012
    Publication date: January 9, 2014
    Inventor: Youn-Sub LIM
  • Publication number: 20140007927
    Abstract: Exemplary embodiments provide a solar cell device, and method for forming the solar cell device by integrating a switch component into a solar cell element. The solar cell element can include a solar cell, a solar cell array and/or a solar cell panel. The integrated solar cell element can be used for a solar sensor, while the solar sensor can also use discrete switches for each solar cell area of the sensor. Exemplary embodiments also provide a connection system for the solar cell elements and a method for super-connecting the solar cell elements to provide a desired connection path or a desired power output through switch settings. The disclosed connection systems and methods can allow for by-passing underperforming solar cell elements from a plurality of solar cell elements. In embodiments, the solar cell element can be extended to include a battery or a capacitor.
    Type: Application
    Filed: September 10, 2013
    Publication date: January 9, 2014
    Applicant: Intersil Americas Inc.
    Inventor: Stephen Joseph Gaul
  • Publication number: 20140008755
    Abstract: According to one embodiment, in a semiconductor device, a semiconductor substrate has a first surface and a second surface which is opposed to the first surface. An insulating layer is provided on the first surface of the semiconductor substrate. A metal wiring is provided within the insulating layer. A support substrate is bonded to the insulating layer. A poly silicon electrode is connected to the metal wiring through a contact. A pad is provided on the second surface of the semiconductor substrate and is connected to the poly silicon electrode through a metal film deposited in a via-hole to penetrate the semiconductor substrate and extend to the poly silicon electrode.
    Type: Application
    Filed: February 11, 2013
    Publication date: January 9, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hidetoshi KOIKE
  • Publication number: 20140008520
    Abstract: A sensor includes an array of pixels, and a global shutter configured to expose the array of pixels. Each pixel includes storage elements configured to independently store successive frames within a predetermined time period. Each storage element is configured to be independently read out.
    Type: Application
    Filed: February 7, 2012
    Publication date: January 9, 2014
    Inventor: Jeffrey M. Raynor
  • Publication number: 20140008709
    Abstract: A CMOS image sensor includes a substrate, a punch-through prevention layer formed over the substrate, an epitaxial layer formed over the punch-through prevention layer, a gate electrode formed over the epitaxial layer; a photodiode formed in the epitaxial layer to be substantially aligned with one side of the gate electrode, a floating diffusion region formed in the epitaxial layer to be substantially aligned with the other side of the gate electrode, and an extended photodiode region formed below the photodiode to be coupled with the punch-through prevention layer.
    Type: Application
    Filed: August 30, 2012
    Publication date: January 9, 2014
    Inventor: Youn-Sub LIM