Insulative Material Deposited Upon Semiconductive Substrate Patents (Class 438/778)
  • Patent number: 8785333
    Abstract: A method of manufacturing a semiconductor device includes forming a thin film containing a predetermined element, carbon, nitrogen and a borazine ring skeleton on a substrate by performing a cycle for a first predetermined number of times. The cycle includes forming a first layer containing the predetermined element, a halogen group, carbon and nitrogen by supplying a first precursor gas containing the predetermined element and the halogen group and a second precursor gas containing the predetermined element and an amino group to the substrate, for a second predetermined number of times; and forming a second layer containing the predetermined element, carbon, nitrogen and the borazine ring skeleton by supplying a reaction gas containing a borazine compound to the substrate and allowing the first layer to react with the borazine compound to modify the first layer under a condition where the borazine ring skeleton in the borazine compound is maintained.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: July 22, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Yoshitomo Hashimoto, Yoshiro Hirose, Satoshi Shimamoto, Atsushi Sano
  • Publication number: 20140199855
    Abstract: A method for making a carbon nanotube film includes the steps of: (a) adding a plurality of carbon nanotubes to a solvent to create a carbon nanotube floccule structure in the solvent; (b) separating the carbon nanotube floccule structure from the solvent; and (c) shaping the separated carbon nanotube floccule structure to obtain the carbon nanotube film.
    Type: Application
    Filed: December 20, 2007
    Publication date: July 17, 2014
    Applicants: HON HAI Precision Industry CO., LTD., Tsinghua University
    Inventors: Ding Wang, Chang-Hong Liu, Shou-Shan Fan
  • Patent number: 8778194
    Abstract: A method is described for manufacturing a component having a through-connection. The method includes providing a substrate; forming a trench structure in the substrate, a substrate area which is completely surrounded by the trench structure being produced; forming a closing layer for closing off the trench structure, a cavity girded by the closing layer being formed in the area of the trench structure; removing substrate material from the substrate area surrounded by the closed-off trench structure; and at least partially filling the substrate area surrounded by the closed-off trench structure with a metallic material. A component having a through-connection is also described.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: July 15, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Jochen Reinmuth, Yvonne Bergmann
  • Patent number: 8778814
    Abstract: A method of manufacturing a semiconductor device includes the steps of: preparing an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, tetramethylcyclotetrasiloxane, carbon dioxide gas and oxygen gas, a flow rate of said oxygen gas being at most 3% of a flow rate of the carbon dioxide gas. The surface of the silicon carbide layer of the underlying structure may be treated with a plasma of weak oxidizing gas which contains oxygen and has a molecular weight larger than that of O2 to bring the surface more hydrophilic. Film peel-off and cracks in the interlayer insulating layer decrease.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: July 15, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tamotsu Owada, Shun-ichi Furuyama, Hirofumi Watantani, Kengo Inoue, Atsuo Shimizu
  • Publication number: 20140193983
    Abstract: Disclosed herein are methods of forming SiC/SiCN film layers on surfaces of semiconductor substrates. The methods may include introducing a silicon-containing film-precursor and an organometallic ligand transfer reagent into a processing chamber, adsorbing the silicon-containing film-precursor, the organometallic ligand transfer reagent, or both onto a surface of a semiconductor substrate under conditions whereby either or both form an adsorption-limited layer, and reacting the silicon-containing film-precursor with the organometallic ligand transfer reagent, after either or both have formed the adsorption-limited layer. The reaction results in the forming of the film layer. In some embodiments, a byproduct is also formed which contains substantially all of the metal of the organometallic ligand transfer reagent, and the methods may further include removing the byproduct from the processing chamber. Also disclosed herein are semiconductor processing apparatuses for forming SiC/SiCN film layers.
    Type: Application
    Filed: January 10, 2013
    Publication date: July 10, 2014
    Inventor: Adrien LaVoie
  • Patent number: 8772178
    Abstract: By depositing the lower portion of a silicon dioxide interlayer dielectric by means of SACVD or HDP-CVD techniques, the generation of voids may be reliably avoided even for devices having spaces between closely spaced lines on the order of 200 nm or less. Moreover, the bulk silicon dioxide material is deposited by well-established plasma enhanced CVD techniques, thereby providing the potential for using well-established process recipes for the subsequent CMP process, so that production yield and cost of ownership may be maintained at a low level.
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: July 8, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hartmut Ruelke, Christof Streck, Kai Frohberg
  • Patent number: 8772182
    Abstract: A semiconductor device manufacture method has the steps of: (a) coating a low dielectric constant low-level insulating film above a semiconductor substrate formed with a plurality of semiconductor elements; (b) processing the low-level insulating film to increase a mechanical strength of the low-level insulating film; (c) coating a low dielectric constant high-level insulating film above the low-level insulating film; and (d) forming a buried wiring including a wiring pattern in the high-level insulating film and a via conductor in the low-level insulating film. The low-level insulating film and high-level insulating film are made from the same material. The process of increasing the mechanical strength includes an ultraviolet ray irradiation process or a hydrogen plasma applying process.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: July 8, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yoshiyuki Ohkura
  • Patent number: 8772106
    Abstract: Memory devices are described along with methods for manufacturing and methods for operating. A memory device as described herein includes a plurality of memory cells located between word lines and bit lines. Memory cells in the plurality of memory cells comprise a diode and a metal-oxide memory element programmable to a plurality of resistance states including a first and a second resistance state, the diode of the memory element arranged in electrical series along a current path between a corresponding word line and a corresponding bit line. The device further includes bias circuitry to apply bias arrangements across the series arrangement of the diode and the memory element of a selected memory cell in the plurality of memory cells.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: July 8, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Ming-Daou Lee, Erh-Kun Lai, Kuang-Yeu Hsieh, Wei-Chih Chien, Chien Hung Yeh
  • Patent number: 8772179
    Abstract: According to one embodiment, a pattern forming method using a template containing a pattern that has at least one recess section or protrusion section to transfer the shape of the pattern to a resin layer on a substrate, is provided. The method includes a process for coating the resin on the substrate, a process for making the hardness of the first portion as a portion of the resin higher than the hardness of the second portion as the portion other than the first portion, and a process in which the portion other than the pattern of the template makes contact with the first portion, in a state where a gap is maintained between the template and the resin, the shape of the pattern is transferred to the second portion, and the resin is cured. Embodiments of an apparatus for pattern forming are also provided.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: July 8, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Fukuhara, Masayuki Hatano
  • Patent number: 8764993
    Abstract: A method of making a porous SiOC membrane is provided. The method comprises disposing a SiOC layer on a porous substrate, and etching the SiOC layer to form through pores in the SiOC layer. A porous SiOC membrane having a network of pores extending through a thickness of the membrane is provided.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: July 1, 2014
    Assignee: General Electric Company
    Inventors: Atanu Saha, Salil Mohan Joshi, An-Ping Zhang
  • Patent number: 8765233
    Abstract: A method of forming a low-carbon silicon-containing film by CVD on a substrate having trenches includes: introducing a silicon-containing compound having three or less hydrocarbon units in its molecule and having a boiling temperature of 35° C. to 220° C.; applying RF power to the gas; and depositing a film on a substrate having trenches wherein the substrate is controlled at a temperature such that components of the silicon-containing compound are at least partially liquidified on the substrate, thereby filling the trenches with the film.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: July 1, 2014
    Assignee: ASM Japan K.K.
    Inventors: Atsuki Fukazawa, Hisashi Tazawa, Shigeyuki Onizawa
  • Patent number: 8767411
    Abstract: During manufacture of an electronic device, an aerogel coating is applied to a first side of an IC substrate of a first IC. A bonding procedure is initiated, during which IC interconnects are either placed on the coated side of the substrate or on the opposite side of the substrate. The first IC is connected on a carrier to a second IC with the coated side of the first IC facing the second IC to reduce heat transmission to the second IC during operation of the first IC. The aerogel coating reduces thermal stress to the circuit board and surrounding components, reduces the risk of overheating of critical circuit components, provides chemical and mechanical insulation from contamination during subsequent wafer handling operations, and provides a thermal isolator between IC regions of dissimilar power dissipation, which isolator facilitates efficient thermal extraction from localized hotspots.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Martin P. Goetz, Gary E. O'Neil
  • Publication number: 20140179118
    Abstract: A surface treatment method for a semiconductor device includes providing a substrate where a plurality of projected patterns are formed, forming a hydrophobic coating layer on a surface of each of the plurality of projected patterns, rinsing the substrate with deionized water, and drying the substrate, wherein the hydrophobic coating layer is formed using a coating agent that includes phosphate having more than one hydrocarbon group, phosphonate having more than one hydrocarbon group, or a mixture thereof.
    Type: Application
    Filed: March 15, 2013
    Publication date: June 26, 2014
    Applicant: SK hynix Inc.
    Inventors: Sung-Hyuk CHO, Hyo-Sang KANG, Sung-Ki PARK, Kwon HONG, Hyung-Soon PARK, Hyung-Hwan KIM, Young-Bang LEE, Ji-Hye HAN, Tae-Yeon JUNG, Hyeong-Jin NOR
  • Publication number: 20140175615
    Abstract: A method for manufacturing a semiconductor device includes: forming a semiconductor element on a main surface of a substrate; forming a low melting glass film having a melting point of 450° C. or less on the main surface and the semiconductor element; heat treating the substrate while pressing the low melting glass film toward the main surface of the substrate with a pressurizing jig that is insulating or semi-insulating, and sintering the low melting glass film; and leaving the pressurizing jig on the low melting glass film after sintering the low melting glass film.
    Type: Application
    Filed: September 25, 2013
    Publication date: June 26, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yoichi Nogami, Yoshitsugu Yamamoto, Yoshinori Yokoyama, Shinnosuke Soda
  • Publication number: 20140179119
    Abstract: A method of forming a carbon-rich silicon carbide-like dielectric film having a carbon concentration of greater than, or equal to, about 30 atomic % C and a dielectric constant of less than, or equal to, about 4.5 is provided. The dielectric film may optionally include nitrogen. When nitrogen is present, the carbon-rich silicon carbide-like dielectric film has a concentration nitrogen that is less than, or equal, to about 5 atomic % nitrogen.
    Type: Application
    Filed: February 28, 2014
    Publication date: June 26, 2014
    Applicants: GLOBALFOUNDRIES, INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alfred Grill, Joshua L. Herman, Son Nguyen, E. Todd Ryan, Hosadurga K. Shobha
  • Patent number: 8759148
    Abstract: A method of mounting a semiconductor chip includes: forming a resin coating on a surface of a path connecting a bonding pad on a surface of a semiconductor chip and an electrode pad formed on a surface of an insulating base material; forming, by laser beam machining, a wiring gutter having a depth that is equal to or greater than a thickness of the resin coating along the path for connecting the bonding pad and the electrode pad; depositing a plating catalyst on a surface of the wiring gutter; removing the resin coating; and forming an electroless plating coating only at a site where the plating catalyst remains.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 24, 2014
    Assignee: Panasonic Corporation
    Inventors: Shingo Yoshioka, Hiroaki Fujiwara
  • Patent number: 8759232
    Abstract: The present disclosure provides manufacturing techniques and semiconductor devices in which performance of P-channel transistors may be enhanced on the basis of a stress mechanism that involves the deposition of a dielectric bi-layer system. Contrary to conventional strategies, an additional pre-treatment may be performed prior to the deposition of an adhesion layer in a plasma-free process atmosphere, thereby enabling a reduced thickness of the adhesion layer and a higher internal stress level of the subsequent top layer.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: June 24, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Joerg Hohage, Hartmut Ruelke, Ralf Richter
  • Patent number: 8759146
    Abstract: A method of forming a material comprises conducting an ALD layer cycle of a first metal, the ALD layer cycle comprising a reactive first metal precursor and a co-reactive first metal precursor. An ALD layer cycle of a second metal is conducted, the ALD layer cycle comprising a reactive second metal precursor and a co-reactive second metal precursor. An ALD layer cycle of a third metal is conducted, the ALD layer cycle comprising a reactive third metal precursor and a co-reactive third metal precursor. The ALD layer cycles of the first metal, the second metal, and the third metal are repeated to form a material, such as a GeSbTe material, having a desired stoichiometry. Additional methods of forming a material, such as a GeSbTe material, are disclosed, as is a method of forming a semiconductor device structure including a GeSbTe material.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: June 24, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Publication number: 20140170860
    Abstract: Substrate processing uniformity is improved in the surfaces of wafers and between the wafers. A method of manufacturing a semiconductor device, including: loading a substrate holder into an inner tube, the substrate holder holding a plurality of substrates in a state where the plurality of substrates are horizontally oriented and stacked; forming thin films on the plurality of substrates by supplying a source gas to an inside of the inner tube; and unloading the substrate holder from the inner tube, wherein the forming the thin films is performed in a state where a conductance of a space between an inner wall of the inner tube and a gas penetration preventing cylinder is smaller than a conductance of a region where the plurality of substrates are stacked.
    Type: Application
    Filed: February 19, 2014
    Publication date: June 19, 2014
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Hirohisa YAMAZAKI, Satoshi OKADA, Tsutomu KATO
  • Publication number: 20140170859
    Abstract: A film formation device to conduct a film formation process for a substrate includes a rotating table, a film formation area configured to include a process gas supply part, a plasma processing part, a lower bias electrode provided at a lower side of a position of a height of the substrate on the rotating table, an upper bias electrode arranged at the same position of the height or an upper side of a position of the height, a high-frequency power source part connected to at least one of the lower bias electrode and the upper bias electrode and configured to form a bias electric potential on the substrate in such a manner that the lower bias electrode and the upper bias electrode are capacitively coupled, and an exhaust mechanism.
    Type: Application
    Filed: December 9, 2013
    Publication date: June 19, 2014
    Applicant: Tokyo Electron Limited
    Inventors: Jun YAMAWAKU, Chishio Koshimizu, Yohei Yamazawa, Mitsuhiro Tachibana, Hitoshi Kato, Takeshi Kobayashi, Shigehiro Miura, Takafumi Kimura
  • Publication number: 20140162465
    Abstract: Apparatuses and methods are provided for electrostatically inhibiting particle contamination of a surface of a process structure, such as a mask or reticle. The apparatuses include a plasma-generating system configured to establish a plasma shield over the surface of the process structure. The plasma shield includes a plasma region and a plasma sheath over the surface of the process structure, with the plasma sheath being disposed, at least partially, adjacent to the surface of the process structure, between the plasma region and the surface of the process structure. The plasma shield facilitates negatively charging particles within the plasma shield, and electrostatically inhibits negatively-charged particle contamination of the surface of the process structure to be protected.
    Type: Application
    Filed: December 11, 2012
    Publication date: June 12, 2014
    Applicants: BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOIS, SEMATECH, INC.
    Inventors: John R. SPORRE, Vibhu JINDAL, David RUZIC
  • Publication number: 20140162425
    Abstract: A method for forming a dielectric film is disclosed. The method includes (a) exposing a substrate to a first gas pulse having a first oxygen-containing gas in a chamber; (b) exposing the substrate to multiple consecutive second gas pulses having a second oxygen-containing gas in the chamber, wherein the first oxygen-containing gas is different from the second oxygen-containing gas; and (c) sequentially after (a) and (b), exposing the substrate to a third gas pulse having a metal-containing gas in the chamber. Steps (a), (b), and (c) may be repeated any number of times to form the dielectric film with a predetermined thickness.
    Type: Application
    Filed: December 7, 2012
    Publication date: June 12, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Liang-Chen Chi, Chia-Ming Tsai, Yu-Min Chang, Chin-Kun Wang, Miin-Jang Cheng, Keng-Ham Lin
  • Patent number: 8748325
    Abstract: A polyimide film is effectively formed on a complicated surface. The polyimide film is formed by reacting, on the surface, diamine monomer and tetracarboxylic acid dianhydride monomer both of which are dissolved within carbon dioxide in a supercritical states, together with a polyamic acid resulting from a reaction between the diamine monomer and the tetracarboxylic acid dianhydride reached to the surface.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: June 10, 2014
    Inventors: Mitsuhiro Horikawa, Hiroyuki Ode, Masashi Haruki, Shigeki Takishima, Shinichi Kihara
  • Publication number: 20140154890
    Abstract: A periphery coating unit performs a scan-in process of moving a resist liquid nozzle 27 from an outside of an edge Wb of a wafer W to a position above a periphery region Wc of the wafer W while rotating the wafer W and discharging a resist liquid from the resist liquid nozzle 27; and a scan-out process of moving the resist liquid nozzle 27 from the position above the periphery region Wc of the wafer W to the outside of the edge Wb of the wafer W while rotating the wafer W and discharging the resist liquid from the resist liquid nozzle 27. Further, in the scan-out process, the resist liquid nozzle 27 is moved at a speed v2 lower than a speed v3 at which the resist liquid is moved to a side of the edge Wb of the wafer W.
    Type: Application
    Filed: December 3, 2013
    Publication date: June 5, 2014
    Applicant: Tokyo Electron Limited
    Inventors: Shinichi Hatakeyama, Yoshitomo Sato, Kazuyuki Tashiro, Naofumi Kishita
  • Patent number: 8741759
    Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming a gate stack over a substrate, forming spacers adjoining opposite sidewalls of the gate stack, forming a sacrificial layer adjoining the spacers, removing a portion of the sacrificial layer, removing a portion of the spacers to form a recess cavity below the left spacers. Then, a strain feature is formed in the recess cavity. The disclosed method provides an improved method by providing a space between the spacer and the substrate for forming the strained feature, therefor, to enhance carrier mobility and upgrade the device performance.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yu-Lien Huang
  • Patent number: 8741784
    Abstract: A process for fabricating a semiconductor device is described. A silicon oxide layer is formed. A nitridation process including at least two steps is performed to nitridate the silicon oxide layer into a silicon oxynitride (SiON) layer. The nitridation process comprises a first nitridation step and a second nitridation step in sequence, wherein the first nitridation step and the second nitridation step are different in the setting of at least one parameter.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: June 3, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Liang Lin, Te-Lin Sun, Ying-Wei Yen, Yu-Ren Wang
  • Patent number: 8741396
    Abstract: An amorphous carbon film, which has excellent etching resistance and is capable of reducing reflectance when a resist film is exposed to light, is form. A method for manufacturing a semiconductor device includes forming an object film to be etched on a wafer, supplying a process gas containing a CO gas and an N2 gas into a processing container, forming an amorphous carbon nitride film from the supplied CO gas and N2 gas, forming a silicon oxide film on the amorphous carbon nitride film, forming an ArF resist film on the silicon oxide film, patterning the ArF resist film, etching the silicon oxide film by using the ArF resist film as a mask, etching the amorphous carbon nitride film by using the silicon oxide film as a mask, and etching the object film to be etched by using the amorphous carbon nitride film as a mask.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: June 3, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Hiraku Ishikawa, Eiichi Nishimura
  • Patent number: 8741786
    Abstract: A disclosed fabrication method of a semiconductor device includes steps of depositing a dielectric film on a semiconductor substrate; thermally treating the dielectric film; and irradiating an ionized gas cluster onto the thermally treated dielectric film.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: June 3, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Koji Akiyama, Hirokazu Higashijima, Yoshitsugu Tanaka, Yasushi Akasaka, Koji Yamashita
  • Patent number: 8741746
    Abstract: A monolayer or partial monolayer sequencing processing, such as atomic layer deposition (ALD), can be used to form a semiconductor structure of a silicon film on a germanium substrate. Such structures may be useful in high performance electronic devices. A structure may be formed by deposition of a thin silicon layer on a germanium substrate surface, forming a hafnium oxide dielectric layer, and forming a tantalum nitride electrode. The properties of the dielectric may be varied by replacing the hafnium oxide with another dielectric such as zirconium oxide or titanium oxide.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: June 3, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8741161
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming a pillar on a base layer, forming a insulating layer on the base layer to cover the pillar by using GCIB method, where a lowermost portion of an upper surface of the insulating layer is lower than an upper surface of the pillar, and polishing the insulating layer and the pillar to expose a head of the pillar by using CMP method, where an end point of the polishing is the lowermost portion of the upper surface of the insulating layer.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: June 3, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuyuki Sonoda, Kyoichi Suguro, Masatoshi Yoshikawa, Koji Yamakawa, Katsuaki Natori, Daisuke Ikeno
  • Patent number: 8735305
    Abstract: In some embodiments, the present invention discloses a gate dielectric deposition process, including depositing a fluorinated hafnium oxide by an ALD process utilizing a fluorinated hafnium precursor and an oxidant. A two-step ALD deposition process can be used, including a fluorinated hafnium oxide layer deposition followed by a hafnium oxide layer deposition. Hafnium oxide can provide high dielectric constant, high density, large bandgap and good thermal stability. Fluorinated hafnium oxide can passivate interface states and bulk traps in the hafnium oxide, for example, by forming Si—F or Hf—F bonds, which can improve the reliability of the hafnium oxide gate dielectrics.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: May 27, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Jinhong Tong
  • Patent number: 8736014
    Abstract: A semiconductor device and method for making such that provides improved mechanical strength is disclosed. The semiconductor device comprises a semiconductor substrate; an adhesion layer disposed over the semiconductor substrate; and a porous low-k film disposed over the semiconductor substrate, wherein the porous low-k film comprises a porogen and a composite bonding structure including at least one Si—O—Si bonding group and at least one bridging organic functional group.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Jiun Lin, Ching-Yu Lo, Hai-Ching Chen, Tien-I Bao, Chen-Hua Yu
  • Patent number: 8736051
    Abstract: A semiconductor device includes an interlayer insulating film containing Si, O, C, and H, an under-bump metal film disposed over the interlayer insulating film and containing Ni, and a bump electrode disposed over the under-bump metal film. In the interlayer insulating film, a ratio of a peak height of Si—CH3 near a wave number 1270 cm?1 to a peak height of Si—O near a wave number 1030 cm?1 obtained by Fourier-transform infrared spectroscopy (FTIR) is 0.15 or greater and 0.27 or less. A ratio of a peak height of Si—CH2—Si near a wave number 1360 cm?1 to the peak height of Si—CH3 near the wave number 1270 cm?1 is 0.031 or greater.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: May 27, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuya Usami, Tomoyuki Nakamura, Naoki Fujimoto
  • Publication number: 20140141624
    Abstract: It is an object of the present invention to provide a method of and an apparatus for manufacturing a tunnel barrier layer or a gate insulator film with good film quality and film thickness uniformity. The present invention is characterized in that, a shield is configured to shield a region of a substrate to which an erosion region of a target is projected along a normal from a surface of the target and sputtered particles are configured to deposit on the substrate linearly moved when passing through an opening formed in the shield.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 22, 2014
    Applicant: IZA CORPORATION
    Inventor: Noel Abarra
  • Publication number: 20140138695
    Abstract: A method for producing a low temperature polycrystalline silicon thin film, comprising steps of: providing a substrate; forming a thermal conduction and electrical insulation layer, a buffer layer and an amorphous silicon layer on the substrate in this order; and performing a high-temperature treatment and a laser annealing on the amorphous silicon layer to convert the amorphous silicon layer to a polycrystalline silicon thin film, wherein the thermal conduction and electrical insulation layer comprises regular patterns distributed on the substrate.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 22, 2014
    Applicant: Boe Technology Group Co., Ltd.
    Inventors: Xueyan TIAN, Chunping LONG
  • Patent number: 8728956
    Abstract: Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by the following operations: (a) exposing the substrate surface to a first reactant in vapor phase under conditions allowing the first reactant to adsorb onto the substrate surface; (b) exposing the substrate surface to a second reactant in vapor phase while the first reactant is adsorbed on the substrate surface; and (c) exposing the substrate surface to plasma to drive a reaction between the first and second reactants adsorbed on the substrate surface to form the film.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: May 20, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Adrien LaVoie, Shankar Swaminathan, Hu Kang, Ramesh Chandrasekharan, Tom Dorsh, Dennis M. Hausmann, Jon Henri, Thomas Jewell, Ming Li, Bryan Schlief, Antonio Xavier, Thomas W. Mountsier, Bart J. van Schravendijk, Easwar Srinivasan, Mandyam Sriram
  • Patent number: 8728953
    Abstract: A method of processing a semiconductor workpiece includes placing a back surface of the workpiece on a workpiece support in a chamber so that the front surface of the workpiece faces into the chamber for processing, and the back surface is in fluid communication with a back region having an associated back gas pressure. The method further includes performing a workpiece processing step at a first chamber pressure Pc1 and a first back pressure Pb1, wherein Pc1 and Pb1 give rise to a pressure differential, Pb1?Pc1, and performing a workpiece cooling step at a second chamber pressure Pc2 and a second back pressure Pb2, wherein Pc2 and Pb2 are higher than Pc1 and Pb1, respectively.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: May 20, 2014
    Assignee: SPTS Technologies Limited
    Inventors: Stephen R Burgess, Anthony P Wilby
  • Publication number: 20140131832
    Abstract: A method for manufacturing a semiconductor device includes providing a substrate having a mask layer formed thereon, providing a first photomask having a first layout pattern and a second photomask having a second layout pattern, the first layout pattern including a plurality of active area portions and at least a neck portion connecting two adjacent active area portions, transferring the first layout pattern from the first photomask to the mask layer to form a plurality of active area patterns and at least a neck pattern connecting two adjacent active area patterns in the mask layer, and transferring the second layout pattern from the second photomask to the mask layer to remove the neck pattern to form a patterned mask. The patterned mask includes the active area patterns. A slot is at least formed between the two adjacent active area patterns.
    Type: Application
    Filed: November 13, 2012
    Publication date: May 15, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Shiang Yang, Cheng-Te Wang
  • Patent number: 8722546
    Abstract: A method of forming a dielectric film having Si—C bonds and/or Si—N bonds on a semiconductor substrate by cyclic deposition, includes: (i) conducting one or more cycles of cyclic deposition in a reaction space wherein a semiconductor substrate is placed, using a Si-containing precursor and a reactant gas; and (ii) before or after step (i), applying a pulse of RF power to the reaction space while supplying a rare gas and a treatment gas without supplying a Si-containing precursor, whereby a dielectric film having Si—C bonds and/or Si—N bonds is formed on the semiconductor substrate.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: May 13, 2014
    Assignee: ASM IP Holding B.V.
    Inventors: Atsuki Fukazawa, Takahiro Oka
  • Publication number: 20140127855
    Abstract: Method for the oriented crystallization of materials. The present invention relates to a method useful for orienting the crystallization of a material over a surface zone of at least one face of a substrate, comprising at least the steps consisting in: i. determining, on said face, the surface over which the crystalline deposit must be formed, referred to as the zone of interest, ii. depositing, on said face and at the periphery of said zone of interest, at least one particle dedicated to forming a crystallization nucleus, iii. bringing said particle into contact with at least said material to be crystallized, iv.
    Type: Application
    Filed: April 23, 2012
    Publication date: May 8, 2014
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Mohammed Benwadih
  • Patent number: 8716150
    Abstract: Methods of forming a semiconductor device are provided. The methods include, for example, forming a low-k dielectric having a continuous planar surface, and, after forming the low-k dielectric, subjecting the continuous planar surface of the low-k dielectric to an ethylene plasma enhanced chemical vapor deposition (PECVD) treatment.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: May 6, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Zhiguo Sun, Songkram Srivathanakul, Huang Liu, Hung-Wei Liu
  • Patent number: 8716156
    Abstract: One illustrative method disclosed herein includes forming a mandrel structure above a semiconductor substrate, performing an oxidation process to oxidize at least a portion of the mandrel structure so as to thereby define oxidized regions on the mandrel structure, removing the oxidized regions to thereby defined a reduced thickness mandrel structure, forming a plurality of fins on the reduced thickness mandrel structure and performing an etching process to selectively remove at least a portion of the reduced thickness mandrel structure so as to thereby expose at least a portion of each of the fins.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: May 6, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Bartlomiej Jan Pawlak, Steven Bentley, Ajey Jacob
  • Patent number: 8716125
    Abstract: Embodiments of the present invention provide methods of in-situ vapor phase deposition of self-assembled monolayers as copper adhesion promoters and diffusion barriers. A copper region is formed in a dielectric layer. A diffusion barrier comprising a self-assembled monolayer is deposited over the copper region. A capping layer is deposited over the self-assembled monolayer. In some embodiments, the capping layer and self-assembled monolayer are deposited in the same process chamber.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: May 6, 2014
    Assignee: Globalfoundries Inc.
    Inventor: Jinhong Tong
  • Patent number: 8716155
    Abstract: Methods of improving charge trapping are disclosed. One such method includes forming an oxide-nitride-oxide tunnel stack and a silicon nitride layer on the oxide-nitride-oxide tunnel stack. This silicon nitride layer is implanted with ions. These ions may function as electron traps or as fields. The silicon nitride layer may be part of a flash memory device.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: May 6, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Deepak A. Ramappa, Kyu-Ha Shim
  • Publication number: 20140120739
    Abstract: A sol composition for producing a porous low-k dielectric material is provided. The composition can include at least one silicate ester, a polar solvent, water, an acid catalyst for silicate ester hydrolysis, an amphiphilic block copolymer surfactant, and a nonmetallic catalyst that reduces dielectric constant in the produced material. The composition can further include a metallic ion at a lower parts-per-million concentration than the nonmetallic catalyst, and/or the composition can further include a cosolvent. A method of preparing a thin film on a substrate using the sol composition is also provided.
    Type: Application
    Filed: October 31, 2013
    Publication date: May 1, 2014
    Inventors: Mark L.F. Phillips, Travis Savage
  • Publication number: 20140117529
    Abstract: Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. The photoresist features are trimmed, which punches through the narrowed region to form a gap. Spacers are formed along sidewalls of the photoresist features. Two of the spacers merge within the gap. The photoresist features are removed to leave a pattern comprising the spacers. The pattern is extended into the substrate to form a plurality of recesses within the substrate. Electrically conductive material is formed within the recesses to create the electrically conductive lines. Some embodiments include semiconductor constructions having a plurality of lines over a semiconductor substrate. Two of the lines are adjacent to one another and are substantially parallel to one another except in a region wherein said two of the lines merge into one another.
    Type: Application
    Filed: October 25, 2012
    Publication date: May 1, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Vishal Sipani, Kyle Armstrong, Michael D. Hyatt, Michael Dean Van Patten, David A. Kewley, Ming-Chuan Yang
  • Publication number: 20140120738
    Abstract: A method for forming a silicon germanium oxide thin film on a substrate in a reaction space may be performed using an atomic layer deposition (ALD) process. The process may include at least one cycle comprising a germanium oxide deposition sub-cycle and a silicon oxide deposition sub-cycle. The germanium oxide deposition sub-cycle may include contacting the substrate with a germanium reactant, removing excess germanium reactant, and contacting the substrate with a first oxygen reactant. The silicon oxide deposition sub-cycle may include contacting the substrate with a silicon reactant, removing excess silicon reactant, and contacting the substrate with a second oxygen reactant. The films of the present disclosure exhibit desirable etch rates relative to thermal oxide. Depending on the films' composition, the etch rates may be higher or lower than the etch rates of thermal oxide.
    Type: Application
    Filed: October 30, 2013
    Publication date: May 1, 2014
    Inventors: In Soo JUNG, Eun Kee HONG, Seung Woo CHOI, Dong Seok KANG, Yong Min YOO, Pei-Chung HSIAO
  • Patent number: 8710682
    Abstract: The present invention provides polyimide polymer materials for passivating semiconductor wafers and methods for fabricating thereof. The present invention further provides a device that includes a semiconductor wafer and a passivating layer disposed on the surface of the wafer, wherein the passivating layer comprises such polyimide polymers.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 29, 2014
    Assignee: Designer Molecules Inc, Inc.
    Inventors: Stephen M Dershem, Farhad G Mizori, James T Huneke
  • Patent number: 8709956
    Abstract: BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: April 29, 2014
    Assignee: Avalanche Technology Inc.
    Inventors: Kimihiro Satoh, Yiming Hual, Jing Zhang, Ebrahim Abedlfard
  • Publication number: 20140113457
    Abstract: The embodiments herein focus on plasma enhanced atomic layer deposition (PEALD) processes using pulsed plasmas. While conventional PEALD processes use continuous wave plasmas during the plasma exposure/conversion operation, the embodiments herein utilize a pulsed plasma during this operation to achieve a film with high quality sidewalls. Because conventional PEALD techniques result in films having high quality at the bottom and top of a feature, but low quality on the sidewalls, this increased sidewall quality in the disclosed methods corresponds to a film that is overall more uniform in quality compared to that achieved with conventional continuous wave plasma techniques.
    Type: Application
    Filed: December 30, 2013
    Publication date: April 24, 2014
    Inventors: James S. Sims, Jon Henri, Kathryn M. Kelchner, Sathish Babu S. V. Janjam, Shane Tang