Insulative Material Deposited Upon Semiconductive Substrate Patents (Class 438/778)
  • Patent number: 9587308
    Abstract: A cleaning method includes performing a first cleaning process of supplying a fluorine-based gas from a first nozzle heated to a first temperature and a nitrogen oxide-based gas from a second nozzle heated to a first temperature into a process chamber heated to the first temperature in order to remove on surfaces of members in the process chamber by a thermochemical reaction, changing in internal temperature of the process chamber to a second temperature higher than the first temperature, and performing a second cleaning process of supplying a fluorine-based gas from the first nozzle heated to the second temperature into the process chamber heated to the second temperature in order to remove substances remaining on the surfaces of the members in the process chamber after removing the deposits by the thermochemical reaction and to remove deposits deposited in the first nozzle by the thermochemical reaction.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: March 7, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Kenji Kameda, Ryuji Yamamoto, Yuji Urano
  • Patent number: 9551070
    Abstract: Corrosion resistant substrate supports and methods of making corrosion resistant substrate supports are provided herein. In some embodiments, a method of making corrosion resistant substrate supports includes exposing the substrate support disposed within a substrate processing chamber to a process gas comprising an aluminum containing precursor; and depositing an aluminum containing layer atop surfaces of the substrate support.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: January 24, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Mei Chang, Chien-Teh Kao, Juno Yu-Ting Huang
  • Patent number: 9548241
    Abstract: Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: January 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Huan Lee, Shau-Lin Shue, Keith Kuang-Kuo Koai, Hai-Ching Chen, Tung-Ching Tseng, Wen-Cheng Yang, Chung-En Kao, Ming-Han Lee, Hsin-Yen Huang
  • Patent number: 9543140
    Abstract: Methods of depositing boron and carbon containing films are provided. In some embodiments, methods of depositing B,C films with desirable properties, such as conformality and etch rate, are provided. One or more boron and/or carbon containing precursors can be decomposed on a substrate at a temperature of less than about 400° C. In some embodiments methods of depositing silicon nitride films comprising B and C are provided. A silicon nitride film can be deposited by a deposition process including an ALD cycle that forms SiN and a CVD cycle that contributes B and C to the growing film.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: January 10, 2017
    Assignee: ASM IP HOLDING B.V.
    Inventor: Viljami Pore
  • Patent number: 9530617
    Abstract: Some embodiments relate to a method for semiconductor processing. In this method, a semiconductor wafer is provided. A surface region of the semiconductor wafer is probed to determine whether excess charge is present on the surface region. Based on whether excess charge is present, selectively inducing a corona discharge to reduce the excess charge. Other techniques are also provided.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: December 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lin-Jung Wu, Jyh-Shiou Hsu, Chi-Ming Yang
  • Patent number: 9514951
    Abstract: A substrate processing method can remove a part of a processing target film formed on a surface of a substrate W under a normal pressure atmosphere while suppressing an influence upon the substrate. A source material of the processing target film, which is decomposed by irradiating an ultraviolet ray thereto under an oxygen-containing atmosphere, is coated on the substrate W, and the processing target film is formed by heating the source material coated on the substrate W. Then, the substrate W having thereon the processing target film is placed within a processing chamber under the oxygen-containing atmosphere where a gas flow velocity is equal to or smaller than 10 cm/sec, and the part of the processing target film is removed by irradiating the ultraviolet ray to the substrate W.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: December 6, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Masatoshi Kaneda, Yuzo Ohishi, Keisuke Yoshida
  • Patent number: 9514946
    Abstract: An improvement is achieved in the performance of a semiconductor device including a memory element. Over a semiconductor substrate, a gate electrode for the memory element is formed via an insulating film as a gate insulating film for the memory element. The insulating film includes first, second, third, fourth, and fifth insulating films in order of being apart from the substrate. The second insulating film has a charge storing function. The band gap of each of the first and third insulating films is larger than a band gap of the second insulating film. The band gap of the fourth insulating film is smaller than the band gap of the third insulating film. The band gap of the fifth insulating film is smaller than the band gap of the fourth insulating film.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: December 6, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Masao Inoue, Yoshiki Maruyama, Tomoya Saito, Atsushi Yoshitomi
  • Patent number: 9508549
    Abstract: Methods of forming an electronic device comprise: (a) providing a semiconductor substrate comprising a porous feature on a surface thereof; (b) applying a composition over the porous feature, wherein the composition comprises a polymer and a solvent, wherein the polymer comprises a repeat unit of the following general formula (I): wherein: Ar1, Ar2, Ar3 and Ar4 independently represent an optionally substituted divalent aromatic group; X1 and X2 independently represent a single bond, —O—, —C(O)—, —C(O)O—, —OC(O)—, —C(O)NR1—, —NR2C(O)—, —S—, —S(O)—, —SO2— or an optionally substituted C1-20 divalent hydrocarbon group, wherein R1 and R2 independently represent H or a C1-20 hydrocarbyl group; m is 0 or 1; n is 0 or 1; and o is 0 or 1; and (c) heating the composition; wherein the polymer is disposed in pores of the porous feature. The methods find particular applicability in the manufacture of semiconductor devices for forming low-k and ultra-low-k dielectric materials.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: November 29, 2016
    Assignees: Dow Global Technologies LLC, Rohm and Haas Electronic Materials LLC
    Inventors: Jong Keun Park, Phillip D. Hustad, Emad Aqad, Mingqi Li, Cheng-Bai Xu, Peter Trefonas, III, James W. Thackeray
  • Patent number: 9496746
    Abstract: A wireless power transmission system is provided for high power applications. The power transmission system is comprised generally of a charging unit configured to generate an alternating electromagnetic field and a receive unit configured to receive the alternating electromagnetic field from the charging unit. The charging unit includes a power source; an input rectifier; an inverter; and a transmit coil. The transmit coil has a spirangle arrangement segmented into n coil segments with capacitors interconnecting adjacent coil segments. The receive unit includes a receive coil and an output rectifier. The receive coil also has a spirangle arrangement segmented into m coil segments with capacitors interconnecting adjacent coil segments.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: November 15, 2016
    Assignee: The Regents Of The University Of Michigan
    Inventors: Chris Mi, Siqi Li, Trong-Duy Nguyen, Junhua Wang, Jiangui Li, Weihan Li, Jun Xu
  • Patent number: 9455185
    Abstract: Disclosed is a process of annealing through silicon vias (TSVs) or other deeply buried metallic interconnects using a back side laser annealing process. The process provides several advantages including sufficient grain growth and strain relief of the metal such that subsequent thermal processes do not cause further grain growth; shorter anneal times thereby reducing cycle time of 3D device fabrication; and reduced pattern sensitivity of laser absorption.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: September 27, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oleg Gluschenkov, Andrew J. Martin, Joyeeta Nag
  • Patent number: 9425182
    Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: August 23, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenobu Maeda, Jeong Hwan Yang
  • Patent number: 9401396
    Abstract: Provided is a method for manufacturing a semiconductor device, in which a degradation of characteristics of a thin film transistor can be suppressed by performing plasma oxidation treatment on a gate insulating film containing nitrogen. An embodiment of the present invention is a method for manufacturing a semiconductor device comprising a thin film transistor including a gate electrode, a gate insulating film containing nitrogen, and a channel region in microcrystalline semiconductor films. The method includes the steps of performing plasma treatment on the gate insulating film in an oxidizing gas atmosphere containing hydrogen and an oxidizing gas containing an oxygen atom, and forming the microcrystalline semiconductor film over the gate insulating film. Formula (1), a/b?2, and Formula (2), b>0, are satisfied, where the amount of hydrogen and the amount of the oxidizing gas in the oxidizing gas atmosphere are a and b, respectively.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: July 26, 2016
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Kanta Abe, Hidekazu Miyairi, Tetsuhiro Tanaka, Takashi Ienaga, Yoshitaka Yamamoto
  • Patent number: 9385308
    Abstract: In a particular illustrative embodiment, a method of fabricating a semiconductor device is disclosed that includes forming a metal layer over a device substrate, forming a via in contact with the metal layer, and adding a dielectric layer above the via. The method further includes etching a portion of the dielectric layer to form a trench area, and depositing a perpendicular magnetic tunnel junction (MTJ) structure within the trench area.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: July 5, 2016
    Assignee: QUALCOMM Incorporated
    Inventor: Xia Li
  • Patent number: 9343294
    Abstract: A method for forming a semiconductor device includes forming a first dielectric layer overlying a substrate, forming at least a first opening in the first dielectric layer, forming a conformal dense layer lining the at least first opening in the first dielectric layer, forming a barrier layer overlying the conformal dense layer, forming a conductive feature in the at least first opening, removing a portion of the first dielectric layer between any two adjacent conductive features to form a second opening, wherein the second opening exposes the conformal dense layer between the two adjacent conductive features, and depositing between the two adjacent conductive features a second dielectric layer having an air gap formed therein.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: May 17, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Chi, Hung-Wen Su
  • Patent number: 9318365
    Abstract: A substrate processing apparatus for processing a substrate comprises: a plurality of chuck pins each having an accommodating groove for accommodating a portion of peripheral part of the substrate, holding the substrate at a hold position in a horizontal posture by pressing inner faces of the accommodating grooves toward portions of peripheral part of the substrate; and a plurality of guide members, being disposed on or above the respective plurality of chuck pins, guiding process liquid discharged from the substrate to a surrounding area of the substrate; wherein each of the plurality of guide member includes: an inner-edge guide disposed at a position inward and above the accommodating groove; and an outer-edge guide disposed at a position level with or below the inner-edge guide and outward the chuck pin.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: April 19, 2016
    Assignee: SCREEN Holdings Co., Ltd.
    Inventor: Takahiro Yamaguchi
  • Patent number: 9299957
    Abstract: A method of manufacturing an organic light-emitting display apparatus includes preparing a deposition target in which an organic light-emitting portion is formed on a substrate, forming a pre-encapsulation layer for encapsulating the organic light-emitting portion by using a facing target sputtering apparatus, and forming an encapsulation layer by performing a plasma surface process on the pre-encapsulation layer by using the facing target sputtering apparatus. The facing target sputtering apparatus includes a chamber in which a mounting portion for accommodating the deposition target is provided, a gas supply portion facing the mounting portion and supplying gas to the chamber, a first target portion and a second target portion disposed in the chamber and facing each other, and an induced magnetic field coil surrounding the exterior of the chamber.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: March 29, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventor: Su-Hyuk Choi
  • Patent number: 9263250
    Abstract: Provided is a method of forming a silicon nitride film on a surface to be processed of a target object, which includes: repeating a first process a first predetermined number of times, the process including supplying a silicon source gas containing silicon toward the surface to be processed and supplying a decomposition accelerating gas containing a material for accelerating decomposition of the silicon source gas toward the surface to be processed; performing a second process of supplying a nitriding gas containing nitrogen toward the surface to be processed a second predetermine number of times; and performing one cycle a third predetermined number of times, the one cycle being a sequence including the repetition of the first process and the performance of the second process to form the silicon nitride film on the surface to be processed.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: February 16, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akinobu Kakimoto, Kazuhide Hasebe
  • Patent number: 9230828
    Abstract: A device includes a semiconductor fin over a substrate, a gate dielectric on sidewalls of the semiconductor fin, and a gate electrode over the gate dielectric. A source/drain region is on a side of the gate electrode. A dislocation plane is in the source/drain region.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: January 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhiqiang Wu, Wen-Hsing Hsieh, Hua Feng Chen, Ting-Yun Wu, Carlos H. Diaz, Tzer-Min Shen, Ya-Yun Cheng
  • Patent number: 9196476
    Abstract: A thin film having a high resistance to HF and a low dielectric constant is formed with high productivity. A method of manufacturing a semiconductor device, includes performing a cycle a predetermined number of times, the cycle including: (a) supplying a source gas containing a predetermined element, carbon and a halogen element and having a chemical bond between the predetermined element and carbon to a substrate; and (b) supplying a reactive gas including a borazine compound to the substrate, wherein the cycle is performed under a condition where a borazine ring structure in the borazine compound and at least a portion of the chemical bond between the predetermined element and carbon in the source gas are preserved to form a thin film including the borazine ring structure and the chemical bond between the predetermined element and carbon on the substrate.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: November 24, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Atsushi Sano, Yoshiro Hirose
  • Patent number: 9190271
    Abstract: A thin film formation method to form an amorphous silicon film containing an impurity on a surface of an object to be processed in a process chamber that allows vacuum exhaust includes supplying a silane-based gas composed of silicon and hydrogen into the process chamber in a state that the silane-based gas is adsorbed onto the surface of the object without supplying an impurity-containing gas, supplying the impurity-containing gas into the process chamber to form the amorphous silicon film containing the impurity without supplying the silane-based gas, and performing the supplying of the silane-based gas and the supplying of the impurity-containing gas alternately and repeatedly such that the impurity reacts with the silane-based gas.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: November 17, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kazuhide Hasebe, Akinobu Kakimoto
  • Patent number: 9177791
    Abstract: Embodiments provided herein describe systems and methods for forming semiconductor devices. A semiconductor substrate is provided. The semiconductor substrate is exposed to bromine radicals, hydrogen radicals, or a combination thereof. An oxide layer is formed above the semiconductor substrate. The semiconductor substrate is held within a controlled atmosphere at least from the completion of the exposing of the semiconductor substrate to bromine radicals, hydrogen radicals, or a combination thereof and the beginning of the forming of the oxide layer.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: November 3, 2015
    Assignee: Intermolecular, Inc.
    Inventor: Khaled Ahmed
  • Patent number: 9171753
    Abstract: In one embodiment, the method includes forming a conductive via structure in a base layer. The base layer has a first surface and a second surface, and the second surface is opposite the first surface. The method further includes removing the second surface of the base layer to expose the conductive via structure such that the conductive via structure protrudes from the second surface, and forming a first lower insulating layer over the second surface such that an end surface of the conductive via structure remains exposed by the first lower insulating layer.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: October 27, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho-Jin Lee, Kyu-ha Lee, Gilheyun Choi, YongSoon Choi, Pil-Kyu Kang, Byung-Lyul Park, Hyunsoo Chung
  • Patent number: 9171716
    Abstract: A method of forming a metal oxide hardmask on a template includes: providing a template constituted by a photoresist or amorphous carbon formed on a substrate; and depositing by atomic layer deposition (ALD) a metal oxide hardmask on the template constituted by a material having a formula SixM(1-x)Oy wherein M represents at least one metal element, x is less than one including zero, and y is approximately two or a stoichiometrically-determined number.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: October 27, 2015
    Assignee: ASM JAPAN K.K.
    Inventor: Hideaki Fukuda
  • Patent number: 9163310
    Abstract: Embodiments relate to using radicals to at different stages of deposition processes. The radicals may be generated by applying voltage across electrodes in a reactor remote from a substrate. The radicals are injected onto the substrate at different stages of molecular layer deposition (MLD), atomic layer deposition (ALD), and chemical vapor deposition (CVD) to improve characteristics of the deposited layer, enable depositing of material otherwise not feasible and/or increase the rate of deposition. Gas used for generating the radicals may include inert gas and other gases. The radicals may disassociate precursors, activate the surface of a deposited layer or cause cross-linking between deposited molecules.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: October 20, 2015
    Assignee: VEECO ALD Inc.
    Inventor: Sang In Lee
  • Patent number: 9159781
    Abstract: Provided is a method for manufacturing a semiconductor device, in which a degradation of characteristics of a thin film transistor can be suppressed by performing plasma oxidation treatment on a gate insulating film containing nitrogen. An embodiment of the present invention is a method for manufacturing a semiconductor device comprising a thin film transistor including a gate electrode, a gate insulating film containing nitrogen, and a channel region in microcrystalline semiconductor films. The method includes the steps of performing plasma treatment on the gate insulating film in an oxidizing gas atmosphere containing hydrogen and an oxidizing gas containing an oxygen atom, and forming the microcrystalline semiconductor film over the gate insulating film. Formula (1), a/b?2, and Formula (2), b>0, are satisfied, where the amount of hydrogen and the amount of the oxidizing gas in the oxidizing gas atmosphere are a and b, respectively.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: October 13, 2015
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Kanta Abe, Hidekazu Miyairi, Tetsuhiro Tanaka, Takashi Ienaga, Yoshitaka Yamamoto
  • Patent number: 9153658
    Abstract: A gate insulating film of a conventional semiconductor device is subjected to dielectric breakdown at a low electric field strength and thus its service life is short. This is because since the size of the asperity of at least one of a semiconductor layer-side interface and an electrode-side interface is large and, an electric field applied to the gate insulating film is locally concentrated and has a variation in its strength. This problem is solved by specifying the sizes of the asperities of both interfaces of the gate insulating film.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: October 6, 2015
    Assignee: TOHOKU UNIVERSITY
    Inventors: Rihito Kuroda, Akinobu Teramoto, Shigetoshi Sugawa
  • Patent number: 9147618
    Abstract: A method of providing a semiconductor structure comprising a diffusion barrier layer and a seed layer, the seed layer comprising an alloy of copper and a metal other than copper, depositing an electrically conductive material on the seed layer, performing an annealing process, wherein at least a first portion of the metal other than copper diffuses away from a vicinity of the diffusion barrier layer through the electrically conductive material, and wherein, in case of a defect in the diffusion barrier layer, a second portion of the metal other than copper indicative of the defect remains in a vicinity of the defect, measuring a distribution of the metal other than copper in at least a portion of the semiconductor structure, and determining, from the measured distribution of the metal other than copper, if the second portion of the metal other than copper is present.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: September 29, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Frank Koschinsky, Bernd Hintze, Dirk Utess
  • Patent number: 9147589
    Abstract: A processing system includes a chamber and a steam source that supplies steam in the chamber. A UV source directs UV light onto a deposited layer of a substrate in the presence of the steam from the steam source for a predetermined conversion period to at least partially convert the deposited layer.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: September 29, 2015
    Assignee: NOVELLUS SYSTEMS, INC.
    Inventors: Bhadri N Varadarajan, Bart Van Schravendijk
  • Patent number: 9117657
    Abstract: A method for filling recesses of a substrate with an insulation film includes: (i) exposing surfaces of the recesses of the substrate to a pre-deposition gas in a reactive state in a reaction space to treat the surfaces with reactive hydrocarbons generated from the pre-deposition gas without filling the recesses; and (ii) depositing a flowable insulation film using a process gas other than the pre-deposition gas on a surface of the substrate to fill the recesses treated in step (i) therewith by plasma reaction. The pre-deposition gas has at least one hydrocarbon unit in its molecule.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: August 25, 2015
    Assignee: ASM IP HOLDING B.V.
    Inventors: Akinori Nakano, Shintaro Ueda
  • Patent number: 9117818
    Abstract: Techniques related to nanocomposite dielectric materials are generally described herein. These techniques may be embodied in apparatuses, systems, methods and/or processes for making and using such material. An example process may include: providing a film having a plurality of nanoparticles and an organic medium; comminuting the film to form a particulate; and applying the particulate to a substrate. The example process may also include providing a nanoparticle film having nanoparticles and voids located between the nanoparticles; contacting the film with a vapor containing an organic material; and curing the organic material to form the nanocomposite dielectric film. Various described techniques may provide nanocomposite dielectric materials with superior nanoparticle dispersion which may result in improved dielectric properties.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: August 25, 2015
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Seth Miller
  • Patent number: 9117653
    Abstract: A method for in-situ dry cleaning of a Ge containing semiconductor surface, other than SiGe. The method is conducted in a vacuum chamber. An oxygen monolayer(s) is formed and promotes removal of essentially all carbon from the surface, and serves to both clean and functionalize the surface. The Ge semiconductor surface is then annealed at a temperature below that which would induce dopant diffusion.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: August 25, 2015
    Assignee: The Regents of the University of California
    Inventors: Tobin Kaufman-Osborn, Andrew C. Kummel, Kiarash Kiantaj
  • Patent number: 9093268
    Abstract: Semiconductor devices including porous low-k dielectric layers and fabrication methods are provided. A dielectric layer is formed on a substrate by introducing and polymerizing a main reaction gas on a surface of the substrate. The main reaction gas has a chemical structure including a ring-shaped group, silicon, carbon, and hydrogen, and the ring-shaped group includes at least carbon and hydrogen. A porous low-k dielectric layer is then formed from the dielectric layer by curing the dielectric layer with UV light.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: July 28, 2015
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Ming Zhou
  • Patent number: 9076649
    Abstract: A method of forming a thin film on a surface of target objects in a vacuum-evacuable processing chamber by using a source gas and a reaction gas includes: forming a mixed gas by mixing the source gas and an inert gas in a gas reservoir tank, and supplying the mixed gas and the reaction gas into the processing chamber.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: July 7, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Keisuke Suzuki, Kentaro Kadonaga, Volker Hemel, Bernhard Zobel
  • Patent number: 9076874
    Abstract: An object is to provide a structure of a transistor which has a channel formation region formed using an oxide semiconductor and a positive threshold voltage value, which enables a so-called normally-on switching element. The transistor includes an oxide semiconductor stack in which at least a first oxide semiconductor layer and a second oxide semiconductor layer with different energy gaps are stacked and a region containing oxygen in excess of its stoichiometric composition ratio is provided.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: July 7, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Tatsuya Honda
  • Patent number: 9048294
    Abstract: Described are manganese-containing films, as well as methods for providing the manganese-containing films. Doping manganese-containing films with Co, Mn, Ru, Ta, Al, Mg, Cr, Nb, Ti or V allows for enhanced copper barrier properties of the manganese-containing films. Also described are methods of providing films with a first layer comprising manganese silicate and a second layer comprising a manganese-containing film.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: June 2, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Jing Tang, Zhefeng Li, Paul F. Ma, David Thompson
  • Patent number: 9049061
    Abstract: This invention discloses a CMOS device, which includes: a first MOSFET; a second MOSFET different from the type of the first MOSFET; a first stressed layer covering the first MOSFET and having a first stress; and a second stressed layer covering the second MOSFET, wherein the second stressed layer is doped with ions, and thus has a second stress different from the first stress. This invention's CMOS device and method for manufacturing the same make use of a partitioned ion implantation method to realize a dual stress liner, without the need of removing the tensile stressed layer on the PMOS region or the compressive stressed layer on the NMOS region by photolithography/etching, thus simplifying the process and reducing the cost, and at the same time, preventing the stress in the liner on the NMOS region or PMOS region from the damage that might be caused by the thermal process of the deposition process.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: June 2, 2015
    Assignee: The Institute of Microelectronics Chinese Academy of Science
    Inventors: Qiuxia Xu, Chao Zhao, Gaobo Xu
  • Publication number: 20150147892
    Abstract: A method for fabricating a semiconductor structure is provided, including: providing a solid precursor having a first average particle size; solving the solid precursor in an organic solvent into an intermediate; recrystallizing the intermediate to form solid granules, wherein the solid granules has a second average particle size larger than the first average particle size; vaporizing the solid granules to form a film-forming gas; and depositing the film-forming gas on a substrate to form a resistance film. A method for modifying a resistance film source in a semiconductor fabrication and a solid precursor delivery system are also provided. The method for fabricating a semiconductor structure in the present disclosure can remove small particles or ultra-small particles from solid precursor, and does not need extra time to dump cracked solid precursor.
    Type: Application
    Filed: November 27, 2013
    Publication date: May 28, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Liang CHENG, Chien-Hao TSENG, Yen-Yu CHEN, Ching-Chia WU, Chang-Sheng LEE, Wei ZHANG
  • Patent number: 9034774
    Abstract: This film forming method comprises: a first material gas supply step (A) wherein a first raw material gas is supplied over the substrate to be processed so that a first chemical adsorption layer, which is adsorbed on the substrate by means of the first raw material gas is formed on the substrate to be processed, a second material gas supply step (C) wherein a second raw material that is different from the first raw material gas is supplied over the substrate, on which the first chemical adsorption layer has been formed, so that a second chemical adsorption layer, which is adsorbed by means of the second raw material gas, is formed on the first chemical adsorption layer; and a plasma processing step (E) wherein a plasma processing is carried on at least the first and second chemical adsorption layers using microwave plasma.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: May 19, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Kouji Tanaka, Hirokazu Ueda
  • Publication number: 20150132972
    Abstract: A substrate processing apparatus includes: a reaction tube configured to accommodate a plurality of substrates and to be supplied with a gas generated by vaporizing or turning into mist a solution containing a reactant in a solvent; a lid configured to close the reaction tube; a first heater configured to heat the plurality of substrates; a thermal conductor placed on the lid on an upper surface thereof; a second heater placed outside the reaction tube around a side thereof, the second heater being configured to heat the gas flowing near the lid; and a heating element placed on the lid on a lower surface thereof, the heating element configured to heat the lid.
    Type: Application
    Filed: January 26, 2015
    Publication date: May 14, 2015
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Yuichi WADA, Hiroshi ASHIHARA, Hideto TATENO, Harunobu SAKUMA
  • Publication number: 20150132928
    Abstract: A technique for forming nanostructures including introducing a plurality of molecular-size scale and/or nanoscale building blocks to a region near a substrate and simultaneously scanning a pattern on the substrate with an energy beam, wherein the energy beam causes a change in at least one physical property of at least a portion of the building blocks, such that a probability of the portion of the building blocks adhering to the pattern scanned by the energy beam is increased, and wherein the building blocks adhere to the pattern to form the structure. The energy beam and at least a portion of the building blocks may interact by electrostatic interaction to form the structure.
    Type: Application
    Filed: January 20, 2015
    Publication date: May 14, 2015
    Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Joseph M. Jacobson, David Kong, Vikas Anant, Ashley Salomon, Saul Griffith, Will DelHagen, Vikrant Agnihotri
  • Publication number: 20150130027
    Abstract: A method of forming a carbon-containing thin film and a method of manufacturing a semiconductor device using the method of forming the carbon-containing thin film are described. The method of forming a carbon-containing thin film includes the steps of introducing a substrate into a chamber, injecting hydrocarbon gas and at least nitrogen gas simultaneously into the chamber, and depositing a carbon-containing thin film including carbon and nitrogen on the substrate, thereby forming a carbon-containing thin film having high selectivity and uniform thickness.
    Type: Application
    Filed: November 11, 2014
    Publication date: May 14, 2015
    Inventors: Se jun PARK, Ho jun KIM, Jaihyung WON, Gyuwan CHOI, Dohyung KIM
  • Patent number: 9027508
    Abstract: A periphery coating unit performs a scan-in process of moving a resist liquid nozzle 27 from an outside of an edge Wb of a wafer W to a position above a periphery region Wc of the wafer W while rotating the wafer W and discharging a resist liquid from the resist liquid nozzle 27; and a scan-out process of moving the resist liquid nozzle 27 from the position above the periphery region Wc of the wafer W to the outside of the edge Wb of the wafer W while rotating the wafer W and discharging the resist liquid from the resist liquid nozzle 27. Further, in the scan-out process, the resist liquid nozzle 27 is moved at a speed v2 lower than a speed v3 at which the resist liquid is moved to a side of the edge Wb of the wafer W.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: May 12, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Shinichi Hatakeyama, Yoshitomo Sato, Kazuyuki Tashiro, Naofumi Kishita
  • Patent number: 9029171
    Abstract: The present disclosure relates to a structure and method to create a self-repairing dielectric material for semiconductor device applications. A porous dielectric material is deposited on a substrate, and exposed with treating agent particles such that the treating agent particles diffuse into the dielectric material. A dense non-porous cap is formed above the dielectric material which encapsulates the treating agent particles within the dielectric material. The dielectric material is then subjected to a process which creates damage to the dielectric material. A chemical reaction is initiated between the treating agent particles and the damage, repairing the damage. A gradient concentration resulting from the consumption of treating agent particles by the chemical reaction promotes continuous diffusion the treating agent particles towards the damaged region of the dielectric material, continuously repairing the damage.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee, Tien-I Bao
  • Publication number: 20150118863
    Abstract: Provided herein are methods and apparatus for forming flowable dielectric films having low porosity. In some embodiments, the methods involve plasma post-treatments of flowable dielectric films. The treatments can involve exposing a flowable film to a plasma while the film is still in a flowable, reactive state but after deposition of new material has ceased.
    Type: Application
    Filed: October 21, 2014
    Publication date: April 30, 2015
    Inventors: Megha Rathod, Deenesh Padhi, Nerissa Draeger, Bart J. van Schravendijk, Kaihan Ashtiani
  • Publication number: 20150118862
    Abstract: Provided herein are methods and apparatus for improved flowable dielectric deposition on substrate surfaces. The methods involve improving nucleation and wetting on the substrate surface without forming a thick high wet etch rate interface layer. According to various embodiments, the methods may include single or multi-stage remote plasma treatments of a deposition surface. In some embodiments, a treatment may include exposure to both a reducing chemistry and a hydrogen-containing oxidizing chemistry. Apparatus for performing the methods are also provided.
    Type: Application
    Filed: October 21, 2014
    Publication date: April 30, 2015
    Inventors: Patrick Reilly, Harald te Nijenhuis, Nerissa Draeger, Bart J. van Schravendijk, Nicholas Muga Ndiege
  • Patent number: 9018106
    Abstract: A method of forming a material layer on a substrate is provided. The method is based on a combination of an overheating before deposition and a cooling of the reaction chamber during a second deposition stage. The second deposition stage follows a first deposition stage preferably carried out at a predetermined temperature. This combination makes it possible to compensate for the reactant gas depletion across wafer throughout the whole deposition process. The method can be conveniently used when growing a nitride layer to be used as a hard mask during shallow trench isolation (STI) region formation.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: April 28, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Fabian Koehler, Itasham Hussain, Bianca Antonioli-Trepte
  • Patent number: 9018108
    Abstract: Methods of forming a dielectric layer on a substrate are described, and may include introducing a first precursor into a remote plasma region fluidly coupled with a substrate processing region of a substrate processing chamber A plasma may be formed in the remote plasma region to produce plasma effluents. The plasma effluents may be directed into the substrate processing region. A silicon-containing precursor may be introduced into the substrate processing region, and the silicon-containing precursor may include at least one silicon-silicon bond. The plasma effluents and silicon-containing precursor may be reacted in the processing region to form a silicon-based dielectric layer that is initially flowable when formed on the substrate.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 28, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Sukwon Hong, Toan Tran, Abhijit Mallick, Jingmei Liang, Nitin K. Ingle
  • Patent number: 9018093
    Abstract: A method for forming a layer constituted by repeated stacked layers includes: forming a first layer and a second layer on a substrate under different deposition conditions to form a stacked layer, wherein the film stresses of the first and second layers are tensile or compressive and opposite to each other, and the wet etch rates of the first and second layers are at least 50 times different from each other; and repeating the above step to form a layer constituted by repeated stacked layers, wherein the deposition conditions for forming at least one stacked layer are different from those for forming another stacked layer.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: April 28, 2015
    Assignee: ASM IP Holding B.V.
    Inventors: Naoto Tsuji, Fumitaka Shoji
  • Publication number: 20150108618
    Abstract: A porous layer is described. The porous layer comprises a solidified sol-gel inorganic material having a distribution of nanometric voids, wherein at least some of nanometric voids are at least partially coated internally by carbon or a hydrophobic substance containing carbon.
    Type: Application
    Filed: May 7, 2013
    Publication date: April 23, 2015
    Inventors: Simon Litsyn, Gil Rosenman, Amir Handelman, Yakov Roizin
  • Patent number: 9012333
    Abstract: A method, in one embodiment, can include forming a tunnel oxide layer on a substrate. In addition, the method can include depositing via atomic layer deposition a first layer of silicon nitride over the tunnel oxide layer. Note that the first layer of silicon nitride includes a first silicon richness. The method can also include depositing via atomic layer deposition a second layer of silicon nitride over the first layer of silicon nitride. The second layer of silicon nitride includes a second silicon richness that is different than the first silicon richness.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: April 21, 2015
    Assignee: Spansion LLC
    Inventors: Yi Ma, Shenqing Fang, Robert Ogle