Abstract: A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design, wherein the first digital design and the second digital design are intended to have a same logical function. A plurality of testcase types are then created by constraining one or more internal signals, and one or more test scripts representing the plurality of testcase types are produced. The method also includes verifying the second digital design with a testing simulation program by comparing results of the test scripts from the operational model and the reference model.
Type:
Grant
Filed:
November 26, 2007
Date of Patent:
July 6, 2010
Assignee:
International Business Machines Corporation
Inventors:
Jason Raymond Baumgartner, Christian Jacobi, Viresh Paruthi, Kai Oliver Weber
Abstract: The invention disclosed herein provides methods and materials for observing the state of a sensor, for example those used by diabetic patients to monitor blood glucose levels. Typically a voltage such as a voltage pulse is applied to the sensor in order to solicit a current response from which for example, factors such as impedance values can be derived. Such values can then be used as indicators of a sensor's state, for example the state of sensor hydration, sensor noise, sensor offset, sensor drift or the like.
Type:
Application
Filed:
December 29, 2008
Publication date:
July 1, 2010
Applicant:
Medtronic MiniMed, Inc.
Inventors:
Bradley Chi Liang, Larry E. Tyler, Mohsen Askarinya, Charles Robert Gordon, Randal C. Schulhauser, Kenneth W. Cooper, Kris R. Holtzclaw, Brian T. Kannard, Rajiv Shah
Abstract: In a method to test a clinical and/or medical-technical system and a method for controlling medical-technical examination workflows in a clinical and/or medical-technical system, medical examination workflows in the appertaining system are simulated. For this purpose, a process workflow plan is selected from a number of process workflow plans dependent on an examination task, each of the process workflow plans including a number of linked process units with which system component of the system are respectively associated. Each process workflow plan also includes an input parameter set, an output parameter set and a transfer function that is dependent on the examination task and/or the associated system component. Respective output parameter values and/or performance data for the individual process units are then determined from a number of input parameter values for the appertaining process units on the basis of the transfer function.
Abstract: Systems and methods for performing data transfer rate throttling o improve the effective data transfer rate for SATA storage devices. The data transfer rate is diluted by inserting ALIGN primitives when data is sent. The receiving device simply discards the ALIGN primitives. Therefore, the receive data FIFO does not fill as quickly and fewer flow control sequences are needed for flow control to prevent the receive data FIFO from overflowing. An advantage of using the ALIGN primitives instead of conventional flow control is that the round-trip handshake latency is not incurred to disable and later enable data transfers.
Abstract: A tester for testing a semiconductor device is disclosed. The tester for testing the semiconductor device employs a data selector for converting a logical test pattern data transmitted from a pattern generator into a physical test pattern data and an expected data based on the logical test pattern data, thereby generating various timings based on a time delay instead of using a plurality of clocks to improve a test efficiency and reduce a manufacturing cost.
Abstract: In an aspect of the present invention, a microcomputer includes a CPU core section, and a plurality of external input terminals. A testing section selects a selection external input terminal from the plurality of external input terminals, detects an intermediate voltage of the selection external input terminal, and outputs an interrupt processing signal related to the detection of the intermediate voltage to the CPU core section.
Abstract: A testing apparatus tests a communication control apparatus, which performs given processing on input communication data and outputs the data. The testing apparatus includes an output unit which outputs data to the communication control apparatus, a generating unit which generates data to be output by the communication control apparatus after the apparatus normally processes data output to the apparatus, an input unit which inputs data output by the communication control apparatus, and an inspection unit which compares data generated by the generating unit with data input by the input unit to check if the communication control apparatus operates normally.
Abstract: The traveling wave excitation system phase shifter chassis method and device of the invention is compact, inexpensive, and versatile when compared to customary methods for generating traveling wave excitation signals that would require using an equivalent number of commercial function generators. The method and device of the invention produces up to 56 simultaneous sine waves that are phase shifted with respect to one another.
Type:
Grant
Filed:
January 7, 2004
Date of Patent:
June 1, 2010
Assignee:
The United States of America as represented by the Secretary of the Air Force
Inventors:
Keith W. Jones, Christophe Pierre, Steven L. Ceccio, John Judge, Steve Fuchs
Abstract: A probe card assembly, according to some embodiments of the invention, can comprise a tester interface configured to make electrical connections with a test controller, a plurality of electrically conductive probes disposed to contact terminals of an electronic device to be tested, and a plurality of electrically conductive data paths connecting the tester interface and the probes. At least one of the data paths can comprise an air bridge structure trace comprising an electrically conductive trace spaced away from an electrically conductive plate by a plurality of pylons.
Abstract: A heterogeneous device including multiple types of resources is provided to implement multiple logic functions. Logic functions are provided with multiple configuration options. In one example, an optimal set of configuration options along with a target device are selected using cost and resource availability information associated with multiple heterogeneous programmable chips and the configuration options provided with the logic blocks.
Abstract: A method of characterizing the frequency response of a frequency translation device over a wide IF bandwidth is based on a two-dimensional model to generate calibration data for a device at run-time. The model is a function of a center frequency and frequency offset for a plurality of center frequencies over a wide system bandwidth to produce a frequency response at each center frequency. The frequency responses at each center frequency are scaled and normalized relative to a reference frequency and stored.
Abstract: Various methods, carrier media, and systems for detecting defects on a specimen using a combination of bright field channel data and dark field channel data are provided. One computer-implemented method includes combining pixel-level data acquired for the specimen by a bright field channel and a dark field channel of an inspection system. The method also includes detecting defects on the specimen by applying a two-dimensional threshold to the combined data. The two-dimensional threshold is defined as a function of a threshold for the data acquired by the bright field channel and a threshold for the data acquired by the dark field channel.
Abstract: A technique for determining the number of constraints on, or topological dimension of, a set of input data produced by a nonlinear system, such as a pathological vocal or econometric system. The technique characterizes the tangent space about a predetermined base point by identifying a maximal set of non-redundant nonlinear fits to the data. It needs only a few data points and only assumes that the functional form of the true constraints is smooth. Each fit is equivalent to a set of contours, with the data lying along the zero-value contour. For each fit, the gradient at the base point in the uphill direction identifies the constraint direction. The number of linearly independent constraint directions provides the number of constraints near the base point. The remaining unconstrained directions define the tangent space, which has a dimensionality equal to the number of linearly independent unconstrained directions.
Type:
Grant
Filed:
October 16, 2006
Date of Patent:
May 4, 2010
Assignee:
Speech Technology and Applied Research Corporation
Abstract: The invention discloses a circuit testing apparatus for testing a device under test. The circuit testing apparatus includes a precision measurement unit, a signal transformation module, and a microprocessor. The precision measurement unit is coupled to the device under test for providing a testing signal and receiving a measurement signal generated according to the testing signal. The signal transformation module is coupled to the precision measurement unit for receiving the measurement signal and transforming the measurement signal to a signal measurement result according to a predetermined manner. The microprocessor is coupled to the precision measurement unit and the signal transformation module for examining the signal measurement result to determine a test result for the device under test.
Abstract: A method and system for testing a computer is presented. The temperature of the computer is controlled by one or more on-board fans inside the computer's enclosure. Voltages are controlled at the Voltage Regulator Module (VRM) level. A test program is then run under varying temperature and VRM voltages, and the results of the test program are logged. The present invention can be used either at the manufacturer's location or the customer's site, either under local or remote control.
Type:
Grant
Filed:
May 12, 2005
Date of Patent:
April 20, 2010
Assignee:
International Business Machines Corporation
Inventors:
Srinivas Cheemalapati, Jimmy Grant Foster, Sr., Timothy J. Schlude, Philip Louis Weinstein
Abstract: A program circuit activates a pass signal when a first program unit is programmed. The first program unit is programmed when a test of an internal circuit is passed. A mode setting circuit switches an operation mode to a normal operation mode or a test mode by external control. A state machine allows a partial circuit of the internal circuit to perform an unusual operation different from a normal operation when the pass signal is inactivated during the normal operation mode. By recognizing the unusual operation during the normal operation mode, it can be easily recognized that a semiconductor integrated circuit is bad. Since a failure can be recognized without shifting to the test mode, for example, a user who purchases the semiconductor integrated circuit can also easily recognize the failure.
Abstract: A method for forming an electrical connection with head gimbal assembly. At least a portion of an unmounted head gimbal assembly is placed on a surface. The unmounted head gimbal assembly includes a flexible portion, the flexible portion includes contact pads, and the surface includes electrical contacts and slots. A section of the flexible portion is pushed against the surface, and the contact pads are interconnected with the electrical contacts using a clamp assembly controlled by a computer. The clamp assembly includes a clamp with pins, and the interconnecting includes engaging the pins with the slots, rotating the clamp towards the surface, and clamping the contact pads against the electrical contacts.
Type:
Grant
Filed:
January 31, 2007
Date of Patent:
March 23, 2010
Assignee:
Seagate Technology LLC
Inventors:
Justin Lee Holwell, Steven Ivars Palks, Andrew Michael Blair, Brett Robert Herdendorf, Michael Steven Quam, Michael Jon Roe, Dale Allen Blomgren
Abstract: In an embodiment, an integrated circuit or chip is supplied to its intended application and a measurement quantity representing the state of one or a plurality of electrical connections in the chip is determined within the application environment of the chip and, if the measurement quantity determined does not correspond to predefined criteria, a corresponding signal is output.
Abstract: A testing system for bus parameters includes a wave displaying unit and a control module connected to the wave displaying unit. The control module includes a decode unit, a testing unit connected to the decode unit, and an output unit connected to the testing unit. The decode unit is connected to the wave displaying unit. The wave displaying unit is configured for receiving an electronic signal from a bus to be tested. The decode unit is configured for decoding the electronic signal to determine if the electronic signal is valid. The testing unit tests parameters of the bus. The output unit displays testing results for the parameters.
Type:
Application
Filed:
October 29, 2008
Publication date:
March 18, 2010
Applicant:
HON HAI PRECISION INDUSTRY CO., LTD.
Inventors:
WANG-DING SU, YUNG-CHENG HUNG, HSIEN-CHUAN LIANG, PO-KAI HUANG, MI-WEN TSAI, CHI-REN KUO
Abstract: A measurement system for testing a DUT includes a plurality of procedures for performing test functions, each procedure having a phase variable; a task queue where the procedures are entered in the task queue with a sign-up value of the phase variable; and a multiphase task executor that arranges the procedures in the queue in response to the sign-up value. The executor changes the phase variable to an execution value and executes the procedures in the task queue after the phase variable has the execution value.
Abstract: A test instrument network for testing a plurality of DUTs includes a plurality of communicating script processors, the script processors being adapted to execute computer code; and a plurality of measurement resources controllable by the script processors in response to executed computer code, the measurement resources being adapted to test the DUTs. Each script processor and measurement resource may be arbitrarily assigned by the controller to one of at least two groups, only one script processor being assigned to be a master script processor, any other script processor being a slave script processor and any group not including the master script processor being a remote group. The master script processor is exclusively authorized to initiate code execution on any script processor in a remote group. Any slave script processor is only able to initiate operation of measurement resources in it own group.
Abstract: Apparatus, systems, and methods for testing SAS cables by applying a signal to one end of a SAS cable, receiving the signal from another end of the SAS cable, and generating an output of information relating to the testing. The testing apparatus may test one or more configuration characteristic of the SAS cable, including, for example a crossover status, a polarity status of transmit (“TX”) wires, and a polarity status of receive (“RX”) wires.
Type:
Application
Filed:
September 2, 2008
Publication date:
March 4, 2010
Inventors:
Brian K. Einsweiler, Luke E. McKay, Steven F. Faulhaber
Abstract: A central test facility transmits wirelessly test data to a local test facility, which tests electronic devices using the test data. The local test facility transmits wirelessly response data generated by the electronic devices back to the central test facility, which analyzes the response data to determine which electronic devices passed the testing. The central test facility may provide the results of the testing to other entities, such as a design facility where the electronic devices were designed or a manufacturing facility where the electronic devices where manufactured. The central test facility may accept requests for test resources from any of a number of local test facilities, schedule test times corresponding to each test request, and at a scheduled test time, wirelessly transmits test data to a corresponding local test facility.
Abstract: Methods systems and computer readable media for testing operation of an instrument controlled by a system under test. Raw data, used by the system under test to calculate reduced data, is inputted to an independent data reduction engine. Independent reduced data is calculated using at least one independent algorithm independent of a corresponding algorithm used by the system under test to calculate the reduced data. Values of the reduced data are compared with corresponding values of the independent reduced data, and at least one of outputting a result of the comparing for use by a human user, and storing a result of the comparing in memory are performed.
Abstract: An integrated chemical, biological, metals, radiation, nuclear, explosives sensor system I-CBMRNE deployed on a common platform supports chemical, biological, metals, radiation, nuclear, explosives (CBMRNE) surveillance systems. The common platform provides a database for collected sensor and video data, spectral analysis for sensor data, pattern recognition systems, data analysis and communications. An I-CBMRNE sensor system provides modular sensor interfaces to enable integration of any commercial off the shelf or proprietary sensor, and provides for ease of integration for new sensor technologies as they emerge. An I-CBMRNE sensor system provides critical functions for sensor support enabling accurate calibrated data to be presented for analysis.
Abstract: In one embodiment, a method includes sending an indicator of an availability of a sample from a sample pool stored in a physical inventory. The sample being included in the sample pool based on an attribute of the sample satisfying a condition associated with the sample pool. An indicator that the sample has been selected from the sample pool for analysis at a first test site included in an array of test sites is received. A rule is retrieved from a rule database based on an experimental parameter value associated with the first test site. At least one of the experimental parameter value associated with the first test site or an experimental parameter value associated with a second test site is modified based on a condition within the rule being satisfied.
Type:
Application
Filed:
July 10, 2009
Publication date:
February 18, 2010
Inventors:
Todd M. Covey, Darwin A. Farrow, Barton J. Friedland, Helen Francis-Lang, Malcolm Francis-Lang, Justin W. Mccarthy, Norman B. Purvis, JR., Santosh K. Putta, David B. Rosen, David M. Soper, David C. Spellmeyer
Abstract: The present disclosure is directed to a method for determining dynamic test coverage for a product. The method may comprise: receiving a customer order, the customer order comprising at least one product configuration; receiving a rule set associated with the at least one product configuration; analyzing the rule set to determine a proxy part to add to the at least one product configuration; providing the proxy part an indicator; adding the proxy part to the at least one product configuration; iteratively comparing the product configuration to the rule set until the product configuration meets the rule set; providing a test associated with the at least one product configuration; receiving at least one signal from at least one indicator; and removing at least one proxy part from the at least one product configuration.
Type:
Application
Filed:
August 1, 2008
Publication date:
February 4, 2010
Applicant:
INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventors:
Steven C. Erickson, Fraser A. Syme, William Robert Taylor
Abstract: Disclosed is a system and method for testing a dual mode interface. The dual mode interface includes a first strobe circuit and a second strobe circuit configured to be inoperable during a first operational mode of the interface and operable during a second operational mode of the interface. The dual mode interface also includes a first data circuit and a second data circuit configured to be operable during the first operational mode and the second operational mode. The dual mode interface also includes a signal line connecting an output of the second strobe circuit with an input of the first strobe circuit and a switch element configured to activate said signal line in response to receipt of a test signal.
Type:
Grant
Filed:
May 4, 2006
Date of Patent:
February 2, 2010
Assignee:
Agere Systems, Inc.
Inventors:
Yasser Ahmed, Robert Joseph Kapuschinsky, Ashok Khandelwal, Samuel Khoo, Lane A. Smith
Abstract: Test substrates used to test semiconductor fabrication tools are reclaimed by reading from a database the process steps performed on each test substrate and selecting a reclamation process from a plurality of reclamation processes. The reclamation process can include crystal lattice defect or metallic contaminant reduction treatments for reclaiming each test substrate. Each test substrate is sorted and placed into a group of test substrates having a common defect or contaminant reduction treatment assigned to the test substrates of the group. Additional features are described and claimed.
Type:
Grant
Filed:
November 2, 2005
Date of Patent:
February 2, 2010
Assignee:
Applied Materials, Inc.
Inventors:
Krishna Vepa, Yashraj Bhatnagar, Ronald Rayandayan, Hong Wang
Abstract: Techniques for bisecting a symmetric, substantially transmissive two-port network (a THRU structure) through an optimization solution of the relevant equations defined by transmission matrix mathematics are described. Bisect de-embedding may be performed using a single substantially symmetric THRU structure, a first half of a first substantially symmetric THRU structure and a second half of a second substantially symmetric THRU structure, and by combining bisect de-embedding with conventionally known de-embedding techniques.
Type:
Grant
Filed:
September 9, 2005
Date of Patent:
January 5, 2010
Assignee:
Mayo Foundation for Medical Education and Research
Abstract: A method for testing multiple features of an electronic device sets a global timer and a series of feature test timers. The feature test timers are arranged in a sequence. The global timer is firstly activated. The feature test timers are then activated one by one according to the sequence and one or more features of the electronic device corresponding to each of the feature test timers are tested until the global timer times out.
Abstract: In a method for testing device descriptions for field devices of automation technology, a finite state machine is produced from a device description to serve as a basis for a test script. For testing the device description, the test script is executed, with data being sent to and received from the device description. In such case, it is tested whether desired values set in the test script agree with actual values delivered e.g. from the field device.
Abstract: Embodiments of the present invention provide a data group for each parameter that is classified into a first group and a second group, based on the performance of the products, a base point of a distribution of the data group is calculated, based on the distribution, and a distance range from the base point is decided. The number of data within this range belonging to the first group is counted and substituted for variable FX, the number of data belonging to the second group is counted and substituted for variable SX, the number of data outside this certain range belonging to the first group is counted and substituted for variable FY, and the number of data belonging to the second group is counted and substituted for variable SY. Moreover, a failure content ratio is calculated from variables FX, FY, SX and SY, and the yield impact is calculated.
Type:
Grant
Filed:
March 28, 2007
Date of Patent:
December 29, 2009
Assignee:
Hitachi Global Storage Technologies Netherlands B.V.
Abstract: A recording medium recording thereon a program for a test apparatus including test modules that test devices under test is provided. The program includes: a common function provision program which is executed on a controller for controlling the test apparatus and provides a function common to each type of the test modules; and a plug-in processing program which is executed on the controller and plugs-in an individual function provision program for providing a function appropriate for the type of each of the test modules.
Abstract: A debug system includes equipment to be debugged (onboard information equipment 10) which is controlled by a microcomputer 11; and a command return jig 20 which is connected to the equipment to be debugged via a communication interface unit 12, receives a specific command generated and output by the microcomputer 11 via the communication interface unit, and outputs the specific command by return to the equipment to be debugged, wherein the equipment to be debugged switches, when receiving the specific command from the command return jig, the microcomputer to set it in an operation environment the microcomputer does not use normally.
Abstract: Disclosed is a multi-drive adaptor that includes at least two disk drive ports, a connector, and a communication path. The connector is configured to receive at least one disk drive command transmitted according to a serial protocol from a serial controller. The communication path connects the at least two disk drive ports to the connector and is configured to communicate the at least one disk drive command received at the connector to each of the at least two ports. In some embodiments the connector includes a parallel connector, and the communication path includes serial-to-parallel bridges, each serial-to-parallel bridge coupled to the parallel connector and further coupled to a respective one of the at least two ports. In some embodiments the serial controller is a SATA controller. In some embodiments the connector is a parallel ATA (PATA) connector. In some embodiments the communication path includes a port multiplier.
Abstract: During a total temporal interval a plurality of characteristic values of the technical system are determined. The total temporal interval is divided into a plurality of partial intervals, each partial interval being between a partial interval starting point and a partial interval end point in the total interval. According to said method, for each partial interval, at least one parameter of a pre-determined predictive model is adapted to the characteristic values determined in the partial interval in such a way as to obtain a partial adaptation with which a partial interval and the end point of the partial interval are associated. Respectively one modification measure is determined for the partial adaptations in such a way as to indicate the modifications of the parameters of the respective partial adaptation in relation to the parameters of at least one adjacent partial adaptation.
Type:
Grant
Filed:
May 4, 2005
Date of Patent:
December 8, 2009
Assignee:
Siemens Aktiengesellschaft
Inventors:
Veronika Dunkel, Benedikte Elbel, Michael Greiner, David Meintrup
Abstract: An embedded device testing system for comparing actual device under test input/output vector pairs with modelled device under test input/output vector pairs, wherein actual device under test output vectors are sampled in accordance with a predefined timing reference.
Type:
Grant
Filed:
March 4, 2005
Date of Patent:
November 24, 2009
Assignee:
VFS Technologies Limited
Inventors:
Hani Achkar, Robert Douglas Nedelkovski
Abstract: The method comprises generating an acoustical volume velocity Q in the listening position, measuring a response quantity p, such as sound or vibration, at a suspected source position resulting from the volume velocity Q, and determining the acoustical transfer impedance Zt as the response quantity p divided by the acoustical volume velocity Q, Zt=p/Q. According to the invention the acoustical volume velocity Q is generated using a simulator (10) simulating acoustic properties of at least a head of a human being, the simulator comprising a simulated human ear (14, 15) with an orifice in the simulated head and a sound source (30) for outputting the acoustical volume velocity Q through the orifice. The output volume velocity Q from the orifice of an ear is estimated from measurements with two microphones inside the corresponding ear canal.
Type:
Grant
Filed:
April 14, 2004
Date of Patent:
November 10, 2009
Assignee:
Bruel & Kjaer Sound & Measurement A/S
Inventors:
Klaus Geiger, Christian Glandier, Rolf Helber
Abstract: A high-definition multimedia interface circuit uses a high-definition multimedia interface encoder to produce a plurality of channels of data. An output circuit, connected to the high-definition multimedia interface encoder, produces a plurality of channels of high frequency data from the data produced by the high-definition multimedia interface encoder. A multiplexer selects a channel for sampling, and a capacitive coupler capacitively couples the multiplexer to a sampling circuit. The sampling circuit produces sampled data corresponding to the high frequency data having a clock rate less than a clock rate of the high frequency data. A test circuit compares the sampled data with the data produced by the high-definition multimedia interface encoder.
Type:
Grant
Filed:
April 12, 2006
Date of Patent:
November 10, 2009
Assignee:
Analog Devices, Inc.
Inventors:
Barry L. Stakely, Rodney D. Miller, Jingang Yi
Abstract: The apparatus for analyzing a delay defect of the present invention obtains the RC of the maximal incidence among region codes (RCs) to which check circuits detecting errors caused with gradual increase in the frequency of an operational clock pulse fed to an integrated circuit belongs. The apparatus obtains information on latch in which an error is caused with the RC of the maximal incidence, with reference to a mapping table that describes the mapping relationship between an RC and a latch. The apparatus extracts a circuit portion in which an error can be captured with the region code of the maximal incidence by exhaustively tracing back circuit portions connected with each obtained latch, from the latch to the latch described in the mapping table. The apparatus gives delay defects to the input and the output pin of each of logic elements included in the extracted circuit portion, generates test patterns for detecting the given delay defects, and performs delay tests.
Abstract: A master testing control system includes at least one remote computer with one or more communications lines for communicating over a communications network and a plurality of remote sensors, a two way real-time digital video system, a two-way real-time digital audio system. A set of instructions is on each remote computer for sending and receiving data over one or more data lines and for remote display. A set of instructions is on each remote computer for displaying data. At least one local computer is located geographically distant from the remote computer and able to monitor and control the display, storage, and transmission of data acquired by the remote computer. The remote computer collects data from the plurality of sensors and transmits this data to the local computer, under the control of the local computer, for permanent recording.
Abstract: A method of the present invention includes: inputting a state transition diagram that represents first transitions between a plurality of states; inputting a mapping function that maps a given state to a value within a certain range; mapping each of the states with the mapping function to obtain mapping values, and perform grouping of the states into a plurality of groups based on the mapping values; for each of pairs of two groups obtained by combining two of the groups, setting a second transition from one group of the two groups to the other group when there is at least one first transition between therein; generating a representative transition path which is a sequence of the second transitions by tracing sequentially the second transitions; converting the representative transition path to a transition path in the state transition diagram; outputting the transition path as the test case.
Abstract: Analyzers are described that includes a mode selector for selecting one measurement mode from said plurality of measurement modes; a display for displaying a screen; and a display controller for displaying on said screen a picture representing contents of the measurement mode selected by said mode selector.
Abstract: In a method of testing a device under test (DUT) using a test device adapted to provide a connection to a central controller, a test procedure activation signal is supplied from the central controller to the test device. A test procedure for testing the DUT is performed on the basis of test procedure data, upon receipt of the test procedure activation signal. The test procedure is adjustable upon receipt of a feedback signal from the DUT. The test procedure is adjusted by 1) receiving a feedback signal from the DUT, 2) determining from the feedback signal properties of a physical connection between the test device and the DUT, and 3) adjusting the test procedure to modify the test signal and compensate for the properties of the physical connection between the test device and the DUT.
Abstract: In an arrangement comprising a supporting structure and a reproduction, arranged inside the supporting structure, of an aircraft passenger cabin on a 1:1 scale for receiving components of cabin systems, the invention consists in that the supporting structure is formed by a structure reproduction, composed of standardised elements, for receiving components of the cabin system and the cabin fittings and comprises standardised supports and connections in such a way that these components can be tested under operating conditions and at least one movable test module is provided which comprises multifunctional test rigs for operating and testing the cabin systems.
Abstract: A system for validating two-way continuity of a customer premises equipment (CPE) unit in a hybrid fiber coax (HFC) cable network. A two-way client uses a two-way query interface to acquire information indicative of the two-way operational status of a subscriber CPE units from a two-way validation server and to display the information graphically.
Abstract: A method, apparatus, and a computer program product for providing web service testing are provided. The apparatus may include a processor that is configured to provide a user interface for a testing tool accessible in a distributed network architecture. The processor may also be configured to receive selections of an application(s) to be tested that is accessible in a distributed network architecture, a function(s) that is associated with the selected application and a method(s) that is associated with the selected function(s). Additionally, the processor may be configured to receive selections of a test case(s) that is associated with the selected method(s). Moreover, the processor may be configured to automatically conduct the selected test case(s).
Type:
Application
Filed:
March 14, 2008
Publication date:
September 17, 2009
Applicant:
Verizon Data Services, Inc.
Inventors:
Amish Gandhi, Valeriy Elbert, Paul Perry, Gregory Wang
Abstract: A system and method for semiconductor CP (circuit probe) test management. A control request message is received from a client computer, directing alignment of a probe unit or a wafer in a prober, attachment of a probe pin of the probe unit on a specific area of the wafer, and subsequent execution of CP testing. At least one control command corresponding to the control request message is issued to direct the prober for alignment of the probe unit or the wafer, attachment of the probe pin of the probe unit on the specific area of the wafer, and subsequent execution of CP testing.
Abstract: A parametric parameter is selected, which has an upper specification limit and a lower specification limit. A storage percentile is determined. The storage percentile is equal to a product yield percentage if the number of the set of measurements greater than the upper specification limit exceeds the number of the set of measurements lower than the lower specification limit, and is equal to the product yield percentage subtracted from one hundred percent if the number of the set of measurements less than the lower specification limit exceeds the number of the set of measurements greater than the upper specification limit. A measurement closest to the storage percentile is stored.