Abstract: Fast Hartley Transforms in a radix-2 block transform method enables true split and merge transform processing of equal sized data halves for enabling recursive merges and splits in Hartley transform domain without data degradation. Input data in the time domain or spatial domain during either the split and merge radix-2 forward Hartley transform processing is firstly transform processed followed by combinational processing. Whole transformed data is split using combinational processing into transformed data halves in the Hartley transform domain as a true split. The transformed halves are merged using combinational processing into whole merged transformed data in the Hartley transform domain. Time or spatial domain input data can be transformed into the Hartley transform domain in the form of split halves or merged whole. The split halves can be merged by the merge process combinational processing and the merged whole can be split by the split process combinational processing.

Abstract: A register file structure efficiently handles matrix and image processing. The register file contains an array of data elements and has modes for accessing of multiple data values that are aligned horizontally or vertically in a data array and for accessing data having different widths for each data value. The different modes allow manipulation of a transposed array without requiring a transpose operation and permit fast horizontal or vertical filtering with parallel access and multiplications of horizontally or vertically aligned data elements.

Abstract: Discrete Karhunen-Loeve Transforms in a radix-2 block transform method enables true split and merge transform processing of equal sized data halves in the KLT domain for enabling recursive merges and splits in the KLT domain without data degradation. Input data in the time domain or spatial domain during either the split and merge radix-2 forward transform processing is firstly transform processed followed by combinational processing. Whole transformed data is split using combinational processing into transformed halves in the transform domain as a true split. Transformed halves are merged using combinational processing into whole merged transformed data in the transform domain. Time or spatial domain input data can be transformed into the transform domain in the form of split halves or merged whole. The split halves are merged by the merge process combinational processing and the merged whole are split by the split process combinational processing.

Abstract: Discrete Sine Transforms in a radix-2 block transform method enables true split and merge transform processing of equal sized data halves in the DST transform domain for enabling recursive merges and splits in DST transform domain without data degradation. Input data in the time domain or spatial domain during either the split and merge radix-2 forward transform processing is firstly transform processed followed by combinational processing. Whole transformed data is split using combinational processing into transformed data halves in the transform domain as a true split. The transformed halves are merged using combinational processing into whole merged transformed data in the transform domain. Time or spatial domain input data can be transformed into the transform domain in the form of split halves or merged whole. The split halves are merged by the merge process combinational processing and the merged whole are split by the split process combinational processing.

Abstract: A digital and a multiplication method are described, which lead to an efficient architecture for a hardware implementation of digital FIR and IIR filters into FPGAs. The multiplications of input sample data and delayed sample data with filter coefficients are performed by addressing look-up tables in which corresponding multiplication results are prestored. The size of the look-up tables is reduced by storing only those multiplication results which cannot be obtained by a shifting operation performed on the other pre-stored multiplication results, the input sample data, or the delayed sample data. Thereby, the size of the look-up tables can be compressed significantly such that an implementation of large digital filters into FPGAs is possible.

Abstract: A method and apparatus to reduce the amount of required memory and instruction cycles when implementing Fast Fourier Transforms (FFTs) on a computer system is described. The invention optimizes FFT software using in-place bit reversal (IPBR) implemented on a processor capable of bit reversed incrementation. Alternative embodiments implement the invention for out of place bit reversal (OOPBR) and on processors that do not support special instructions for bit reversed incrementation. The invention only generates unique bit-reversed address pairs and avoids generation of self-reversed addresses. To optimize the invention for in place bit reversal, every non-self bit reversed address in the input array is generated only once, while making simple, computationally efficient increments away from the previous pair of bit reversed addresses. The address pair generator can independently advance only one address in each address pair, and bit reversal of one address uniquely defines the other address.

Abstract: Improved transposition of a matrix in a computer system may be accomplished while utilizing at most a single permutation vector. This greatly improves the speed and parallelability of the transpose operation. For a standard rectangular matrix having M rows and N columns and a size M×N, first n and q are determined, wherein N=n*q, and wherein M×q represents a block size and wherein N is evenly divisible by p. Then, the matrix is partitioned into n columns of size M×q. Then for each column n, elements are sequentially read within the column row-wise and sequentially written into a cache, then sequentially read from the cache and sequentially written row-wise back into the matrix in a memory in a column of size q×M. A permutation vector may then be applied to the matrix to arrive at the transpose. This method may be modified for special cases, such as square matrices, to further improve efficiency.

Abstract: An Hadamard transform coding circuit changes a rounding method for each Hadamard transform block to prevent a rounding operation from providing an error biased in one direction, as seen in a picture in its entirety, for data compression and rounding. More specifically, after Hadamard transform there exist decimal parts 0.0, 0.25, 0.5 and 0.75, and if a numerical value is simply rounded off a probability would be increased that the numerical value is biased to increase in absolute value. Accordingly for 0.5 a rounding operation to provide an integer switches for each block. Thus a motion image decoding apparatus can be provided to reduce error accumulation and suppress flickering, color variation and other similar noticeable degradations.

Abstract: In a system having a plurality of processors 1 to M and each processor has corresponding output registers 1 to N an apparatus and method to transfer is claimed. The data comprises a current group of data and a next group of data. Each group of data comprises a plurality of portions of data. The current group of data from each processor 1 to M is transferred to its corresponding output register 1 to N. Each processor then receives and processes the next group of data. Simultaneously, the portion of data from output register N to output register N-1 is transferred. Similarly, each portion of data from output register N-1 is transferred to output register N-2, and so on. The portion of data from register 1 is transferred to a frame buffer.

Abstract: In one embodiment, a Walsh-Hadamard decoder can have a hardware efficient Fast Hadamard Transform (“FHT”) engine. In one embodiment, the FHT engine can include an input to receive an input sequence to be decoded into a Walsh-Hadamard codeword. The FHT engine can further include a controller to correlate the received input sequence with a plurality of Walsh-Hadamard codewords using two add/subtract modules. In one embodiment, the two add/subtract modules operate in parallel.

Abstract: A method and apparatus for performing a radix-4 fast Hadamard transform (FHT) with reduced complexity and for directly determining the maximum output of a fast Hadamard transform using either a radix-4 transform or radix-2 transform without actually generating the outputs. The radix-4 fast Hadamard transform is implemented using only seven operations. To find the maximum value of the output of a fast Hadamard transform and its corresponding index, the N-1 stages of a conventional N stage fast Hadamard transform are computed while a find-maximum stage is inserted in place of the Nth stage. The invention also provides a methodology for constructing fast Hadamard transforms of the form H2N using radix-4 FHTs and permuting the results to achieve the correct outputs.

Abstract: A system and method preprocesses data, in a computer system where forecasting of computing resources is performed based on past and present observations of measurements related to the resources. The preprocessing includes decomposing the past and present observations into a smooth time sequence, a jump time sequence, a noise time sequence and a spike time sequence. The method (and system) includes detecting the spikes in a signal representing the measurements, detecting the jumps in the signal, removing spikes and jumps from the signal, and removing the noise from the signal, to obtain a smooth version of the signal.

Abstract: A method for indexing a plurality of ordered elements stored in bit-reversed order in a first and a second memory space, the first memory space indexed by a first memory index denoting memory positions in the first memory space, the second memory space indexed by a second memory index denoting memory positions in the second memory space, the logical position of the elements within the ordered elements indexed by an element index, the method including bit-reversing the element index of a selected element, locating the selected element as being in the first memory space where the MSB of the bit-reversed index equals 0 and the second memory space where the MSB of the bit-reversed index equals 1, and locating the position of the selected element within the MSB-located memory space at the memory index of the MSB-located memory space that corresponds to the non-MSB bits of the bit-reversed index.

Abstract: A microprocessor structure for performing a discrete wavelet transform operation, said discrete wavelet transform operation comprising decomposition of an input signal comprising a vector of r×km input samples, r, k and m being non-zero positive integers, over a specified number of decomposition levels j, where j is an integer in the range 1 to J, starting from a first decomposition level and progressing to a final decomposition level, said microprocessor structure having a number of processing stages, each of said number of processing stages corresponding to a decomposition level j of the discrete wavelet transform operation and being implemented by a number of basic processing elements, the number of basic processing elements implemented in each of said processing stages decreasing by a factor of k from a decomposition level j to a decomposition level j+1.

Abstract: A method is disclosed for performing a discrete cosine transform (DCT) using a microprocessor having an instruction set that includes SIMD floating point instructions. In one embodiment, the method includes: (1) receiving a block of integer data having C columns and R rows; and (2) for each row, (a) loading the row data into registers; (b) converting the row data into floating point form so that the registers each hold two floating point row data values; and (c) using SIMD floating point instructions to perform weighted-rotation operations on the values in the registers. Suitable SIMD floating point instructions include the pswap, pfmul, and pfpnacc instructions. For the row-DCT, the data values are preferably ordered in the registers so as to permit the use of these instructions. For the column-DCT, two columns are preferably processed in parallel using SIMD instructions to improve computational efficiency.

Abstract: A method for finding optimal filter coefficients for a filter given an input data sequence and an objective function is disclosed. The method includes selecting a wavelet basis having k parameters and minimizes the k parameters according to the predetermined objective function. The wavelet basis is reparameterized into k/2 rotation parameters and factorized into a product of rotation and delay matrices. The k/2 rotation parameters are provided for the rotation matrices and a data transform matrix is computed based on the product of the rotation and delay matrices. The input data sequence is converted into transformed data by applying the data transform matrix to the input data. The Jacobian of the data transform matrix and the input data sequence is determined and multiplied by the gradient vector with respect to the transformed data of the objective function.

Abstract: A transformation engine includes an address generator; a butterfly unit coupled to the address generator; a twiddle LUT coupled to the address generator; and a multiplier having a first input coupled to the butterfly unit and a second input coupled to the twiddle LUT.

Abstract: A data transformation algorithm is selectively applied to each data vector as it enters the pipelined structure. In a selection step, the algorithm compares the bit value of the new data vector with the corresponding bit values of the preceding data vector, and sums the number of logic transitions. The transformation algorithm is applied to the new data vector only if it would reduce the resulting number of transitions, otherwise the data vector is propagated unmodified. Bit inversion is a data transformation algorithm according to the present invention that provides up to a 50% reduction in the number of logic transitions.

Abstract: A method is disclosed for performing an inverse discrete cosine transform (IDCT) using a microprocessor having an instruction set that includes SIMD floating-point instructions. In one embodiment, the method includes: (1) receiving a block of integer data having C columns and R rows; and (2) for each row, (a) loading the row data into registers; (b) converting the row data into floating-point form so that the registers each hold two floating-point row data values; and (c) using SIMD floating-point instructions to perform weighted-rotation operations on the values in the registers. Suitable SIMD floating-point instructions include the pswap, pfmul, and pfpnacc instructions. For the row-IDCT, the data values are preferably ordered in the registers so as to permit the use of these instructions. For the column-IDCT, two columns are preferably processed concurrently using SIMD instructions to improve computational efficiency.

Abstract: The invention comprises a method for calculating an orthogonal discrete transform on the basis of the DIT method in prescribed intermediate steps with the following steps: the data are read from a memory organized on page-for-page basis; the intermediate step prescribed by the transform is carried out; the resulting data are stored in a buffer memory; and the resulting data are written page-for-page from the buffer memory to the memory organized on a page-for-page basis. Suitable discrete orthogonal transforms are FFT, IFFT, DCT, IDCT and transforms of similar structure.

Abstract: The present invention relates to the methods of estimation and recovering of general affine geometrical transformations which were applied to data, extensible to any other defined class of geometrical transformations, according to the preamble of the dependent claims. The parameters of the undergone deformation are robustly estimated based on maxima given by a parametric transform such as Hough transform or Radon transform of some embedded information with periodical or any other known regular structure. The main applications of this invention are robust digital still image/video watermarking, document authentication, and detection of periodical or hidden patterns. In the case of periodical watermarks, the watermark can also be predistorted before embedding based on a key to defeat block-by-block removal attack.

Abstract: The invention relates to a method of analysis for human locomotion irregularities. In such method, acceleration measurements obtained during one or more motions controlled at a stabilized gait of a human being are used, through accelerometers measuring on a time base accelerations according to at least one direction, and any locomotion irregularities are analyzed from reference measurements. Such measured accelerations are submitted to at least one wavelet transformation and the resulting wavelet transform is used to detect and/or analyze the irregularities.

Abstract: Linear transformations are carried out on a matrix that represents information such as an image or a communication. In an aspect, the matrix is processed to remove duplicate information. The duplicate information can be duplicate rows, or zero rows. This matrix is then transformed into a modifed matrix, indicating duplicate information is removed to produce a modified matrix.

Abstract: A method and an apparatus capable of realizing at a high speed an elliptic curve cryptography in a finite field of characteristic 2, in which the elliptic curve is given by y2+xy=x3+ax2+b (b?0) and an elliptic curve cryptography method which can protect private key information against leaking from deviation information of processing time to thereby defend a cipher text against a timing attack and a differential power analysis attack are provided. To this end, an arithmetic process for executing scalar multiplication arithmetic d(x, y) a constant number of times per bit of the private key d is adopted. Further, for the scalar multiplication d(x, y), a random number k is generated upon transformation of the affine coordinates (x, y) to the projective coordinates for thereby effectuating the transformation (x, y)?[kx, ky, k] or alternatively (x, y)?[k2x, k3y, k]. Thus, object for the arithmetic is varied by the random number (k).

Abstract: Methods and apparatuses for transposing a matrix using a vector look up unit. In one aspect of the invention, a method for matrix transposition includes: rotating in a vector register a first row of a matrix to generate a first row, of elements; writing simultaneously into a plurality of look up units the first row of elements indexed by a first row of indices in a vector register; looking up simultaneously from the plurality of look up units a second row of elements indexed by a second row of indices in a vector register; and rotating in a vector register the second row of elements to generate a third row of elements.

Abstract: A method of scaling image and video processing computational complexity according to the maximum available quantities of computational includes performing a plurality of data multiplications which processes digital image and video data, the performance of each data multiplication requiring a predetermined quantity of computational resource units; selecting one of the data multiplications; selecting a shift/add-, a shift/subtract or a shift-operation using a data independent value associated with the selected multiplication that requires a quantity of computational resource units which is less than the predetermined quantity of computational resource units required for performing the selected multiplication; and performing the selected multiplication with the selected operation. Also, a decoder which scales video and still image decoding computational complexity with available computational resources according to the above method.

Abstract: A system and method for parallel computation of Discrete Sine and Cosine Transforms. The computing system includes a plurality of interconnected processors and corresponding local memories. An input signal x is received, partitioned into P local vectors xi, and distributed to the local memories. The preprocessors may calculate a set of coefficients for use in computing the transform. The processors perform a preprocess in parallel on the input signal x to generate an intermediate vector y. The processors then perform a Fast Fourier Transform in parallel on the intermediate vector y, generating a second intermediate vector a. Finally, the processors perform a post-process on the second intermediate vector a, generating a result vector v, the Discrete Transform of signal x. In one embodiment, the method generates the Discrete Sine Transform of the input signal x. In another embodiment, the method generates the Discrete Cosine Transform of the input signal x.

Abstract: A compressed data buffer 21 maintains an image data loaded from a storage device 1, and a decoding section 22 conducts variable length decoding, inverse quantization and inverse discrete cosine transform, and a pixel data shifting section 23 shifts each value of pixel data to right by 1 bit, and a motion compensating section 24 applies motion compensation processing to the data shifted to right by 1 bit, and the frame data buffer 25 stores an image data to be displayed, and a reference data calculating section 24a of the motion compensating section 24 obtains a reference data from a reference buffer based on a motion vector, and a reference data adding section 24b adds the reference data to a data to which decoding processing has been applied, and a reference data storing section 24c leaves in the reference buffer the data to which the motion compensation processing has been applied.

Abstract: A method including decimating a signal x using a filter f to obtain a decimated signal y, interpolating the decimated signal y to obtain a reconstructed signal z, determining a refinement factor s by decimating z and comparing decimated z to the decimated signal y, and determining an improved reconstructed signal r by using the refinement factor s, the filter f, and the reconstructed signal z is disclosed.

Abstract: Apparatus, methods, and computer program products are provided for generating a second set of equations requiring reduced numbers of computations from a first set of general equations, wherein each general equation defines coefficients in terms of a set of samples and a plurality of functions having respective values. A first set of tokens is initially assigned to the plurality of functions such that every value of the functions that has a different magnitude is assigned a different token, thereby permitting each general equation to be defined by the set of samples and their associated tokens. Each general equation is then evaluated and the samples having the same associated token are grouped together. A second set of tokens is then assigned to represent a plurality of unique combinations of the samples. The second set of equations is then generated based at least on the first and second sets of tokens.

Abstract: A data processing apparatus having data cache performs an N-point radix-R Fast Fourier Transform. If the data set is smaller than the data cache, the data processing apparatus performs the Fast Fourier Transform in logRN stages on all the data set in one pass. If the data set is larger than the data cache but smaller than R times the data cache, the data processing apparatus performs a first stage radix-R butterfly computation on all the input data producing R independent intermediate data sets. The data processing apparatus then successively performs second and all subsequent stage butterfly computations on each independent intermediate data set in turn producing corresponding output data. During the first stage radix-R butterfly computations, each of R continuous sets are separated in memory by memory locations equal to the size of a cache line.

Abstract: This invention provides a universal interface system that is capable of launching software applications across operating system platforms. For example, the universal interface system allows a computer using a Microsoft Windows operating system to launch and execute software applications that were written for a UNIX operating system environment. Conversely, the universal interface system allows software applications written for a Linux operating system environment to be launched and operating in a Sun Solaris operating system environment. The universal interface system may interface between the BIOS and the operating system or operate on top of the operating system.

Abstract: Device for processing digital data and, more particularly, for reading out the maximum or minimum value of data belonging to a set of 2n codes in which a relation of order is established and in which each of said data has a rank R comprised between 0 and 2n−1.

Abstract: A method of implementing a two-dimensional Inverse Discrete Cosine Transform on a block of input data. The method includes 1) generating a performance array for the columns of the input data; 2) performing a column-wise IDCT upon the input data, the IDCT performed in accordance with cases given for each of the columns by the performance array; (3) generating a row performance offset for rows of the input data; and 4) performing a row-wise IDCT upon the result data from the performing of the column-wise IDCT.

Abstract: In order to change and, in particular, reduce the crest factor in a signal which is used, in particular, for data transmission by the method of discrete multitone modulation, it is known to store the signal in the form of individual sampling values in a signal vector (y), as a function of which a correction vector (&Dgr;y) is calculated for superimposition of the signal vector (y). The correction vector (&Dgr;y) is calculated here as a function of a maximum element of the signal vector (y) and reduces this maximum value in a targeted manner. In order to be able to reduce new maximum values of the signal vector (y) occurring after the reduction of a first maximum value, according to the invention the correction vector is windowed, so it acts with differing strength on different sections of the signal vector (y) or in that with the windowed correction vector (&Dgr;y) individual maximum values in the signal vector (y) can be reduced in a targeted manner.

Abstract: A digital signal processor DSP for bit-reversal of a large data array of a size has a direct memory access (DMA) controller for performing in-place bit reversal routines on an external memory during a first stage, and a central processing unit (CPU) for swapping small sub-arrays on internal memory in a second stage. The two stage method according to the invention importantly reduces the real-time implementation for sorting large size data arrays on uni-processor DSP platforms, by extensively using the external memory and avoiding a random access to the internal memory. As well, the invention provides for improved dense integration and reduced costs when used in dense wavelength division multiplexing (DWDM) systems.

Abstract: An architecture component for use in performing a wavelet transform of a sampled signal, and an architecture including such components are disclosed. The architecture component includes a multiplier, and a multiplexor to multiplex a number n of filter coefficients onto the multiplier. The multiplier processes n consecutive samples with consecutive coefficients, successive multiplier outputs being stored for subsequent processing to generate an output of the filter after every n samples. The wavelet transform may be a discrete wavelet transform or a wavelet packet decomposition. The architecture component may be configured to multiplex two or more coefficients onto a multiplier. Embodiments are disclosed in which the components are derived from a parameterized description in a hardware description language.

Abstract: Various components of the present invention are collectively designated as Analysis of Variables Through Analog Representation (AVATAR). It is a method, processes, and apparatus for measurement and analysis of variables of different type and origin. AVATAR offers an analog solution to those problems of the analysis of variables which are normally handled by digital means. The invention allows (a) the improved perception of the measurements through geometrical analogies, (b) effective solutions of the existing computational problems of the order statistic methods, and (c) extended applicability of these methods to analysis of variables.

Abstract: Fast transforms that use multiple scaled terms is disclosed. The discrete transforms are split into sub-transforms that are independently calculated using multiple scaling terms on the transform constants. The effect of the scaling for the transform coefficients may optionally be handled by appropriately scaling the quantization values or any comparison values. Further, optimal representations of the scaled terms for binary arithmetic are found. The resulting calculations result in fast transform calculations, decreased software execution times and reduced hardware requirements for many linear transforms used in signal and image processing application, e.g., the DCT, DFT and DWT.

Abstract: A system and method for parallel computation of the unordered Hadamard transform. The computing system includes a plurality of interconnected processors and corresponding local memories. An input signal x is received, partitioned into M1 sub-vectors xi of length M2, and distributed to the local memories. Each processor computer a Hadamard transform (order M2) on the sub-vectors in its local memory (in parallel), generating M1 result sub-vectors ti of length M2, which compose a vector t of length M1×M2. A stride permutation (stride M2) is performed on t generating vector u. Each processor computes a Hadamard transform (order M1) on the sub-vectors uj in its local memory (in parallel), generating M1 result sub-vectors vj of length M2, which compose a vector v of length M2×M1. A stride permutation is performed on v (stride M1) generating result vector w, which is the Hadamard transform of the input signal x.

Abstract: A method for advancing pointers in a memory including a sequence of N data points of a stage M of a Fast Fourier Transform (FFT) whose first stage is stage 0, the N data points including N/2 a data points and N/2 B data points, the N data points are stored in the memory in 2M groupings of a data points, each of the groupings having 2(Log2N)−1−M data points, and each of the groupings is followed by a grouping of 2(Log2N)−1−M B data points, the method including the steps of a) setting a pointer index Ap equal to the binary value of the data point memory index corresponding to the first A data point in the memory, b) setting a pointer index Bp equal to the binary value of the data point memory index corresponding to the first B data point in the memory, c) setting a first binary bit mask value R1 equal to 2(Log2N)−1−M+1, d) setting a second binary bit mask value R2 equal to 2(Log2N)−1−M, e) advancing the Bp pointer index to the data point memory index correspo

Abstract: A digital data system (100) provides 1-D, 2-D and 3-D capability and multi-band channel capability. Improved filter banks are created by generating a filter bank having an analysis portion and synthesis portion and obtaining wavelet coefficients (302) for each portion. The wavelet coefficients are expressed in a format capable of canonical signed digit (CSD) representation, such as integers (302). The canonical signed digit (CSD) representation is controlled by a value, N, selected to control resolution of the CSD coding. Optimized CSD-coded wavelet coefficients are used as filters for data signals (318).

Abstract: The invention describes a digital signal processor to execute at least one dedicated operation of a dedicated system such as an digital front-end of any digital subscriber line system.

Abstract: The present invention relates to a discrete transform calculation device (FFTP). The device has control means (CNTRL) which configure first and second memories (RAM1 and RAM2) according to the number of transforms used during a first processing. The device applies in particular to a demodulator which allows management of several Fourier transforms in parallel.

Abstract: A sliding weight Fourier transformer for the transformation of rows of numbers, in the process of which a new Fourier transformation is performed by making a correction to a previously determined Fourier transformation. In order to obtain a weighted Fourier transformation, the Fourier transformation is split-up in three transformations that can also be corrected and that together make up the weighted Fourier transformation.

Abstract: A new method for characterising the amplitude and phase distributions of the light propagating through arrayed-waveguide gratings is presented. The new method is based on the IFT. A very good agreement of the results obtained from the IFT method in comparison with OLC method has been achieved. The new method has been applied to an AWG with a small &Dgr;L of 22 &mgr;m where the other methods fail. The precision of this measurement is demonstrated by a good agreement between the transmittance obtained from direct measurement and from calculation using the amplitude and phase distributions. Finally we want to point out, that although the results are based on a FTS measurement, the method can be applied to any experimental technique that provides a measurement of the complex transmittance of the AWG.

Abstract: An orthogonal transform processor which can be implemented in simple hardware. A data reception unit accepts a pair of source data values at intervals of T. For each given pair of source data values, an adder/subtractor performs addition and subtraction at intervals of T/n, where n is an integer representing the order of the orthogonal transform algorithm being implemented. The resultant data values are stored in some predetermined storage locations defined in a storage unit. A feedback unit reads out such stored data values from the storage unit and feeds them back to the adder/subtractor. When the intended operation stages are finished, a data output unit reads out the data from the storage unit and sends them out as the final result values.

Abstract: A fast Hadamard transform device is provided which prevent from increasing of circuit scale and shorten a developing TAT even if the number of bits to be operated. The device includes n of shift register units and n/2 of butterfly computation units. Input data are entered to the shift register units in response to a signal and data stored in the shift register units are supplied as quantized data by providing a signal for each “log2n*(p+log2n)” clocks.

Abstract: A discrete cosine transformation apparatus comprises a transposition section that transposes input picture signal of N×N pixels in every N pixels between the one-dimensional processing and the two-dimensional processing and a transformation section that subjects an output of the transposition section to a discrete cosine transformation.

Abstract: A method and apparatus for including in a processor instructions for performing horizontal intra-add operations on packed data. One embodiment of the processor is coupled to a memory. The memory has stored therein at least a first packed data. The processor performs operations on data elements in the first packed data to generate a plurality of data elements in a second packed data in response to receiving an instruction. At least two of the plurality of data elements in the second packed data store the results of an intra-add operation, at least one of these results coming from the operation on data elements of the first packed data. One embodiment of a software method utilizes horizontal intra-add instructions for performing butterfly computations as may be employed, for example, in Walsh-Hadamard transforms or in Fast-Fourier Transforms.