Abstract: A data conversion processing circuit which effects processing for data conversion which projects two-dimensional data on a plurality of straight lines with different inclinations. The data conversion processing circuit includes a circuit unit for storing two-dimensional data, a circuit unit for producing x and y coordinate locating data, which serves as an addend, according to an angle &thgr; and generating a signal for use in selecting data, a circuit unit for selecting data, which serves as an addend, from among stored data in response to the control signal, and a circuit unit for adding selected data. For producing coordinates and selecting data, the data conversion processing circuit carries out arithmetic operations for a Hough transform expressed as AH(&rgr;, &thgr;)=∫a(&rgr;·cos &thgr;−t·sin &thgr;, &rgr;·sin &thgr;+t·cos &thgr;)dt. For handling different angles &thgr;, the arithmetic operations are carried out in a time-division manner.

Abstract: A VLSI wavelet transform (WT) architecture suitable for use in a discrete wavelet transform (DWT) or a discrete wavelet packet transform (DWPT). The WT architecture has a multiplier; an accumulator; at least two address generators that has a first address generator and a second address generator; a control unit; a memory of result that stores computation results; and a memory of table, which pre-stores all possible weights, each of which weights is a product of some specified filter coefficients for performing a DWT/DWPT with parameters of decomposition level, length of data segment, and filter length. The first address generator and the control unit receive data input, the control unit exports control signals to multiplier, accumulator, second address generator, and memory of table.

Abstract: The method of the present invention transforms descriptor vectors that characterize items partitioned into groups into a space that discriminates between those groups in a well defined optimal sense. First data is generated that represents a differences between the groups of descriptor vectors. Second data is generated representing variation within the groups of descriptor vectors. A set of component vectors is then identified that maximizes an F distributed criterion function that measures differences of descriptor vectors between groups relative to variations of descriptor vectors within groups. A statistic is generated for subsets of the component vectors. For each particular subset of component vectors, a probability value for the statistic associated with the particular subset is calculated. The subset with the minimum probability value is selected. Finally, one or more of the descriptor vectors for the items are mapped to a space corresponding to the selected subset of component vectors.

Abstract: A system (10) for generating a transform includes a first transform lookup table (12) and second transform lookup table (28). A transform exclusive OR array (26) is connected to an output (24) of the first transform lookup table (12) and an output (32) of the second transform lookup table (28). The system (10) allows transforms (polynomial codes, CRCs) to be generated using two or more tables.

Abstract: Apparatus, methods, and computer program products are provided for generating a second set of equations requiring reduced numbers of computations from a first set of general equations, wherein each general equation defines coefficients in terms of a set of samples and a plurality of functions having respective values. A first set of tokens is initially assigned to the plurality of functions such that every value of the functions that has a different magnitude is assigned a different token, thereby permitting each general equation to be defined by the set of samples and their associated tokens. Each general equation is then evaluated and the samples having the same associated token are grouped together. A second set of tokens is then assigned to represent a plurality of unique combinations of the samples. The second set of equations is then generated based at least on the first and second sets of tokens.

Abstract: According to the invention, a matrix of elements is processed in a processor. A first subset of matrix elements is loaded from a first location and a second subset of matrix elements is loaded from a second location. A third subset of matrix elements is stored in a first destination and a fourth subset of matrix elements is stored in a second destination. The loading and storing steps result from the same instruction issue.

Abstract: A digital channelizer employs a polyphase filter element in which a shift register is used to commutate time series data to a bank of polyphase filters at the inputs of an FFT module. The filter bank and FFT module are updated at a frequency that is independent of the rate that the data is fed into the buffer and filter/FFT cycle rates of less than the ratio of the input data rate to the number of input channels may be accommodated by the shift register commutation. The output of the FFT module is interpolation filtered by inserting interpolated points between adjacent data points in the channelized output stream to increase the output frequency by an integral multiple of the update rate of the polyphase filter/FFT update rate.

Abstract: A linear transform system (18) for decoding video data is provided. The system (18) includes inputs (50, 52, 54, 56, 58, 60, 62, 64) connected in series to a circuit (40) for implementing a decoding algorithm that includes a multiplication circuit stage (42, 44, 46) having a multiple output scaler structure (82, 84, 86). A bit-serial operator stage (48) is connected in series with the multiplication circuit stage (42, 44, 46). The bit-serial operator stage (48) is coupled to a plurality of outputs (66, 68, 70, 72, 74, 76, 78, 80) that generate decoded video data.

Abstract: The present invention is embodied in a system and method for fast computation of a spatial transform of an input signal. The computation system includes a window processor having a window function and an operator having a first set of weights. The window processor receives the input signal as sample blocks and the operator is adapted to apply butterfly coefficients determined by the window function to produce resulting vectors. Also, the window processor maps the input signal to a cascade of butterflies using the first set of weights and reorders the cascade of butterflies. A transform processor having a transform module computes a spatial transform from the reordered cascade of butterflies to produce transform coefficient. A coefficient combination operator combines the transform coefficients to produce an encoded output corresponding to the input signal.

Abstract: A method for solving many classes of real-world problems with a quantum mechanical system by coaxing the system from a starting state to a desired state that is present in the quantum mechanical system with a probability greater than zero. Moving of the quantum mechanical system toward the desired states is effected by a repeated application of operator Q≡−IsU−1ItU, U is a unitary matrix, Is is a diagonal matrix that characterizes the starting state of the system with 1's in every position along the diagonal, except at the position corresponding to column s and row s, which represents the starting state, where it is −1. It is a similar diagonal matrix that characterizes the desired target state, t. The Q transformation is applied a prescribed number of times, followed by a single transfomation U, yielding the desired target state.

Abstract: A reversible Discrete Cosine Transform (DCT) is described. The reversible DCT may be part of a compressor in a system. The system may include a decompressor with a reversible inverse DCT for lossless decompression or a legacy decompressor with an inverse DCT for lossy decompression.

Abstract: A Fast Fourier Transformation (FFT) method and apparatus is implemented using a radix-r butterfly design based on a reduced single phase of calculation, termed a butterfly-processing element (BPE). Butterfly calculations are each executed in the same number of iterations, and comprised of substantially identical butterfly-processing elements. The resulting algorithm, in which a number of parallel processors operate simultaneously by a single instruction sequence, reduces both the computational burden and the communication burden. The use of substantially identical butterfly-processing elements, repeated in combination to form a radix-r butterfly, enables the design of FFT butterflies containing identical structures and a systematic means of accessing the corresponding multiplier coefficients stored in memory. The butterfly-processing element substantially reduces the complexity of the radix-r butterfly, particularly for higher order radices.

Abstract: A system and method for encoding and decoding data utilizes Walsh-Hadamard Transforms and inversion techniques to generate the possible minimum disparity values for the data to be encoded. A minimum disparity value is then selected that also provides sufficient transition density.

Abstract: Adaptive windowing of Fast Fourier Transform (FFT) data to reduce spectral leakage and increase sidelobe rejection. The adaptive windowing is extended to 5 and 7 point convolution formulas. Thus, the present invention extends the non-static shift-variant data adaptive window generated from a spatial variant apodization. The extensions are achieved by using the window structure of multiple cosines. The sidelobe leakage of the adaptive windows is extremely small, the signal-to-noise ration is higher than conventional techniques and spectral detection is possible with higher order windowing.

Abstract: The invention relates to a method for the determination of the impulse response g(t) of a broad band linear system. The method can be used for the application of high frequency technology. For a test signal, a maximum length binary sequence (MLBS) is employed. The measured signal, obtained by the system, is sampled under maintenance of the sample theorem whereby the sampling clock in accordance with the invention is obtained directly from that high frequency clock pulse which is used for the generation of the MLBS. The digitized measured signal is then subjected to a fast Hadamard-transformation for calculation of the impulse response. The invention furthermore, provides a measuring circuit which carries out this method.

Abstract: A calculating apparatus performs FFT calculation or IFFT calculation on input data and then outputs the calculated data. An input buffer memory temporarily stores the input data and outputs it to a memory. An output buffer memory temporarily stores the final data of the calculating apparatus and then outputs it to an external source. The input buffer memory or the output buffer memory is provided with an address generating circuit. The address generating circuit sets the write addresses or the read addresses of the data to be stored in either buffer memory in a predetermined order. Thus, the frequency domain of the data in the calculating apparatus is converted without requiring the use of an external circuit.

Abstract: A fast Hadamard transform device is provided which prevent from increasing of circuit scale and shorten a developing TAT even if the number of bits to be operated. The device includes n of shift register units and n/2 of butterfly computation units. Input data are entered to the shift register units in response to a signal and data stored in the shift register units are supplied as quantized data by providing a signal for each “log2n*(p+log2n)” clocks.

Abstract: The mathematical foundations of conventional numerical simulation of physical systems provide no consistent description of the behavior of such systems when subjected to discontinuous physical influences. As a result, the numerical simulation of such problems requires ad hoc encoding of specific experimental results in order to address the behavior of such discontinuous physical systems. In the present invention, these foundations are replaced by a new combination of generalized function theory and nonstandard analysis. The result is a class of new approaches to the numerical simulation of physical systems which allows the accurate and well-behaved simulation of discontinuous and other difficult physical systems, as well as simpler physical systems. Applications of this new class of numerical simulation techniques to process control, robotics, and apparatus design are outlined.

Abstract: A hardware accelerator for a coding system for pictures includes an array of lines and columns of pixels, and calculates the variance of macroblocks of a digitized video image for a real-time coding of the current image together with the preceding and successive images, according to the MPEG-2 video algorithm. The architecture minimizes the silicon area needed for implementing the hardware accelerator for a cost-effective reduction on the CPU of the coding system. The use of a plurality of distinct filter/demultiplexers of known architectures is eliminated by conveying the incoming pixels to the respective input lines of distinct variance calculation paths by the use of a simple counter.

Abstract: Recently, a number of reversible wavelet transforms have been identified which allow for exact reconstruction in integer arithmetic. Different transforms vary in how rounding is performed. The present invention provides a transform, which is linear except for the rounding with non-linear operations in order to create a reversible implementation. Also, the present invention also provides transforms which are decomposed into all FIR parts.

Abstract: An image compression scheme uses a reversible transform, such as the Discrete Hartley Transform, to efficiently compress and expand image data for storage and retrieval of images in a digital format. The image data is divided into one or more image sets, each image set representing a rectangular array of pixel data from the image. Each image set is transformed using a reversible transform, such as the Hartley transform, into a set of coefficients which are then quantized and encoded using an entropy coder. The resultant coded data sets for each of the compressed image sets are then stored for subsequent expansion. Expansion of the stored data back into the image is essentially the reverse of the compression scheme.

Abstract: A compression/decompression engine is disclosed for reducing memory requirements of a decode system by storing decoded video data in compressed form. The compression engine comprises parsing chrominance UV data into separate chrominance U data and chrominance V data, and transform logic implementing a Hadamard transformation of multiple bytes of decoded video data in parallel into frequency domain signals. Compression logic is coupled to the transform logic and performs, preferably, a 2:1 transformation of the frequency domain signals to produce compressed video signals for storage in memory. The transform logic and compression logic transform and compress multiple bytes of decoded video data in parallel within a single clock cycle of the decode system. Upon retrieval from memory, the compressed data is returned to original format by the decompression engine, which employs the same transform logic as used by the compression engine.

Abstract: The present invention is embodied in a system and method for fast computation of a spatial transform of an input signal. The computation system includes a window processor having a window function and an operator having a first set of weights. The window processor receives the input signal as sample blocks and the operator is adapted to apply butterfly coefficients determined by the window function to produce resulting vectors. Also, the window processor maps the input signal to a cascade of butterflies using the first set of weights and reorders the cascade of butterflies. A transform processor having a transform module computes a spatial transform from the reordered cascade of butterflies to produce transform coefficient. A coefficient combination operator combines the transform coefficients to produce an encoded output corresponding to the input signal.

Abstract: A method and an apparatus for controlling calculation error produced by the accumulation error due to digit truncation in a non-integer computation. The error is eliminated by controlling the values of LSB, C.sub.in and the addition/subtraction selecting signal as, so that C.sub.in is not necessarily equal to C.sub.in. Considering a even number of cascaded pipelines, C.sub.in in the odd pipelines is set as 0, wherein C.sub.in in the even pipelines is set as 1. The resultant error is thus eliminated mutually by odd and even pipelines.

Abstract: The present invention is embodied in a system and method for fast computation of a spatial transform of an input signal. The computation system includes a window processor having a window function and an operator having a first set of weights. The window processor receives the input signal as sample blocks and the operator is adapted to apply butterfly coefficients determined by the window function to produce resulting vectors. Also, the window processor maps the input signal to a cascade of butterflies using the first set of weights and reorders the cascade of butterflies. A transform processor having a transform module computes a spatial transform from the reordered cascade of butterflies to produce transform coefficient. A coefficient combination operator combines the transform coefficients to produce an encoded output corresponding to the input signal.

Abstract: A digital signal processing apparatus comprises a sensor, a multi-valued binary level signal generator, a wavelet transform section, and a post processor. The signal generator receives analog signals output from the sensor and converts them to multi-valued binary level signals. The wavelet transform section has fundamental elements and threshold devices. The fundamental elements are provided at the nodes of a tree structure. Each threshold device is designed to receive at least two multi-valued signals and to output one binary signal, it receives the coefficients of the scaling functions output from the fundamental elements provided at the same level of the tree structure, for extracting the feature of the analog signal. The output signals of the wavelet transform section, i.e., the results of the wavelet transform, are input to the post processor. The apparatus can therefore perform signal processing including wavelet transform, at high speed without using large-scale hardware.

Abstract: The invention provides a coding system and a decoding system wherein a discrete cosine transform which provides a high coding efficiency is approximated to allow reversible coding and decoding while maintaining the high coding efficiency and a system which includes such coding and decoding systems. Reversible coding is realized by multiplying a transform matrix by a fixed number for each row to approximate the transform matrix with integer values, performing re-quantization in a basic region defined by a multiple of a determinant for suppressing redundancy while maintaining a condition wherein reversible coding is possible in the basic region, and performing re-quantization for the entire region making use of the fact that such basic region appears periodically in a signal space.

Abstract: A method for computing a decimation-in-time Fast Fourier Transform of a sample is provided, the method including inputting first 2B-bit values representing the sample into a radix-4 first section of the decimation-in-time Fast Fourier Transform and performing first complex 2B-bit integer additions and subtractions on the first 2B-bit values to form second 2B-bit values, without performing a multiplication. The method also includes rounding the second 2B-bit values to form B-bit values output from the radix-4 first section of the decimation-in-time Fast Fourier Transform.

Abstract: A data processing system (100) of the present invention analyses input data (10) for statistical similarities in time and determines processing steps depending on the analysis. The system (100) transfers a first data set (12) which changes at every time transition (i-1) to i into a second data set (13) to output sets (22 and 23) by a transfer function H. According to a method of the present invention, the number of calculation instructions h(n) which are performed is established by comparing consecutive old input data (12) and new input data (13). The transfer function H is thereby simplified and the number of executed instructions optimized.

Abstract: The invention provides a high speed two-dimensional discrete cosine transform circuit which can reduce the number of addition operations for rounding to one time. The two-dimensional IDCT circuit calculates M.times.N-point two-dimensional inverse discrete cosine transforms wherein M.times.N is equal to 2.sup.2n, and includes an M.times.N two-dimensional IDCT operator for calculating two-dimensional inverse discrete cosine transforms as matrix vector products of a transform matrix of MN rows and MN columns and MNth-order input vectors, a shift operator for shifting results of the calculation of the M.times.N two-dimensional IDCT operator rightwardly, and an adder for adding 2.sup.n-2 to a discrete cosine coefficient from among discrete cosine transform coefficients to be inputted to the M.times.N two-dimensional IDCT operator. An output signal of the shift operator is outputted as a circuit output signal of the two-dimensional IDCT circuit.