Abstract: A method of performing a Grover's or a Deutsch-Jozsa's quantum algorithm being input with a binary function defined on a space having a basis of vectors of n of qubits includes carrying out a superposition operation over input vectors for generating components of linear superposition vectors referred to a second basis of vectors of n+1 qubits. An entanglement operation is performed over components of the linear superposition vectors for generating components of numeric entanglement vectors. The method allows a non-negligible time savings because the entanglement operation does not multiply a superposition vector for an entanglement matrix, but generates components of an entanglement vector simply by copying or inverting respective components of the superposition vector depending on values of the binary function. An interference operation is performed over components of the numeric entanglement vectors for generating components of output vectors.

Abstract: A method and apparatus for performing a radix-4 fast Hadamard transform (FHT) with reduced complexity that utilizes only seven operations and for directly determining the maximum output of a fast Hadamard transform using either a radix-4 transform or radix-2 transform without actually generating the outputs. To find the maximum value of the output of a fast Hadamard transform and its corresponding index, the N−1 stages of a conventional N stage fast Hadamard transform are computed while a find-maximum stage is inserted in place of the Nth stage. The invention also provides a methodology for constructing fast Hadamard transforms of the form H2N using radix-4 FHTs and permuting the results to achieve the correct outputs.

Abstract: A flipping algorithm for the hardware realization of Lifting-based DWT, relates a flipping algorithm and hardware architecture for the hardware realization of Lifting-based DWT, by using lifting architecture as starting point, by multiplying the edge of the cutset which is through the multiplier and the basic computing unit by the reciprocal of multiplier coefficient in order to cut off the accumulation effect of timing delay.

Abstract: A one-dimensional wavelet system and method. In various embodiments, computation engines are set forth for forward and inverse transforms in a wavelet system. The computation engine includes a plurality of register banks having input ports arranged to receive input sample values and a multiplexer coupled to the output ports of the register banks. A processing unit is configured to perform the forward or inverse wavelet transform for data values that are sequenced through the register banks and multiplexer by a control unit. The computation unit is adaptable to implement discrete wavelet transform, discrete wavelet packet, and custom wavelet trees.

Abstract: Techniques for arranging operations performable on information in an information processing system are provided. In a system having a plurality of information producers and a plurality of information subscribers, paths are identified over which information traverses, and within which the information is subject to select and/or transform operations. The present invention optimizes the system by reorganizing the sequence of select and transform operations so that transforms follow select operations; and by combining multiple select and transform operations into single select and transform operations, respectively. Using these optimizations, the processing resources of the system can be reorganized, and/or information flow graphs describing the system can be designed, so that the select operations are “pushed” toward the producers, and transform operations are “pushed” toward the subscribers. Efficient content-based routing systems can then be used to implement the select operations.

Abstract: Input signals are transformed with an Hadamard transformation matrix in each of the four four-point Hadamard transformation units, wherein a rounding unit rounds up the least significant bit of each of the odd number of coefficients and discards the least significant bit of each of the remaining odd number of coefficients among the four transformed coefficients output from each of the four-point Hadamard transformation units to produce four sets of four integer coefficients, and one integer coefficient is selected from each set, and four selected integer coefficients including odd number of rounded up are input to an Hadamard transformation unit and are Hadamard transformed, and the Hadamard transformed coefficients are rounded up to produce integer.

Abstract: A digital image coding device based on wavelet transform technology includes a lower-bitplane replacement section which is provided after a coefficient modeling section and before an arithmetic coding section. The coefficient modeling section converts wavelet coefficients into binary data composed of a plurality of bitplanes for each code-block. The lower-bitplane replacement section replaces a designated number of lower-order bitplanes of the plurality of bitplanes with zero to produce modified binary data. The designated number of low-order bitplanes is designated depending on a noise characteristic of the image capturing device. The arithmetic coding section codes bitplanes of the modified binary data.

Abstract: A one-dimensional (1D) Inverse Discrete Cosine Transform (IDCT) is applied to an input two-dimensional (2D) transform block along the axis to be modified. Since the one-dimensional IDCT is not performed on the other axis, each block is left in a one-dimensional transform space (called hybrid space). For a shift (merge), the appropriate “m” elements are picked up from one block and the “8−m” elements are picked up from the other block and are used as input to the one-dimensional forward DCT (FDCT) along that same axis. For two-dimensional shifts or merges, the results of the first one-dimensional IDCT and FDCT can be stored with extra precision to be used as input to a second one-dimensional IDCT and FDCT along the other axis. The execution time worst case conditions are approximately constant for all shift/merger amounts. Taking advantage of fast paths can improve the execution times for typical blocks.

Abstract: A generalized radix-2 block transform method enables true split and merge transform processing of equal sized data halves in the transform domain enabling recursive merges and splits in transform domain data degradation. Input data in the time domain or spatial domain during either the split and merge radix-2 forward transform processing is firstly transform processed followed by combinational processing. In the split transform process, whole transformed data is split using combinational processing into first and second transformed data halves in the transform domain as a true split. In the merge transform process, first and second transform halves are merged using combinational processing into a merged transformed data whole in the transform domain. In either case, time or spatial domain input data can be transformed into the transform domain in the form of split halves or merged whole.

Abstract: Fast Hartley Transforms in a radix-2 block transform method enables true split and merge transform processing of equal sized data halves in the transform domain for enabling recursive merges and splits in transform domain without data degradation. Input data in the time domain or spatial domain during either the split and merge radix-2 forward transform processing is firstly transform processed followed by combinational processing. In the split transform process, whole transformed data is split using combinational processing into first and second transformed data halves in the transform domain as a true split. In the merge transform process, first and second transform halves are merged using combinational processing into a merged transformed data whole in the transform domain. In either case, time or spatial domain input data can be transformed into the transform domain in the form of split halves or merged whole.

Abstract: Discrete Sine Transforms in a radix-2 block transform method enables true split and merge transform processing of equal sized data halves in the transform domain for enabling recursive merges and splits in transform domain without data degradation. Input data in the time domain or spatial domain during either the split and merge radix-2 forward transform processing is firstly transform processed followed by combinational processing. In the split transform process, whole transformed data is split using combinational processing into first and second transformed data halves in the transform domain as a true split. In the merge transform process, first and second transform halves are merged using combinational processing into a merged transformed data whole in the transform domain. In either case, time or spatial domain input data can be transformed into the transform domain in the form of split halves or merged whole.

Abstract: Fast Fourier Transforms in a radix-2 block transform method enables true split and merge transform processing of equal sized data halves in the transform domain for enabling recursive merges and splits in transform domain without data degradation. Input data in the time domain or spatial domain during either the split and merge radix-2 forward transform processing is firstly transform processed followed by combinational processing. In the split transform process, whole transformed data is split using combinational processing into first and second transformed data halves in the transform domain as a true split. In the merge transform process, first and second transform halves are merged using combinational processing into a merged transformed data whole in the transform domain. In either case, time or spatial domain input data can be transformed into the transform domain in the form of split halves or merged whole.

Abstract: Discrete Karhunen-Loeve Transforms in a radix-2 block transform method enables true split and merge transform processing of equal sized data halves in the transform domain for enabling recursive merges and splits in transform domain without data degradation. Input data in the time domain or spatial domain during either the split and merge radix-2 forward transform processing is firstly transform processed followed by combinational processing. In the split transform process, whole transformed data is split using combinational processing into first and second transformed data halves in the transform domain as a true split. In the merge transform process, first and second transform halves are merged using combinational processing into a merged transformed data whole in the transform domain. In either case, time or spatial domain input data can be transformed into the transform domain in the form of split halves or merged whole.

Abstract: Discrete Cosine Transforms in a radix-2 block transform method enables true split and merge transform processing of equal sized data halves in the transform domain for enabling recursive merges and splits in transform domain without data degradation. Input data in the time domain or spatial domain during either the split and merge radix-2 forward transform processing is firstly transform processed followed by combinational processing. In the split transform process, whole transformed data is split using combinational processing into first and second transformed data halves in the transform domain as a true split. In the merge transform process, first and second transform halves are merged using combinational processing into a merged transformed data whole in the transform domain. In either case, time or spatial domain input data can be transformed into the transform domain in the form of split halves or merged whole.

Abstract: The known signal that is transmission data for the pilot carrier is output to multiplier 103 to be subjected to amplitude adjustment (gain control) using a predetermined coefficient. The coefficient is set as appropriate in the range that makes an amplitude of the known signal larger than the amplitude of a message signal in consideration of, for example, error rate deterioration and increment of peak power in the entire transmission power. In addition, since the number of pilot carriers is small as compared to the number of all carriers, the increment of the gain of the pilot carrier does not generally have a large effect on the increment of the peak power.

Abstract: A transformation engine includes an address generator; a butterfly unit coupled to the address generator; a twiddle LUT coupled to the address generator; and a multiplexer having a first input coupled to the butterfly unit and a second input coupled to the twiddle LUT.

Abstract: A digital filter includes a plurality of filter cells, each of which includes circuitry to determine a coefficient for the filter cell, to adjust the coefficient in accordance with a gain that is used by each of the plurality of filter cells, and to multiply input data by the adjusted coefficient in order to generate a filter cell output. An adder circuit generates a filter output by adding filter cell outputs from each of the plurality of filter cells, and an inverse gain circuit adjusts the filter output in accordance with an inverse of the gain used to adjust the coefficients of the plurality of filter cells.

Abstract: The present invention relates to a filter bank approach to adaptive filtering method using independent component analysis. More particularly, the invention relates to a method of improving the performance of adaptive filtering method by applying independent component analysis that is capable of reflecting the secondary or even higher order statistical characteristics to adaptive filtering algorithm using the filter bank approach.

Abstract: An apparatus and method are provided for performing both forward and inverse Haar transforms of a sequence of n-bit data samples. The forward Haar transform apparatus has sum-and-truncate logic and a plurality of coefficient generators. The sum-and-truncate logic generates a plurality of n-bit intermediate terms. The plurality of coefficient generators is coupled to the sum-and-truncate logic. The plurality of coefficient generators generate a plurality of spectral coefficients, where at most n+1 bits are required to represent each of the plurality of spectral coefficients. The inverse Haar transform apparatus has index signal and inverse transform logic. The index signal indicates a specific n-bit sample, the specific n-bit sample being one of a sequence of n-bit samples corresponding to the Haar transform. The inverse transform logic is coupled to the index signal.

Abstract: The power consumption, memory allocation, and CPU time used in a signal processor executing a fast transform can be optimized by using a particular method of scheduling the calculations. The transform typically is used to transform a first m-dimensional indexed array into a second m-dimensional indexed array. The elements of the first m-dimensional array are grouped according to the index difference between the elements of the particular butterfly code of that stage. A second grouping of elements is composed of butterfly code elements having non-maximal index differences. The second group advantageously includes elements also assigned to the first group. The butterfly codes of the groups are arranged sequentially and are executed in the sequential schedule. In a second embodiment, elements are grouped according to a group specific threshold value. Memory is allocated to the groups according to the size of the group such that the access to memory is minimized during execution.

Abstract: The present invention provides a method and apparatus that transforms input signals X0, X1, X2, X3 using a 4-point Hadamard transform matrix, and of the resulting transformation data, rounds up the LSB of the first transformed data and rounds down the LSB of the remaining odd-numbered data. When restoring the data to its original state the rounding is executed after a Hadamard inverse transformation is performed, thereby restoring the data to its original state X0, X1, X2, X3.

Abstract: The present invention provides an algorithm and hardware structure for numerical operations on signals that is reconfigurable to operate in a downsampling or non-downsampling mode. According to one embodiment, a plurality of adders and multipliers are reconfigurable via a switching fabric to operate as a plurality of MAAC kernels (described in detail below), when operating in a non-downsampling mode and a plurality of MAAC kernels and AMAAC kernels (described in detail below), when operating in a downsampling mode.

Abstract: A method of transposing an array using diagonal access. An array of m rows, m diagonals up, and m diagonals down. Rows and diagonals access the same array using different mapping functions. Each row comprising n data element. Each diagonal comprising of n data element. First, every row of the array is loaded into the diagonals up with same index number in a new storage array. Second, every row of the new array is rotated by its index number. Third, the new array is stored back in the original array using the diagonals down. The result, a transposed array of the original array is completed.

Abstract: A register file structure efficiently handles matrix and image processing. The register file contains an array of data elements and has modes for accessing of multiple data values that are aligned horizontally or vertically in a data array and for accessing data having different widths for each data value. The different modes allow manipulation of a transposed array without requiring a transpose operation and permit fast horizontal or vertical filtering with parallel access and multiplications of horizontally or vertically aligned data elements.

Abstract: An apparatus and method are provided for performing both forward and inverse Haar transforms of a sequence of n-bit data samples. The forward Haar transform apparatus has sum-and-truncate logic and a plurality of coefficient generators. The sum-and-truncate logic generates a plurality of n-bit intermediate terms. The plurality of coefficient generators is coupled to the sum-and-truncate logic. The plurality of coefficient generators generate a plurality of n+1-bit spectral coefficients. The inverse Haar transform apparatus has index signal and inverse transform logic. The index signal indicates a specific n-bit sample, the specific n-bit sample being one of a sequence of n-bit samples corresponding to the Haar transform. The inverse transform logic is coupled to the index signal. The inverse transform logic computes the specific n-bit sample, where the specific n-bit sample is derived from selected n+1-bit spectral coefficients.

Abstract: The present invention discloses methods for condition-based monitoring of a system and its components using joint time-frequency analysis and signal demodulation. A first method allows construction of models of non-stationary signals having multiple time and frequency scales of interest. In particular, the method uses wavelet analysis to encode essential information in time-frequency transformations and provides a signal model for an operating fault or normal operation of a system of interest. A second method uses the signal models for condition-based monitoring to detect a change in a signal. In this method, the signal models are correlated with sensor signals to determine the operating condition of a system or system component. A third method for condition-based monitoring uses signal demodulation. In this method, a nominal response of a system component is subtracted from a detected signal to more reliably detect subtle changes in the signal due to component degradation.

Abstract: A discrete wavelet transform apparatus for a lattice structure is disclosed. This apparatus includes first through M-th lattice lattices installed in series along the length of a selected filter and each having an upper signal path and a lower signal path for supplying an output of the discrete wavelet transform apparatus, a data form transform unit for converting the form of the input signal and supplying to the first lattice stage, and a delay control unit connected between the lattice stages for thereby simplifying the hardware structure and implementing a scalable characteristic with respect to the different resolution levels and different filter lengths.

Abstract: Architecture and method for performing discrete wavelet transforms An architecture component an a method for use in performing a 2-dimensional discrete wavelet transform of 2-dimensional input data is disclosed. The architecture component comprises a serial processor for receiving the input signal row-by-row, a memory for receiving output coefficients from the serial processor, and a parallel processor for processing coefficients stored in the memory and a serial processor for processing further octaves. The parallel processor is operative to process in parallel coefficients previously derived from one row of input data by the serial processor.

Abstract: The invention relates to a device (FFTP) for computing discrete transforms. The device comprises a local memory (RAM2) for registering results of sub-transform computations, a sub-transform computation comprising several computation layers. The device is characterized by computation means (CAL_M) which are capable of interlacing computation layers of two or several consecutive sub-transforms of the same size.

Abstract: The invention relates to a microprocessor structure for performing a discrete wavelet transform operation. It uses a flowgraph representation of discrete wavelet transforms (DWTs) and wavelet packets. This representation is useful for developing efficient parallel algorithms and VLSI architectures. As examples, two DWT architectures for Haar wavelets and three architectures for Hadamard wavelets and wavelet packets are proposed with the efficiency (counted as the measure of the average utilization of basic processing elements) of approximately 100%. The proposed architectures are fast and provide excellent performance with respect to area-time characteristics. They are scalable, simple, regular, and free of long connections (depending on the length of input signal). The invention can be extended to inverse wavelet transforms.

Abstract: A method is provided for logarithmic compression, transmission, and expansion of spectral data. A log Gabor transformation is made of incoming time series data to output spectral phase and logarithmic magnitude values. The output phase and logarithmic magnitude values are compressed by selecting only magnitude values above a selected threshold and corresponding phase values to transmit compressed phase and logarithmic magnitude values. A reverse log Gabor transformation is then performed on the transmitted phase and logarithmic magnitude values to output transmitted time series data to a user.

Abstract: A digital signal transformation method, in which the original samples (x2i; y12i) of the digital signal are transformed into output samples (y12i, x2i). Any output sample being calculated by a function of original samples, and/or of intermediate samples (t2i+1, v2i, t12i, v12i+1), and/or of output samples is characterized in that each function is broken down into elementary operations, and the elementary operations of all the functions are ordered so as to minimize the number of samples that are simultaneously necessary. The invention makes it possible to minimize the memory space necessary to calculate the transformation.

Abstract: A digital signal processor DSP for bit-reversal of a large data array of a size has a direct memory access (DMA) controller for performing in-place bit reversal routines on an external memory during a first stage, and a central processing unit (CPU) for swapping small sub-arrays on internal memory in a second stage. The two stage method according to the invention importantly reduces the real-time implementation for sorting large size data arrays on uni-processor DSP platforms, by extensively using the external memory and avoiding a random access to the internal memory. As well, the invention provides for improved dense integration and reduced costs when used in dense wavelength division multiplexing (DWDM) systems.

Abstract: The invention provides a system and method for quantum computation comprising the steps of defining a Hilbert space to represent a physical quantum mechanical system; selecting a set of quantum observables for said system; selecting a subspace of said Hilbert space in which all states representing said quantum mechanical system have the same eigenvalue; and storing information in or processing information using said subspace. In addition, the invention provides a system and method for quantum computation, comprising defining a Hilbert space to represent a physical quantum mechanical system; selecting a subspace of said Hilbert space in which the quantum mechanical state of the physical system is decoherence free; and processing quantum information using the quantum mechanical system by controlling only multi body interactions.

Abstract: A Fast Chirp Transform (FCT) for the digital processing of chirp signals and exemplary applications. The FCT is a generalization of a multidimensional Fast Fourier Transform. Phase coefficients for boundary intervals are calculated using phase functions describing the time dependent frequency characteristics of an input signal in the time domain. A multidimensional FFT is performed on the dot product of the phase coefficients and the input signal resulting in a multidimensional representation of the input signal in the frequency domain. The FCT and its inverse can be used to enhance the signal to noise ratio in applications involving chirp signals.

Abstract: Two-dimensional discrete wavelet transform analysis and synthesis banks. In various embodiments, a cascade combination of two one-dimensional wavelet transforms is implemented, along with a set of memory buffers between the two stages. The memory buffers store intermediate results between the stages of the two-dimensional discrete wavelet transform, thereby eliminating off-chip memory references.

Abstract: The invention relates to a method for determining the parameters, in particular the characteristics of an n-gate, in particular in an amplifier (8). The parameters are determined by applying and optional simultaneous measurement of an input signal sequence with various amplitudes and measuring an output signal sequence, taking into account a skew which the output signal sequence has relative to the input signal sequence. The skew is thus determined by correlation of output signal sequence with the input signal sequence.

Abstract: The present invention is embodied in a system and method for performing spectral analysis of a digital signal having a discrete duration by spectrally decomposing the digital signal at predefined frequencies uniformly distributed over a sampling frequency interval into complex frequency coefficients so that magnitude and phase information at each frequency is immediately available to produce a modulated complex lapped transform (MCLT). The present invention includes a MCLT processor, an acoustic echo cancellation device and a noise reducer integrated with an encoder/decoder device.

Abstract: A system and method for parallel computation of Discrete Sine and Cosine Transforms. The computing system includes a plurality of interconnected processors and corresponding local memories. An input signal x is received, partitioned into P local vectors xi, and distributed to the local memories. The preprocessors may calculate a set of coefficients for use in computing the transform. The processors perform a preprocess in parallel on the input signal x to generate an intermediate vector y. The processors then perform a Fast Fourier Transform in parallel on the intermediate vector y, generating a second intermediate vector a. Finally, the processors perform a post-process on the second intermediate vector a, generating a result vector v, the Discrete Transform of signal x. In one embodiment, the method generates the Discrete Sine Transform of the input signal x. In another embodiment, the method generates the Discrete Cosine Transform of the input signal x.

Abstract: The present invention is embodied in a system and method for performing spectral analysis of a digital signal having a discrete duration by spectrally decomposing the digital signal at predefined frequencies uniformly distributed over a sampling frequency interval into complex frequency coefficients so that magnitude and phase information at each frequency is immediately available to produce a modulated complex lapped transform (MCLT). The system includes real and imaginary window processors and real and imaginary transform processors. The real and imaginary window processors receive the input signal and apply and compute butterfly coefficients for the real and imaginary parts of the signal to produce resulting real and imaginary vectors, respectively. The real and imaginary transform processors compute spatial transforms on the real and imaginary vectors to produce real and imaginary transform coefficient of the MCLT, respectively.

Abstract: An improved architecture for efficiently calculating a discrete wavelet transform is presented. The present system appreciates the associated redundancies of calculations and proposes a topology for eliminating such redundant calculations through the use of storing and making such previously calculated coefficients available in successive wavelet coefficient calculations. The present system while recognizing redundant calculations and performing storage operations, also provides a pipelined architecture whereby the wavelet coefficients are calculated and combined for use in a wavelet packet tree architecture.

Abstract: An ASIC-implemented wavelet transformation engine (circuit) providing a wavelet filter is described. The wavelet filter itself provides up to a 9-stage FIR (finite impulse response) filter with symmetrical coefficients. The architecture of the filter includes data inputs, a bank of shift registers (register bank), coefficient registers, a multiplier/accumulator, a sub-sampling component, and output (results) registers. The filter provides a wavelet-based compression solution that may be implemented in less-costly, page-based memory architecture (e.g., SDRAM), and does so in a manner that overcomes the inherent speed disadvantage encountered due to the horizontal-optimized access strategy employed by page-based memory architectures.

Abstract: A circuit arrangement and method for performing the 2-D DCT. An input permutation processor reorders input samples, constructing a logical matrix of input samples. A plurality of 1-D DCT processors are arranged to receive the reordered data and apply the 1-D DCT along extended diagonals of the matrix. The output polynomials from the 1-D DCT processors are provided to a polynomial transform processor, and the output data from the polynomial transform processor are reordered, by an output permutation processor. The 1-D DCT processors and polynomial transform are multiplier free, thereby minimizing usage of FPGA resources in an FPGA implementation.

Abstract: A method for generating a first plurality of output data values and the matrix factors used to generate an approximation to an image processing transform is disclosed. The first plurality of output data values are generated by transforming a plurality of input data values using a computer and applying a modified transform stored in a modified transformation matrix to the plurality of input data values. The plurality of input data values are stored in a generated matrix, and at least one data value in this matrix is rearranged using a permutation operation and modified by applying a linear combination of the unmodified values to the at least one data value. The modified transform is an approximation to a known transform stored in a transformation matrix that is used to generate a second plurality of output data values, the first plurality of output values approximating the second plurality of output data values.

Abstract: A data processing apparatus and method for quickly and efficiently producing a diagonally (170) mirrored image of a block of data (168). The apparatus comprises a first input operand (182) consisting of a first half of an N×N bit data block and a second input operand (184) consisting of a second half of an N×N bit data block. A first hardware bit transformation (188) forms an upper half of an N-way bit deal of the two operands (186), and a second hardware bit transformation (192) forms a lower half of the N-way bit deal (190). The upper and lower halves of the N-way bit deal represent a diagonally mirrored image (172) of the N×N bit data block. The method retrieves a data block from memory and packs it into two input operand registers. The two hardware bit transformations fill respective destination registers. The data is unpacked from the destination registers and stored to memory.

Abstract: A method of scaling image and video processing computational complexity in accordance with maximum available quantities of computational resource units, the method including the steps of: performing a plurality of data multiplications which processes digital image and video data, each data multiplication having a data dependent value multiplied by data independent value, the performance of each data multiplication requiring a predetermined quantity of computational resource units; selecting one of the data multiplications; selecting a shift/add-, a shift/subtract or a shift-operation using the data independent value associated with the selected multiplication that requires a quantity of computational resource units which is less than the predetermined quantity of computational resource units required for performing the selected multiplication; and performing the selected multiplication with the selected operation.

Abstract: A method for generating data characterizing an item described by an ordered string of characters, comprises the steps of: (i) for a set of separation metrics each representing a unique number of positions of separation between arbitrary characters in a character group in the ordered string of characters, associating first with each separation metric; generating a set of character groups, wherein each character group comprises at least two characters contained within the ordered string of characters; and (ii) for at least one given character group in the set of character groups, for each given separation metric in the set of separation metrics, generating second data representing number of occurrences that the given character group satisfies the given separation metric; generating third data associated with the given character group, wherein the third data is based upon the second data and the first data; and storing the third data in memory for subsequent use.

Abstract: An architecture component for use in performing a wavelet transform of a sampled signal, and an architecture including such components are disclosed. The architecture component includes a multiplier, and a multiplexor to multiplex a number n of filter coefficients onto the multiplier. The multiplier processes n consecutive samples with consecutive coefficients, successive multiplier outputs being stored for subsequent processing to generate an output of the filter after every n samples. The wavelet transform may be a discrete wavelet transform or a wavelet packet decomposition. The architecture component may be configured to multiplex two or more coefficients onto a multiplier. Embodiments are disclosed in which the components are derived from a parameterized description in a hardware description language.

Abstract: The invention comprises an efficient system and method for performing the modified discrete cosine transform (MDCT) in support of time-domain aliasing cancellation (TDAC) perceptive encoding compression of digital audio. In one embodiment, an AC-3 encoder performs a required time-domain to frequency-domain transformation via a MDCT. The AC-3 specification presents a non-optimized equation for calculating the MDCT. In one embodiment of the present invention, an MDCT transformer is utilized which produces the same results as carrying out the calculations directly as in the AC-3 equation, but requires substantially lower computational resources. Because the TDAC scheme requires MDCT calculations on differing block sizes, called the long and short blocks, one embodiment of the present invention utilizes complex-valued premultiplication and postmultiplication steps which prepare and arrange the data samples so that both the long and short block transforms may be computed with a computationally efficient FFT.

Abstract: A method and an apparatus for computing Fast Fourier Transforms (FFT) on a serial input of data blocks are described. Two input buffers share one data processing device in such a way that, at any given time, one buffer is receiving input data while the data in the other buffer is being processed. The need for bit reversal of the data block in the input buffer is eliminated, thus removing one time consuming step in the FFT. This is achieved by writing blocks of input data to the buffer alternately in natural order and in bit reversed order. When the output data in the buffer is in the reverse order, the buffer is addressed in the same reverse order so that the data points are sent in the correct order to the output. At the same time, the new input data is written to the buffer in the reverse order.