Addressing Or Allocation; Relocation (epo) Patents (Class 711/E12.002)
  • Publication number: 20120311290
    Abstract: A constrained computing device is provided. The constrained computing device includes a memory, a processor coupled to the memory, and a journaling component executed by the processor in kernel mode. The journaling component is configured to receive information descriptive of a device control, allocate, in the memory, a variable record structured according to a variable definition associated with the device control, store the information within the variable record, receive updated information descriptive of the device control, allocate, in the memory, an update record structured according to an update variable definition, store the updated information within the update record, and link the variable record to the update record.
    Type: Application
    Filed: June 1, 2011
    Publication date: December 6, 2012
    Inventor: Sean White
  • Patent number: 8327101
    Abstract: A data processing system includes a mechanism for completing an asynchronous memory move (AMM) operation in which the processor receives an AMM ST instruction and processes a processor-level move of data in virtual address space and an asynchronous memory mover then completes a physical move of the data within the real address space (memory). A status/control field of the AMM ST instruction includes an indication of a requested treatment of the lower level cache(s) on completion of the AMM operation. When the status/control field indicates an update to at least one cache should be performed, the asynchronous memory mover automatically forwards a copy of the data from the data move to the lower level cache, and triggers an update of a coherency state for a cache line in which the copy of the data is placed.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: December 4, 2012
    Assignee: International Business Machines Corporation
    Inventors: Ravi K. Arimilli, Robert S. Blackmore, Chulho Kim, Balaram Sinharoy, Hanhong Xue
  • Patent number: 8327057
    Abstract: A device may receive requests intended for a memory that includes a number of banks, determine a number of the requests intended for each of the banks, determine an order for the requests based on the determined number of the requests intended for each of the banks, and send one of the requests to the memory based on the determined order.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: December 4, 2012
    Assignee: Juniper Networks, Inc.
    Inventors: Anjan Venkatramani, Srinivas Perla, John Keen
  • Patent number: 8327085
    Abstract: An approach is provided that uses a hypervisor to allocate a shared memory pool amongst a set of partitions (e.g., guest operating systems) being managed by the hypervisor. The hypervisor retrieves memory related metrics from shared data structures stored in a memory, with each of the shared data structures corresponding to a different one of the partitions. The memory related metrics correspond to a usage of the shared memory pool allocated to the corresponding partition. The hypervisor identifies a memory stress associated with each of the partitions with this identification based in part on the memory related metrics retrieved from the shared data structures. The hypervisor then reallocates the shared memory pool amongst the plurality of partitions based on the identified memory stress of the plurality of partitions.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: December 4, 2012
    Assignee: International Business Machines Corporation
    Inventors: Vaijayanthimala K. Anand, Richard Louis Arndt, David Alan Hepkin, Sergio Reyes, Kenneth Charles Vossen
  • Publication number: 20120303919
    Abstract: A memory management system and method for managing memory blocks of a memory device of a computer. The system includes a free block data structure including free memory blocks for writing, and sorting the free memory blocks in a predetermined order based on block write-erase endurance cycle count and receiving new user-write requests to update existing data and relocation write requests to relocate existing data separately, a user-write block pool for receiving youngest blocks holding user-write data (i.e., any page being updated frequently) from the free block data structure, a relocation block pool for receiving oldest blocks holding relocation data (i.e., any page being updated infrequently) from the free block data structure, and a garbage collection pool structure for selecting at least one of user-write blocks and relocation blocks for garbage collection, wherein the selected block is moved back to the free block data structure upon being relocated and erased.
    Type: Application
    Filed: August 6, 2012
    Publication date: November 29, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xiao-yu Hu, Evangelos S. Eleftheriou, Robert Haas
  • Publication number: 20120303925
    Abstract: The present invention discloses a method and a device for configuring memory capacity, which relates to the field of computer technologies, so as to solve the problem of complex operations of a method for configuring memory capacity in the prior art. A technical solution provided in an embodiment of the present invention includes: performing a first read/write operation on data in a first memory space; if a system status does not change during the first read/write operation, performing a second read/write operation on data in a second memory space obtained by updating the first memory space; if the system status changes during the first/second read/write operation, obtaining a memory address when the system status changes; and configuring the memory capacity according to the memory address. Embodiments of the present invention may be applied in an embedded system or a computer.
    Type: Application
    Filed: August 6, 2012
    Publication date: November 29, 2012
    Inventors: Zhikui HUANG, Yaobing Li, Jian Zhou
  • Publication number: 20120303911
    Abstract: An electronic device may include a memory, and a processor coupled to the memory for storing and accessing data in the memory. The processor may arrange the data in a stack data container including values extending from a stack top to a stack bottom, operate the stack data container in first and second modes of operation, and while in the first mode of operation, push and pop a respective value from the stack top of the stack data container. The processor may also while in the second mode, reverse an orientation of the stack data container and the values therein, and push and pop a respective value from the stack bottom of the reversed stack data container.
    Type: Application
    Filed: May 24, 2012
    Publication date: November 29, 2012
    Inventor: Laurie Dean Perrin
  • Publication number: 20120303926
    Abstract: There is provided a storage subsystem having a virtual volume and a page volume which has a page physical area allocated to the virtual volume. The storage subsystem divides an address space of the virtual volume into a plurality of pages, classifies each of the pages into one of a plurality of states including at least a first state and a second state, and further divide a page which is classified into the second state into a plurality of segments to managed the page classified into the second state. The first state is a state in which a page physical area is allocated to the page from the page volume, and the write data is stored in the page physical area. The second state is a state in which the predetermined pattern data and the segment are managed, in the memory, by correlating with each other.
    Type: Application
    Filed: August 7, 2012
    Publication date: November 29, 2012
    Inventors: Yoshinori OHIRA, Shoji KODAMA, Kenta SHIGA, Yoshiaki EGUCHI
  • Publication number: 20120303927
    Abstract: Methods and systems for managing memory allocation requests are disclosed. Generally, the methods and systems relate to splitting and combining twin buffers for allocating memory of appropriate sizes in response to memory requests. One method disclosed is a method of allocating storage space in a memory of a computing system. The method includes receiving a memory allocation request, the memory allocation request defining a requested memory size, and the memory logically segmented into a plurality of blocks. The method also includes determining whether a block having a best-fit size is available from a buffer pool, the buffer pool selected from among the one or more buffer pools and defining a set of available blocks of a common size. The method includes, upon determining that no block having the best-fit size is available in the buffer pool, locating an available block from a second buffer pool from among the one or more buffer pools, the available block having a size twice the best-fit size.
    Type: Application
    Filed: May 24, 2011
    Publication date: November 29, 2012
    Inventor: Richard Goldberg
  • Publication number: 20120303918
    Abstract: In a computer-implemented data storage system comprising at least one storage control and data storage, wherein data is stored in the form of volumes, at least a plurality of volumes having at least some freespace, and a grouping of a plurality of volumes comprises a pool. In response to a defragmentation request, the storage control initiates migration of data from a pool to generate additional freespace. Subsequent to the migration of data, fragmentation of data of the pool is computed, and the amount of existing freespace of the pool is determined. The amount of existing freespace is compared to a freespace threshold, where the freespace threshold is related to the computed fragmentation. If the comparison indicates the amount of freespace is below the threshold, spill volumes are added to the pool; and, else, the pool is kept intact without adding spill volumes. Then, defragmentation of the pool is initiated.
    Type: Application
    Filed: April 26, 2012
    Publication date: November 29, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: DAVID C. REED, MAX D. SMITH
  • Publication number: 20120303916
    Abstract: In a computer-implemented data storage system comprising at least one storage control and data storage, wherein data is stored in the form of volumes, at least a plurality of volumes having at least some freespace, and a grouping of a plurality of volumes comprises a pool. In response to a defragmentation request, the storage control initiates migration of data from a pool to generate additional freespace. Subsequent to the migration of data, fragmentation of data of the pool is computed, and the amount of existing freespace of the pool is determined. The amount of existing freespace is compared to a freespace threshold, where the freespace threshold is related to the computed fragmentation. If the comparison indicates the amount of freespace is below the threshold, spill volumes are added to the pool; and, else, the pool is kept intact without adding spill volumes. Then, defragmentation of the pool is initiated.
    Type: Application
    Filed: May 25, 2011
    Publication date: November 29, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: DAVID C. REED, MAX D. SMITH
  • Publication number: 20120303928
    Abstract: A method and a storage system are provided for implementing deterministic memory allocation for indirection tables for persistent media or disk drives, such as, shingled perpendicular magnetic recording (SMR) indirection tables. A plurality of fixed-size memory pools are used to store indirection data. The distribution of pool allocate sizes is fixed. A pool allocate size is selected based upon an indirection system request size.
    Type: Application
    Filed: August 11, 2011
    Publication date: November 29, 2012
    Applicant: Hitachi Global Storage Technologies Netherlands B. V.
    Inventor: David Robison Hall
  • Publication number: 20120303922
    Abstract: A method and controller for implementing storage adapter performance optimization with enhanced resource pool allocation, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; a processor, and a plurality of resource pools. A plurality of work queues is associated with the resource pools. The processor initializes a list of types, and the associated amount of pages for each allocate type. The hardware engines maintain a count of allocate types, specifying a type on each allocation and deallocation, and performing allocation from the resource pools for deadlock avoidance.
    Type: Application
    Filed: May 24, 2011
    Publication date: November 29, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian E. Bakke, Brian L. Bowles, Michael J. Carnevale, Robert E. Galbraith, II, Adrian C. Gerhard, Murali N. Iyer, Daniel F. Moertl, Mark J. Moran, Gowrisankar Radhakrishnan, Rick A. Weckwerth, Donald J. Ziebarth
  • Publication number: 20120303917
    Abstract: A system includes a data collector, a plurality of data placement optimizers, a data placement arbitrator, and a data mover. The data collector is configured to collect system configuration data and system performance data. The plurality of data placement optimizers are each configured to analyze the system configuration data and the system performance data for developing a corresponding data movement plan. The data placement arbitrator is configured to arbitrate conflicts between at least two data movement plans of generated by the plurality of data placement optimizers to form an execution plan. The data mover is configured to perform the data movement plans according to the execution plan.
    Type: Application
    Filed: May 27, 2011
    Publication date: November 29, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence Y. CHIU, Yong GUO, Chao G. LI, Yang LIU, Paul MUENCH, Sangeetha SESHADRI
  • Patent number: 8321645
    Abstract: At least certain embodiments include a method, system and apparatus for relocating data between tiers of storage media in a hybrid storage aggregate encompassing multiple tiers of heterogeneous physical storage media including a file system to automatically relocate the data between tiers.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: November 27, 2012
    Assignee: NetApp, Inc.
    Inventors: Faramarz Rabii, John Strunk, Jeffrey S. Kimmel
  • Patent number: 8321651
    Abstract: Systems and methods for an improved memory allocation service in embedded or wireless devices. Memory is allocated using a combination of container memory items and referencing memory items.
    Type: Grant
    Filed: April 1, 2009
    Date of Patent: November 27, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Shailesh Maheshwari, Thomas Klingenbrunn, Vanitha Kumar
  • Patent number: 8321647
    Abstract: Multipage preparation commands for non-volatile memory systems are disclosed. The multipage preparation commands supply data that can be used to prepare a non-volatile memory device for forthcoming multipage program operations. A host controller can use the commands ahead of a multipage program operation to optimize usage of a multipage program command. The non-volatile memory device can use the commands to configure the non-volatile memory in preparation for a subsequent operation, such as changing a command order or using the most optimized command set for the subsequent operation.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: November 27, 2012
    Assignee: Apple Inc.
    Inventors: Vadim Khmelnitsky, Nir Jacob Wakrat, Tahoma Toelkes, Daniel Jeffrey Post, Anthony Fai
  • Patent number: 8321643
    Abstract: Replicated data storage units are autonomously identified and assembled into generationally related data storage volumes. A data storage manager, implementing a re-signaturing process executed at defined intervals or manually initiated on a server or client system connected to the storage area network, scans the collection of visible data storage units to identify those related as a data storage volume. Each replicated data storage unit includes metadata that embeds an identification of the replicated data storage unit and volume accessible to the data storage manager. To assemble a set of replicated data storage units into a generational volume, the data storage unit metadata is rewritten to establish a unique data storage volume identity including information to associate the data storage volume in a lineage with the source data storage volume.
    Type: Grant
    Filed: May 9, 2006
    Date of Patent: November 27, 2012
    Assignee: VMware, Inc.
    Inventors: Satyam B. Vaghani, Nikhil C. Jagtiani
  • Patent number: 8321641
    Abstract: A recording medium has a real data area built from a plurality of clusters and a fat (File Allocation Table) built from a plurality of entries showing usage conditions of the corresponding clusters. A control unit previously divides the fat into a plurality of blocks and creates, in RAM, a search table, at each block, showing presence or absence of an entry (unassigned entry) corresponding to an unassigned cluster. When data are written into the recording medium, the position of a block including an unassigned entry is located on the basis of the search table. Subsequently, the block is read in RAM, thereby locating the position of the unassigned cluster. Data are written in the thus-located cluster.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: November 27, 2012
    Assignee: TEAC Corporation
    Inventor: Hiroki Fukushima
  • Patent number: 8321622
    Abstract: The first controller includes a first relay circuit which is a circuit that controls data transfer, and a first processor coupled to the first relay circuit via a first second path. The second controller includes a second relay circuit which is a circuit that controls data transfer, and is coupled to the first relay circuit via the first path, and a second processor coupled to the second relay circuit via a second second path. The first processor is coupled to the second relay circuit not via the first relay circuit but via a first third path, and accesses the second relay circuit via the first third path during an I/O process. The second processor is coupled to the first relay circuit not via the second relay circuit but via a second third path, and accesses the first relay circuit via the second third path during an I/O process.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: November 27, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Shuji Nakamura, Emi Nakamura, legal representative, Masahiro Arai, Hideaki Fukuda, Nobuyuki Minowa
  • Publication number: 20120297159
    Abstract: System for controlling data transfer between a host system and storage devices. A virtualization controller implements the data transfer and includes first ports for connection with the storage devices, a second port for connection with the host system, a processor, and a memory configured to store volume mapping information which correlates first identification information used by the host system to access a first storage area in one of the storage devices, with second identification information for identifying the first storage area, the correlation being used by the processor to access the first storage area. When data stored in the first storage area is transferred to a second storage area, the processor correlates the first identification information with a third identification information for identifying the second storage area and registers the first identification information and the third identification information in the volume mapping information.
    Type: Application
    Filed: May 22, 2012
    Publication date: November 22, 2012
    Applicant: HITACHI, LTD.
    Inventors: Kiyoshi Honda, Naoko Iwami, Kazuyoshi Serizawa
  • Publication number: 20120297148
    Abstract: A transceiver is designed to share memory and processing power amongst a plurality of transmitter and/or receiver latency paths, in a communications transceiver that carries or supports multiple applications. For example, the transmitter and/or receiver latency paths of the transceiver can share an interleaver/deinterleaver memory. This allocation can be done based on the data rate, latency, BER, impulse noise protection requirements of the application, data or information being transported over each latency path, or in general any parameter associated with the communications system.
    Type: Application
    Filed: August 6, 2012
    Publication date: November 22, 2012
    Applicant: AWARE, INC.
    Inventors: Marcos C. Tzannes, Michael Lund
  • Publication number: 20120297160
    Abstract: Techniques for surface caching are described in which a cache for surfaces is provided to enable existing surfaces to be reused. Surfaces in the cache can be assigned to one of multiple surface lists used to service requests for surfaces. The multiple lists can include at least a main list and an auxiliary list configured to group existing surfaces according to corresponding surface constraints. When a surface is requested, the multiple lists can be searched to find an existing surface based on constraints including, for example, the type of surface and size requirements for the requested surface. If an existing surface is discovered, the existing surface can be returned to service the request. If a suitable surface is not found in the multiple lists, a new surface is created for the request and the new surface can be added to a corresponding one of the multiple surface lists.
    Type: Application
    Filed: June 8, 2011
    Publication date: November 22, 2012
    Applicant: Microsoft Corporation
    Inventors: Benjamin C. Constable, Brian E. Manthos, Li-Hsin Huang, Rafael V. Cintron, Samuel R. Fortiner, Jia Zhu
  • Publication number: 20120297156
    Abstract: A storage system comprising a first storage apparatus, a second storage apparatus, each storing data processed by an external apparatus, each of the first and second apparatuses including a pool of a plurality of unit physical storage areas for storing the data, the unit physical storage areas being classified into a plurality of storage tiers, a logical storage area in the first storage apparatus and the logical storage area in the second storage apparatus respectively including one or more of the storage tiers that are assigned to the respective logical storage areas, the storage system holding storage tier construction information of the first storage apparatus, and a data migration controller, when the data stored in the first storage apparatus are migrated to the second storage apparatus, transferring the storage tier construction information of the first storage apparatus to the second storage apparatus.
    Type: Application
    Filed: May 20, 2011
    Publication date: November 22, 2012
    Applicant: HITACHI, LTD.
    Inventors: Tomohiko Suzuki, Keiichi Tezuka, Akitatsu Harada
  • Publication number: 20120290812
    Abstract: Example embodiments for configuring a non-volatile memory device may comprise configuring M physical partitions of the non-volatile memory into two or more banks, wherein the two or more banks respectively comprise one or more of the M physical partitions, and wherein at least a first of the M physical partitions comprises a first size and wherein at least a second of the M physical partitions comprises a second size.
    Type: Application
    Filed: July 23, 2012
    Publication date: November 15, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Emanuele Confalonieri, Corrado Villa
  • Publication number: 20120290800
    Abstract: A method and apparatus for training read latency of a memory are disclosed. A memory controller includes a command FIFO configured to convey commands to a memory, a data queue coupled to receive data from the memory, and a register configured to provide a value indicative of a number of cycles of a first clock signal after which data is valid. During a startup routine, the memory controller is configured to compare data received by the data queue to a known data pattern after a specified number of cycles of the first clock signal have elapsed. The memory controller is further to configured to decrement the first value and repeat conveying and comparing if the data received matches the data pattern. If the received data does not match the data pattern for any attempted read of the memory, the memory controller is configured to program a second value into the register.
    Type: Application
    Filed: May 12, 2011
    Publication date: November 15, 2012
    Inventors: Guhan Krishnan, Jonathan M. Owen, Brian Amick, Hanwoo Cho
  • Publication number: 20120290809
    Abstract: A method and system for performing garbage collection involving sensitive information on a mobile device. Secure information is received at a mobile device over a wireless network. The sensitive information is extracted from the secure information. A software program operating on the mobile device uses an object to access the sensitive information. Secure garbage collection is performed upon the object after the object becomes unreachable.
    Type: Application
    Filed: July 24, 2012
    Publication date: November 15, 2012
    Applicant: Research In Motion Limited
    Inventors: Herbert A. Little, Neil P. Adams, Stefan E. Janhunen, John F.A. Dahms
  • Publication number: 20120290808
    Abstract: A method of multicast data transfer including accessing a source address to a source location of mapped memory which stores source data, accessing multiple destination addresses to corresponding destination locations of the mapped memory, and for each of at least one section of the source data, reading the section using the source address, storing the section into a local memory of a data transfer device, and writing the section from the local memory to each destination location in the mapped memory using the destination addresses. Separate source and destination attributes may be provided, so that the source and each destination may have different attributes for reading and storing data. The source and each destination may have any number of data buffers accessible by corresponding links provided in data structures supporting the data transfer. The source data may be divided into sections and handled section by section.
    Type: Application
    Filed: May 12, 2011
    Publication date: November 15, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Kun Xu, Tommi M. Jokinen, David B. Kramer
  • Publication number: 20120290804
    Abstract: This invention provides a storage system to store data used by computers. A storage system coupled to a computer and a management apparatus, includes storage devices accessed by the computer and a control unit that controls the storage devices, in which the control unit performs the following operations: setting, in the storage devices, a first virtual device including a first logical device; setting a second virtual device which including a second logical device, which is a virtual volume accessed by the computer; allocating an address of the first logical device to the second logical device; and changing the allocation to change storage areas of the virtual volume.
    Type: Application
    Filed: July 23, 2012
    Publication date: November 15, 2012
    Inventor: Yoshiaki EGUCHI
  • Publication number: 20120290810
    Abstract: Memory transactions that are issued just in time have deterministic response delay. By measuring an actual delay and comparing it to an expected delay a memory scheduler can determine whether it is issuing transaction requests too early and can thereby automatically adapt the issue of transaction requests by delaying future transaction requests to be just in time.
    Type: Application
    Filed: April 18, 2012
    Publication date: November 15, 2012
    Inventors: Jean-Jacques Lecler, Philippe Boucard, Jonah Proujansky-Bell
  • Patent number: 8312235
    Abstract: A data processing system includes a first storage system configured with a virtual logical volume that includes a dynamically expandable volume, a second storage system coupled to the first storage system through a data copy network, a host computer configured to input data to the virtual logical volume, and a management server coupled to the host computer, configured to manage the virtual logical volume.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: November 13, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Tsukasa Shibayama, Wataru Okada, Yukinori Sakashita, Yuri Hiraiwa, Masahide Sato
  • Patent number: 8312223
    Abstract: An approach is provided for pre-fetching of virtual content in a virtual universe based on previous traversals. In one embodiment, there is a pre-fetching tool, including a ranking component configured to rank each of a plurality of parcels of locations previously visited by an avatar according to predefined ranking criteria. The pre-fetching tool further includes a pre-fetching component configured to pre-fetch a virtual content of said parcels of locations based on the ranking.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: November 13, 2012
    Assignee: International Business Machines Corporation
    Inventors: Rosa M. Bolger, Ann Corrao, Rick A. Hamilton, II, Brian M. O'Connell, Brian J. Snitzer
  • Patent number: 8312204
    Abstract: The present disclosure provides a system and method for wear leveling. In one example, the method includes receiving first data to be stored to a first data storage medium and storing the first data to a first storage location in a nonvolatile data store of a second data storage medium comprising a solid-state memory. The method also includes setting a pointer to enable writing second data that is received to a next storage location in the nonvolatile data store. The next storage location comprises an address of the nonvolatile data store that is sequentially after an address of the first storage location. When the address of the first storage location is a last addressed location of the nonvolatile data store the pointer is set to enable writing the second data to a first addressed location of the nonvolatile data store.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: November 13, 2012
    Assignee: Seagate Technology LLC
    Inventors: Fumin Zhang, Chris Malakapalli
  • Publication number: 20120284482
    Abstract: Embodiments disclosed include methods and systems for reusing labels for connected component labeling including assigning one or more labels to one or more groups of raw data representing one or more regions by designating one or more data structures as containing information about the one or more regions; connecting the one or more labels determined to be related; choosing a root label for the connected one or more labels, the root label determined by locating an earliest data element from the one or more groups of raw data; altering a label list of the one or more labels, the label list altered by flagging the root label to include a region label index; and overwriting one or more region label indexes according to the root label.
    Type: Application
    Filed: July 18, 2012
    Publication date: November 8, 2012
    Inventor: Craig Sullender
  • Publication number: 20120284483
    Abstract: Allocation of pages of memory is managed in computing environments that include multiple sized memory pools. Responsive to a request for a page of memory, one or more memory pools are searched for an available frame of memory to service the request. The search uses a predefined order of search, which includes multiple types of memory pools in a specific order based on the requested size of the page of memory.
    Type: Application
    Filed: May 5, 2011
    Publication date: November 8, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alfred F. Foster, David Hom, Charles E. Mari, Matthew J. Mauriello, Robert Miller, JR., Mariama Ndoye, Michael G. Spiegel, Peter G. Sutton, Scott B. Tuttle, Elpida Tzortzatos, Chun Kwan K. Yee
  • Publication number: 20120284478
    Abstract: Auxiliary storage is segmented into different types of extents (i.e., ranges of storage), including extents with 4K blocks of storage, extents with 1M blocks of storage, empty extents, and mixed extents that include blocks of storage of various sizes (e.g., 4K blocks and 1M blocks). The auxiliary storage, and in particular, the extents and blocks of storage therein, are managed to reduce storage fragmentation and optimize system performance.
    Type: Application
    Filed: May 5, 2011
    Publication date: November 8, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher G. Brooker, Alfred F. Foster, Duane C. Hughes, Charles E. Mari, Robert Miller, JR., Harris M. Morgenstern, Walter W. Otto, Steven M. Partlow, Thomas F. Rankin, Elpida Tzortzatos
  • Publication number: 20120284484
    Abstract: A mechanism, in a data processing system, is provided for logical partition defragmentation. The mechanism gathers resource requirements for a plurality of logical partitions running in a plurality of power domains within one or more servers. The mechanism determines optimal hardware utilization for the plurality of logical partitions. The mechanism migrates one or more of the plurality of logical partitions to run in a subset of the plurality of power domains such that at least one power domain within the plurality of power domains is unused. The mechanism puts the at least one unused power domain in a low power state.
    Type: Application
    Filed: April 30, 2012
    Publication date: November 8, 2012
    Applicant: International Business Machines Corporation
    Inventors: Anis M. Abdul, Nicholas E. Bofferding, Ajay K. Mahajan, Rashmi Narasimhan
  • Publication number: 20120284479
    Abstract: Large page memory pools are managed. Thresholds are used to determine if the number of pages in a large page memory pool is to be adjusted. If the number of pages is to be increased, a particular technique is provided for adding additional pages to the pool. Further, if there are too many pages in the pool, one or more pages may be removed.
    Type: Application
    Filed: May 5, 2011
    Publication date: November 8, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alfred F. Foster, David Hom, Charles E. Mari, Matthew J. Mauriello, Robert Miller, JR., Mariama Ndoye, Michael G. Spiegel, Peter G. Sutton, Scott B. Tuttle, Elpida Tzortzatos, Chun-Kwan K. Yee
  • Publication number: 20120284476
    Abstract: A storage controller having a plurality of storage devices and a control circuit providing a plurality of virtual volumes, to each of which a storage area in a plurality of pool volumes provided with the plurality of storage devices can be mapped for writing data in response to a write access sent from an information processing apparatus to a logical area in one of the plurality of virtual volumes, respectively. The control circuit, according to a search of the plurality of pool volumes for a certain storage area in which a certain data pattern is written, releases the certain storage area from mapping to a logical area in the plurality of virtual volumes, so that the control circuit can use the released certain storage area for mapping to a virtual volume of the plurality of virtual volumes as a destination of another write access from the information processing apparatus.
    Type: Application
    Filed: June 21, 2012
    Publication date: November 8, 2012
    Applicant: HITACHI, LTD.
    Inventors: Toshiya Seki, Eiju Katsuragi, Takashi Sakaguchi
  • Publication number: 20120284480
    Abstract: A memory system includes a memory controller and a memory module coupled to the memory controller. One such memory module may include a memory package of a first type and a signal presence detect unit configured to provide configuration data associated with a memory package of a second type to the memory controller. The configuration data may be used to configure the memory controller to interface with the memory package of a first type.
    Type: Application
    Filed: February 15, 2012
    Publication date: November 8, 2012
    Applicant: Micron Technology, Inc.
    Inventors: Brett L. Williams, Thomas H Kinsley
  • Publication number: 20120284473
    Abstract: A memory storage device and a memory controller and an access method thereof are provided. The memory storage device includes a rewritable non-volatile memory chip having a plurality of physical blocks. The access method includes configuring a plurality of logical blocks to be mapped to a part of the physical blocks and dividing the logical blocks into at least a first partition and a second partition, wherein the first partition records an auto-execute file. The access method also includes determining whether a trigger signal is existent and sending a media ready message to a host system if the trigger signal is existent, so as to allow the host system to automatically run the auto-execute file and receive a first password. The access method further includes determining whether to provide the logical blocks in the second partition to the host system according to the first password received from the host system.
    Type: Application
    Filed: June 28, 2011
    Publication date: November 8, 2012
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chia-Jung Hsu, Shih-Hsien Hsu
  • Publication number: 20120284470
    Abstract: Semiconductor memory device with high-speed data transmission capability, system having the same includes a plurality of address input circuits and a plurality of data output circuits and a training driver configured to distribute address information input through the plurality of address input circuits together with a data loading signal for a read training, and generate data training patterns to be output through the plurality of data output circuits.
    Type: Application
    Filed: July 12, 2012
    Publication date: November 8, 2012
    Inventors: Ji-Hyae Bae, Sang-Sik Yoon, Ki-Chang Kwean
  • Publication number: 20120284474
    Abstract: In defragmentation of data of a data storage system, the data storage system having at least one storage control and data storage, allowing defragmentation of data with respect to the data storage, the defragmentation comprising analysis and data movement. During the defragmentation and before completion of the defragmentation, in response to the data movement reaching a stable state, further defragmentation analysis and data movement is interrupted; making a point-in-time copy of the data subject to the defragmentation; and resuming the defragmentation analysis and data movement. At a further stable state where a new point-in-time copy is made, an earlier point-in-time copy is withdrawn. Should the defragmentation process end prematurely, a backup of the data subject to defragmentation may be recovered from a most recent point-in-time copy.
    Type: Application
    Filed: May 6, 2011
    Publication date: November 8, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: DOUGLAS L. LEHR, FRANKLIN E. McCUNE, DAVID C. REED, MAX D. SMITH
  • Publication number: 20120284475
    Abstract: A memory controller for managing data and power in a memory is described. In some implementations, the memory controller is configured to identify a first area of the memory to be operated at a first power level, identify a second area of the memory to be operated at a second power level, transfer data in a region in the second area to a region in the first area, maintain a mapping of an address associated with the region in the second area to an address associated with the region in the first area, operate the first area at the first power level, and operate the second area at the second power level.
    Type: Application
    Filed: May 4, 2012
    Publication date: November 8, 2012
    Inventor: Ofer Zaarur
  • Patent number: 8307186
    Abstract: The management system identifies a server level virtual volume corresponding to a storage level pool on the basis of storage management information and server management information, and displays information relating to the correspondence between the storage level pool and the server level virtual volume. The storage management information represents correspondence between a storage level virtual volume to which a portion of an area is allocated from the storage level pool by thin provisioning technology at the storage level, and the storage level pool. The server management information represents correspondence between a server level virtual volume to which a portion of an area is allocated from the storage level virtual volume belonging to a server level pool by thin provisioning technology at the server level, and the storage level virtual volume.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: November 6, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Nobuhiko Ando, Takato Kusama, Nobuo Beniyama, Yoshiki Fukui, Katsutoshi Asaki
  • Patent number: 8307174
    Abstract: This invention is a system and method for managing sessions and memory resources used for replication of data in a data storage environment. In one embodiment, a methodology is provided that inspecting a plurality of copy sessions forming a copy session group operating in the data storage environment to determine the size and number of buffers each session is using, and determining whether to abort a session of the group and reallocate its buffers by redistributing its memory for use by itself and another session based on the inspection. In other embodiments, implementations include a system, a computer program product, or an apparatus, wherein each embodiment is configured for carrying out the steps involved in the methodology.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: November 6, 2012
    Assignee: EMC Corporation
    Inventors: Pawan Misra, Michael D. Haynes, Chetan Rameshchandra Vaidya, Somnath Gulve
  • Patent number: 8307153
    Abstract: A network device allocates a number of blocks of memory in a ternary content-addressable memory (TCAM) of the network device to each database of multiple databases, and assigns unused blocks of memory of the TCAM to a free pool. The network device also detects execution of a run mechanism by the TCAM, and allocates, based on the execution of the run mechanism, one of the unused blocks of memory to a filter or rule of one of the multiple databases.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: November 6, 2012
    Assignee: Juniper Networks, Inc.
    Inventor: Salem Nanda Kishore
  • Patent number: 8307177
    Abstract: Described in detail herein is a method of copying data of one or more virtual machines being hosted by one or more non-virtual machines. The method includes receiving an indication that specifies how to perform a copy of data of one or more virtual machines hosted by one or more virtual machine hosts. The method may include determining whether the one or more virtual machines are managed by a virtual machine manager that manages or facilitates management of the virtual machines. If so, the virtual machine manager is dynamically queried to automatically determine the virtual machines that it manages or that it facilitates management of. If not, a virtual machine host is dynamically queried to automatically determine the virtual machines that it hosts. The data of each virtual machine is then copied according to the specifications of the received indication.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: November 6, 2012
    Assignee: CommVault Systems, Inc.
    Inventors: Anand Prahlad, Rahul S. Pawar, Prakash Varadharajan, Pavan Kumar Reddy Bedadala
  • Publication number: 20120278572
    Abstract: A method, including configuring data migration from a first volume to a second volume, which are coupled via a storage area network (SAN) to a host computer, with the first volume mapped to the host computer. A volume identifier associated with the first volume is copied to a memory coupled to the second volume, and the copied volume identifier is retrieved from the memory by the host computer. A state of the second volume is to inactive, and the inactive second volume is mapped to the host computer. A state of the first volume is set to inactive, and the status is data from the inactive first volume to the inactive second volume. After the copying, data migration is started from the inactive first volume to the inactive second volume, and after the starting, the state of the second volume is set to active.
    Type: Application
    Filed: June 26, 2012
    Publication date: November 1, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yakov BROIDO, Daniel I. GOODMAN, Haim HELMAN, Leonid KULL, Orit NISSAN-MESSING, Guy ROZENDORN
  • Publication number: 20120278579
    Abstract: Method and apparatus for self-initiated secure erasure of data from a non-volatile memory, such as a solid state drive (SSD). In accordance with various embodiments, the memory is operated in communication with a host device. A self-initiated, non-destructive secure erasure of the data stored in the memory is carried out responsive to a detection of an unauthorized power down event associated with the memory.
    Type: Application
    Filed: April 29, 2011
    Publication date: November 1, 2012
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Ryan James Goss, David Scott Seekins