Abstract: Aspects of the subject matter described herein relate to querying and repairing data. In aspects, a component may detect that data on storage has become corrupted. In response, the component may request data from one or more redundant copies of the data and may determine which of the redundant copies, if any, are not corrupted. If a non-corrupted copy is found, the component may send a request that the corrupted data be repaired and may identify the non-corrupted copy to use to repair the corrupted data.

Abstract: A method of operation of a non-volatile memory system includes: generating a test stimulus for a page in a memory array; measuring a test response from the page in the memory array based on the test stimulus; calculating a measured effective life of the page from the test response; and determining a use plan according to the measured effective life for accessing the page.

Abstract: For facilitating data verification using a checksum in conjunction with a sidefile by a processor device in a computing environment, first block signatures having a first size are calculated for first blocks of a first volume stored on a storage device. The first block signatures are stored to a sidefile. Second block signatures having a second size different from the first size are calculated for second blocks of a second volume stored on the storage device. The second block signatures are stored to the sidefile.

Abstract: A method of copying data includes receiving a command instructing copying of data from a source location in the memory die to a destination location in the memory die. The method includes determining if a criterion is met, including comparing a predefined parameter to a dynamic threshold. In response to determining that the criterion is met, the method includes executing the copying by moving the data from the source location in the memory die to the controller die and, after moving the data to the controller die, moving an error-corrected version of the data from the controller die to the destination location in the memory die. In response to determining that the criterion is not met, the method includes executing the copying by moving the data inside the memory die source location to the destination location without moving the data to the controller die.

Abstract: The disclosed fault analysis rule extraction device includes: an event preprocessing section and a fault analysis rule extraction section. The event preprocessing section merges, with respect to event groups each of which is grouped every certain time period, event groups that can be presumed to occur from the same fault by a cluster analysis. The fault analysis rule extraction section extracts a fault analysis rule useful for a fault analysis by relating event logs to clusters. By the fault analysis rule extraction device of the above configuration, highly accurate fault analysis rule are automatically provided from the event logs of a system.

Abstract: A malfunction analysis apparatus (100) is provided with a malfunction-analysis processor (107), an attribute-extraction processor (108), and an outputter (105). The malfunction-analysis processor (107) obtains a malfunction-contribution degree, which indicates a degree that individual malfunctions (to be called malfunctioning elements, hereafter) contribute to the malfunctioning of the object being analyzed, on the basis of the relative relationship between the data to be analyzed that has, as elements thereof, values generated on the basis of a plurality of indicator values of the object being analyzed, and representative values for the plurality of indicators corresponding to each of the plurality of malfunctions. Then, the malfunctioning elements being generated is specified, on the basis of the obtained malfunction-contribution degree.

Abstract: A post-write read operation, using a combined verification of multiple pages of data, is presented. In a simultaneous verification of multiple pages in a block, the controller evaluates a combined function of the multiple pages, instead of evaluating each page separately. In one exemplary embodiment, the combined function is formed by XORing the pages together. Such a combined verification of multiple pages based on the read data can significantly reduce the controller involvement, lowering the required bus and ECC bandwidth for a post-write read and hence allow efficient post-write reads when the number of dies is large.

Abstract: A method begins by a dispersed storage (DS) processing module identifying a performance anomaly within a dispersed storage network (DSN). The method continues with the DS processing module identifying a set of collections of records corresponding to the performance anomaly, wherein one of the set of collections of records includes an event record including information regarding an event, a first record including information regarding a dispersed storage (DS) processing module processing an event request to produce a plurality of sub-event requests, and a plurality of records including information regarding a set of DS units processing the plurality of sub-event requests. The method continues with the DS processing module determining whether a reliable significance indication of the performance anomaly is determinable, and when the reliable significance indication of the performance anomaly is not determinable, modifying data collection criteria for one or more of the sets collections of records.

Abstract: Techniques involving replication of virtual machines at a target site are described. One representative technique includes an apparatus including a virtual machine configured to provide storage access requests targeting a virtual disk. A storage request processing module is coupled to the virtual machine to receive the storage access requests and update the virtual disk as directed by the storage access requests. A replication management module is coupled to the virtual machine to receive the storage access requests in parallel with the storage request processing module, and to store information associated with the storage access requests in a log file(s). The log file may be transferred to a destination as a recovery replica of at least a portion of the virtual disk.

Abstract: The present invention provides a data processing method, a data processing system and a receiver. The method includes: performing optical-to-electrical conversion processing on a received current optical data signal, to generate a current electric data signal; performing analog-digital conversion processing on the current electric data signal, to generate a current data block; performing equalization processing on the current data block according to a previous second output data block, to generate a current first output data block, where the previous second output data block is generated by performing forward error correction decoding processing on a previous first output data block, and the previous first output data block is generated by performing equalization processing on a previous data block of the current data block; and performing forward error correction decoding processing on the current first output data block, to generate a current second output data block.

Abstract: Correction data units for data packets of a data stream are generated. A correction data unit is based on a set of the data packets of the stream. The stream is transmitted over a lossy communication channel. A performance measure to be optimized is selected, which relates to the recovery of lost data packets of the stream. A coding requirement is determined. For the generation of the correction data units, it is determined, within the constraints of the coding requirement and based on previously generated correction data units, which of the data packets in the stream to include in the set on which the generation of the correction data unit is to be based to thereby optimize the selected performance measure. A generated correction data unit is generated based on a respective set of the data packets of the stream. The generated correction data units are included in the stream.

Abstract: The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes mirroring programming operations such that data associated with a programming operation is programmed to two or more locations in memory of the solid state drive. The method also includes ceasing to mirror programming operations upon an occurrence of a particular event.

Abstract: In one implementation, a memory device includes non-volatile memory, a memory controller communicatively coupled to the non-volatile memory over a first bus, and a host interface through which the memory controller communicates with a host device over a second bus. The memory device can also include a signal conditioner of the host interface adapted to condition signals to adjust a signal level of signals received over the second bus based on signal level data received from the host device, wherein the signal level data relates to a voltage level of signals generated by the host device to encode data transmitted across the second bus.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. A data processing circuit is disclosed that includes: a data detector circuit, a first symbol constrained arrangement circuit, and a second symbol constrained arrangement circuit. The data detector circuit is operable to apply a data detection algorithm to a combination of a first input data set and a decoded data set to yield a detected output that includes a number of non-binary symbols. The first symbol constrained arrangement circuit is operable to receive the detected output and to re-arrange the detected output in accordance with a first arrangement algorithm to yield a re-arranged output. The bits for at least one non-binary symbol from the detected output are maintained together in the re-arranged output.

Abstract: A dispersed storage device for use within a dispersed storage network operates to select a set of dispersed storage units for storage of a data object by slicing an encoded data segment of a data object into error coded data slices, determining slice metadata for the error coded data slices, determining memory characteristics of dispersed storage units capable of storing the error coded data slices and selecting the set of dispersed storage units for storing the error coded data slices based on the slice metadata and the memory characteristics.

Abstract: An apparatus, system, and method are disclosed for managing data in a solid-state storage device. A solid-state storage and solid-state controller are included. The solid-state storage controller includes a write data pipeline and a read data pipeline The write data pipeline includes a packetizer and an ECC generator. The packetizer receives a data segment and creates one or more data packets sized for the solid-state storage. The ECC generator generates one or more error-correcting codes (“ECC”) for the data packets received from the packetizer. The read data pipeline includes an ECC correction module, a depacketizer, and an alignment module. The ECC correction module reads a data packet from solid-state storage, determines if a data error exists using corresponding ECC and corrects errors. The depacketizer checks and removes one or more packet headers. The alignment module removes unwanted data, and re-formats the data as data segments of an object.

Abstract: A secondary location of a network acts as a recovery network for a primary location of the service. The secondary location is maintained in a warm state that is configured to replace the primary location in a case of a failover. During normal operation, the primary location actively services user load and performs backups that include full backups, incremental backups and transaction logs that are automatically replicated to the secondary location. Information is stored (e.g. time, retry count) that may be used to assist in determining when the backups are restored correctly at the secondary location. The backups are restored and the transaction logs are replayed at the secondary location to reflect changes (content and administrative) that are made to the primary location. After failover to the secondary location, the secondary location becomes the primary location and begins to actively service the user load.

Abstract: Subject matter disclosed herein relates to determining that a portion of a memory is at least partially non-functional, replacing the portion of at least partially non-functional memory; and adjusting an error detection and/or correction process responsive to determining that the portion of the memory is at least partially non-functional and/or replacing the portion of at least partially non-functional memory.

Abstract: A wireless device for implementing Incremental Redundancy (IR) operations includes system processing circuitry operable to perform Physical (PHY) layer operations, Media Access Control (MAC) layer operations and Radio Link Control (RLC) operations of the wireless device. The system processing circuitry further includes an IR control module for processing IR transactions related to a received RLC data block and for tracking an Automatic Repeat Request (ARQ) receiving state and received block bit map and a Layer 1 (L1) module for intercepting and diverting the IR transactions to the IR control module and for passing a correctly decoded RLC data block to the RLC layer operations via the MAC layer operations thereby automatically synchronizing the RLC layer operations. An IR processing module is coupled to the system processing circuitry to perform IR operations on the received RLC data block based upon a direction from the IR control module.

Abstract: A method for data storage includes defining a set of scrambling sequences, each sequence including bits in respective bit positions having bit values, such that a distribution of the bit values in any give bit position satisfies a predefined statistical criterion. Each data word is scrambled using a respective scrambling sequence selected from the set. The scrambled data words are stored in the memory device.

Abstract: In described embodiments, a transceiver supports two or more rates using an oversampling clock and data recovery (CDR) circuit sampling high rate data with a predetermined CDR sampling clock. A timing recovery circuit detects and accounts for extra or missing samples when oversampling lower rate data. An edge detector detects each actual data symbol edge and provides for an edge decision offset in a current instant's block of samples. An edge error is generated from the previous instant's actual and calculated edges; and an edge distance between actual edges of the current and previous instants is generated. Filtered edge distance and error are combined to generate a calculated edge position for the data symbol edge for the current instant. The edge decision offset is applied to the current calculated edge position to identify a sample value to generate a decision for the data symbol to detect the current data value.

Abstract: A packet transmission apparatus to transmit a packet limited in arrival deadline through a best-effort network includes a packet automatic retransmission section to control retransmission of an undelivered packet, a forward error correction coding section to add redundant packet to a data packet block, and a redundancy determining section to dynamically determine redundancy of the redundant packet based on observed network state information so that a loss rate after error correction at a receiver achieved by only the retransmission of the undelivered packet satisfies an allowable loss rate after error correction.

Abstract: A method for computer system recovery is presented. In one embodiment, the method includes establishing a connection, via an interface, to a computer system to support the system recovery of the computer system. The method includes executing an emulation application as a recovery agent. The method includes retrieving, based on identifiers associated with the computer system, remote data via another interface. The method further includes performing the system recovery by using at least a part of the remote data.

Abstract: A memory controller including a detection module and a protection module is provided. The memory controller is applicable to a memory having a command transmission port and a data transmission port. The detection module detects whether an error condition occurs in an electronic device associated with the memory. When the error condition is detected, the protection module sends an interrupt command to the memory via the command transmission port to stop an operation associated with the data transmission port.

Abstract: A data management system (“DMS”) provides an automated, continuous, real-time, substantially no downtime data protection service to one or more data sources. A host driver embedded in an application server captures real-time data transactions, preferably in the form of an event journal. The driver functions to translate traditional file/database/block I/O and the like into a continuous, application-aware, output data stream. The host driver includes an event processor that can perform a recovery operation to an entire data source or a subset of the data source using former point-in-time data in the DMS. The recovery operation may have two phases. First, the structure of the host data in primary storage is recovered to the intended recovering point-in-time. Thereafter, the actual data itself is recovered. The event processor enables such data recovery in an on-demand manner, by allowing recovery to happen simultaneously while an application accesses and updates the recovering data.

Abstract: Techniques are presented for dynamically optimizing the performance of the controller-memory (or “back-end”) interface of a non-volatile memory system. Memory systems are usually designed to have a certain amount of error tolerance for error that can then be corrected by ECC. In may circumstances, such as when a device is new, the ECC capabilities of the system exceed what is needed to correct data storage errors. In these circumstances the memory system internally allots a non-zero portion of this error correction capacity to the back-end interface. This allows for the interface to operate at, for example, higher speed or lower power, even though this will likely lead to transmission path error. The system can also calibrate the back-end interface to determine that amount of error that result from various operating conditions, allowing the operating parameters of the back-end interface to be set according to amount of error that is allotted to the transfer process.

Abstract: Apparatus and methods for selective decoding of received code blocks are disclosed. An example method includes receiving a code block, determining a code block quality indicator for the received code block, and attempting to decode the received code block if the code block quality indicator is greater than or equal to a threshold. If the code block quality indicator is less than the threshold, the received code block is discarded without decoding attempts. The threshold may be a static or dynamic threshold.

Abstract: In an encrypted wireless system, when a wireless node detects that it is having problems, it may be programmed to transmit one or more diagnostic messages without encryption, or with reduced encryption. The transmitted diagnostic messages may be received and interpreted by a technician troubleshooting the system. Once the technician troubleshoots and repairs the system, the affected wireless node may detect that it is operating normally, and may cease transmitting the unencrypted, or reduced-encryption, diagnostic messages. In most cases, the wireless system does not need any particular input to initiate the unencrypted, or reduced-encryption, diagnostic message transmissions.

Abstract: Data storage techniques and solutions simultaneously provide efficient random access to information and high noise resilience. The amount of storage space utilized is only slightly larger than the size of the data. The solution is based on locally decodable error-correcting codes (also referred to as locally decodable codes or LDCs). Locally decodable codes are described herein that are more efficient than conventional locally decodable codes. Such locally decodable codes are referred to as “multiplicity codes”. These codes are based on evaluating multivariate polynomials and their derivatives. Multiplicity codes extend traditional multivariate polynomial based (e.g., Reed-Muller) codes. Multiplicity codes inherit the local decodability of Reed-Muller codes, and at the same time achieve substantially better parameters.

Abstract: A method for protecting the integrity of a set of memory pages to be accessed by an operating system of a data processing system, includes running the operating system in a virtual machine (VM) of the data processing system; verifying the integrity of the set of memory pages on loading of pages in the set to a memory of the data processing system for access by the operating system; in response to verification of the integrity, designating the set of memory pages as trusted pages and, in a page table to be used by the operating system during the access, marking non-trusted pages as paged; and in response to a subsequent page fault interrupt for a non-trusted page, remapping the set of pages to a region of the data processing system memory which is inaccessible to the virtual machine.

Abstract: A method of transmitting data in a wireless access system includes: calculating a number C of code blocks using a size B of an input bit sequence, a maximum size Z of the code blocks, and a size L of a cyclic redundancy check (CRC) which is to be attached to each of the code blocks; calculating a size B? of a modified input bit sequence using the number C, the size L, and the size B; obtaining a size K of each of the code blocks using the size B? and the number C; segmenting the input bit sequence to have the number C of the code blocks and the obtained size K of each of the code blocks; generating the code blocks by attaching the CRC to each of the segmented input bit sequences; and channel-coding the code blocks.

Abstract: A solid state storage device includes a flash memory and a controller configured to store data in the flash memory via a plurality of channels. The stored data is encoded using a low-density parity-check code. Hard-decision decoders are configured to decode encoded data received from the flash memory via respective channels of the plurality of channels using the low-density parity-check code and to provide decoded data to the controller in response to one or more read commands from the controller. A soft-decision decoder is configured to decode the encoded data received from the flash memory using the low-density parity-check code and to provide the decoded data to the controller in response to one of the plurality of hard-decision decoders failing to decode the encoded data. The encoded data is obtained by the soft-decision decoder using a plurality of read-retry operations.

Abstract: According to an embodiment, an encoder has a storage and a generator. The storage stores information indicative of a generator matrix corresponding to a partial parity check matrix in a rank-deficient parity check matrix including a lower triangular matrix and one or more cyclic matrices or zero matrices, the partial parity check matrix including rows different from rows of the lower triangular matrix. The generator carries out semi-systematic coding using the generator matrix to generate a portion of code word. The generator matrix has a cyclic matrix portion with one or more cyclic matrices and a non-cyclic matrix portion with rows number of which is equal to a degree of rank deficiency in the partial parity check matrix.

Abstract: A method and system for managing storage of one or more data blocks in a programmable data storage device is provided. A data storage controller partitions each of multiple data blocks into multiple sub data blocks comprising a number of bits based on one or more index value descriptors. The data storage controller generates transition vectors from each of the sub data blocks by applying one or more transition functions. The data storage controller encodes one of the transition vectors for each sub data block for obtaining a residual sub data block comprising a reduced number of bits, thereby resulting in increased bit space. The data storage controller generates a composite data block by merging each residual sub data block. The composite data block is configurable for writing to one or more regions in the programmable data storage device free from a disturbance caused by write operations to other regions.

Abstract: Several different embodiments of a segmented object storage system are described. The object storage system divides files into a number of object segments, each segment corresponding to a portion of the object, and stores each segment individually in the cloud storage system. The system also generates and stores a manifest file describing the relationship of the various segments to the original data file. Requests to retrieve the segmented file are fulfilled by consulting the manifest file and using the information from the manifest to reconstitute the original data file from the constituent segments. Modifying, appending to, or truncating the object is accomplished by manipulating individual segments and the manifest file. In further embodiments, manipulation of the individual object segments and/or the manifest is used to implement copy-on-write, snapshotting, software transactional memory, and peer-to-peer transmission of the large file.

Abstract: A method is provided for managing errors in a virtualized information handling system that includes an error detection system and a hypervisor allowing multiple virtual machines to run on the information handling system. The hypervisor may assign at least one memory region to each of multiple virtual machines. The error detection system may detect an error, determine a physical memory address associated with the error, and report that address to the hypervisor. Additionally, the hypervisor may determine whether the memory region assigned to each virtual machine includes the physical memory address associated with the error. The hypervisor may shut down each virtual machine for which a memory region assigned to that virtual machine includes the physical memory address associated with the error, and not shut down each virtual machine for which the memory regions assigned to that virtual machine do not include the physical memory address associated with the error.

Abstract: A duplicate-aware disk array (DADA) leaves duplicated content on the disk array largely unmodified, instead of removing duplicated content, and then uses these duplicates to improve system performance, reliability, and availability of the disk array. Several implementations disclosed herein are directed to the selection of one duplicate from among a plurality of duplicates to act as the proxy for the other duplicates found in the disk array. Certain implementations disclosed herein are directed to scrubbing latent sector errors (LSEs) on duplicate-aware disk arrays. Other implementations are directed to disk reconstruction/recovery on duplicate-aware disk arrays. Yet other implementations are directed to load balancing on duplicate-aware disk arrays.

Abstract: A method and system for redundancy management is provided for a distributed and recoverable digital control system. The method uses unique redundancy management techniques to achieve recovery and restoration of redundant elements to full operation in an asynchronous environment. The system includes a first computing unit comprising a pair of redundant computational lanes for generating redundant control commands. One or more internal monitors detect data errors in the control commands, and provide a recovery trigger to the first computing unit. A second redundant computing unit provides the same features as the first computing unit. A first actuator control unit is configured to provide blending and monitoring of the control commands from the first and second computing units, and to provide a recovery trigger to each of the first and second computing units. A second actuator control unit provides the same features as the first actuator control unit.

Abstract: According to one embodiment, a command generator sequentially and speculatively issues channel-by-channel access commands to a memory interface in a predetermined access process. A purger returns a series of unexecuted already-issued access commands using a purge response if an error occurs in any of memory accesses via a plurality of channels. A command progress manager updates command progress information such that the command progress on each of the plurality of channels returns to a position specified in an oldest access command of a series of the returned access commands issued to the channel. The command generator issues the channel-by-channel access commands including the oldest access command to the memory interface based on the updated command progress information.

Abstract: A method for managing kernel interface-based discrepancies may include finding a software package having a first version of a kernel package, and retrieving a first kernel interface information from a first file within the kernel package. The first kernel interface information relates to kernel interfaces associated with the kernel package, wherein the interfaces include kernel application binary interface (kABI). The method may further include forming a first dataset including the first kernel interface information relating to the first version of the kernel package, and detecting kernel discrepancies by comparing the first dataset with a second dataset relating to a second version of the kernel package.

Abstract: By using a processor to share certain burdens originally handled by a controller of a nonvolatile memory module, the controller is able to process more complicated procedures. The procedures include an error correction code generating procedure, a data scrambling procedure, a data recovery procedure, an address translation procedure configured to translate a logical address into a physical address, and a wear leveling procedure.

Abstract: The present disclosure provides a controller which comprises a command generator configured to generate a command to non volatile memory, and buffer configured to receive a first data and a second data and configured to combine the first data and the second data, an ECC unit configured to perform the ECC decoding. And the first page data may include at least one error bit corresponding to an error location table and the second page data may include at least one original bit which can be replaced with the error bit. The buffer may replace the at least one error bit with the said at least one original bit. The error location table may save information of location for the repeated error bit.

Abstract: System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory “nest” (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switch or a bus.

Abstract: Data can be encoded by assigning source symbols to base blocks, assigning base blocks to source blocks and encoding each source block into encoding symbols, where at least one pair of source blocks is such they have at least one base block in common with both source blocks of the pair and at least one base block not in common with the other source block of the pair. The encoding of a source block can be independent of content of other source blocks. Decoding to recover all of a desired set of the original source symbols can be done from a set of encoding symbols from a plurality of source blocks wherein the amount of encoding symbols from the first source block is less than the amount of source data in the first source block and likewise for the second source block.

Abstract: A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.

Abstract: In general, techniques are described for enabling a restartable file system. A computing device comprising a processor that executes an operating system may implement the techniques. The processor executes kernel and file system functions of the operating system to perform an operation, where both types of functions call each other to perform the operation. The operating system stores data identifying those of the kernel functions that called the file system functions. In response to determining that one of the file system functions that was called has failed, the operating system accesses the data to identify one of the kernel functions that most recently called one of the file system functions, and returns control to the identified one of the kernel functions without executing any of the file system functions called after the identified one of the kernel functions and prior to the one of the file system functions that failed.

Abstract: The present application relates to a data bus system, its encoder/decoder and encoding/decoding method.

Abstract: Decoding data received includes decoding the received data using a first error correcting circuitry that decodes data in accordance with a first decoding process, terminating execution of the first decoding process used to correct the data before the first error correcting circuitry completes executing the first, decoding process and outputting partially decoded data, determining whether partially decoded data requires further decoding, and in response to determining whether partially decoded data requires further decoding, decoding the partially decoded data using a second error correcting circuitry that decodes data in accordance with a second decoding process. A system decodes data in accordance with the method.

Abstract: A phase-change memory (PCM) includes a matrix of storage cells, including at least a first group with at least one cell. Each cell includes a phase change material having at least a first resistance value and a second resistance value, such that the first group can have an identical message encoded therein in at least a first way and a second way. The memory also includes a controller configured to encode the identical message in the at least first group the first or second way, based on which way causes the least amount of writing cost, given current levels of the group. Another embodiment of memory includes a matrix of storage cells. Each of the storage cells has at least two levels, such that each of the storage cells can have an identical message encoded therein in at least a first way and a second way.

Abstract: A storage apparatus and response time control method capable of preventing response performance deterioration effectively are suggested. Since a response time control unit which delays a response of a corresponding storage device to a command and transfers it to a controller for a storage apparatus is located between the controller and part of or all storage devices in order to equalize response time for the plurality of storage devices to respond to a command issued from the controller, it is possible to equalize the response time of the plurality of storage devices and thereby effectively prevent deterioration of the response performance of the storage apparatus.