Abstract: The present invention is related to systems and methods for maintaining additional processing information during extended delay processing.

Abstract: Fault-tolerant storage is provided using a distributed data storage system that receives input data from clients and divides that data into data blocks for storage. The data blocks are processed using a coding scheme that generates redundant level one error correction blocks (L1EC Blocks). The L1EC blocks enable the reconstruction of one or more damaged or inaccessible data blocks, so long as sufficient undamaged elements are still accessible. The L1EC blocks and the data blocks are divided into distribution sets and these sets are stored at a plurality of data storage locations. At each data storage location additional level two error correction blocks (L2EC blocks) are generated that provide local data redundancy. The L2EC blocks enable reconstruction of damaged elements at a data storage location without requiring communication with the other data storage locations.

Abstract: A systematic encoder such as a systematic polar encoder for channel encoding to ameliorate the effects of noise in a transmission channel. The codeword carries a data word to be transmitted transparently, and also carries a parity part derived from the data word and a fixed word. Implementations advantageously reduce coding complexity to the order of N log(N), wherein N is the dimension of a matrix of the n th Kronecker power associated with a matrix effectively employed by the encoder.

Abstract: A data processing apparatus is provided having error code generation circuitry configured to generate an error code associated with a received data value, such that a bit change in the received data value can be known about by reference to the error code. Stored data values are stored in a data store and associated error codes are stored in an error code store. Error checking circuitry performs a verification operation on a stored data value and an associated error code to determine if an error has occurred in at least one of the stored data value and the associated error code during storage. The received data value comprises at least one additional bit with respect to the stored data value and the error checking circuitry is configured to reconstruct the at least one additional bit by reference to the stored data value and the associated error code.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding circuit having a data decoder circuit, an element modification circuit, an element modification log, and a mis-correction detection circuit.

Abstract: Data may be distributed using data carousels. After a device receives the data, or a portion thereof, the device may make available a data carousel that allows others to receive the data. Each data carousel may contain a portion of the data. Data carousels may also contain error correction information that can be used to reconstruct missing portions of the data being distributed. A carousel directory may keep track of the carousel structure and direct the behavior of devices that are receiving data and/or distributing data.

Abstract: In one embodiment, a scheme for reliably reading data values, such as rapidly-changing counter values, from a memory location. Instead of performing a single read operation, a set of N consecutive read operations is performed to obtain a set of N samples. Since, for counter values and the like, the frequency of occurrence of out-of-sequence values is relatively low, it is expected that a majority of the N samples will be in sequence. Of these N samples, the largest subset of monotonically-increasing values is selected. The median value of this subset of monotonically non-decreasing values is returned as a reliable result of the read operation.

Abstract: Various embodiments of the present invention provide systems and methods for decoding codewords in a multi-section non-binary LDPC decoder. For example, an LDPC decoder is disclosed that includes a variable node processor operable to perform variable node updates based at least in part on check node to variable node messages and to generate variable node to check node messages, and a check node processor operable to process the variable node to check node messages in groups across each of a plurality of sections of an H matrix and to generate the check node to variable node messages.

Abstract: A method for re-using a soft decoder involves receiving soft data and hard data from memory cells in a memory device, mapping the soft data to a first set of soft information, mapping the hard data to a second set of soft information, and using the soft decoder to decode both the first set and second set of soft information.

Abstract: According to one aspect, the subject matter described herein includes a method for dynamically controlling a Turbo decoding process in a long term evolution (LTE) multi-user equipment (UE) traffic simulator. The method includes steps occurring in an LTE traffic simulator configured to simulate plural UE devices. The steps include receiving, from an evolved NodeB under test, a plurality of transport blocks. The steps also include dynamically determining a maximum number of Turbo decoding iterations for each of the transport blocks. The steps further include Turbo decoding each of the transport blocks for no more than its determined maximum number of Turbo decoding iterations.

Abstract: Disclosed are various embodiments that provide turbo decoding implemented as at least a portion of baseband processing circuitry. An input bit stream may be divided into a set of code blocks and a first code block may be separated from the set of code blocks. A hybrid automatic repeat request (HARQ) process is performed on the first code block to generate a processed first code block. The processed first code block is stored in an incremental redundancy (IR) buffer. A turbo decoding process is performed on the processed first code block to generate decoded first code block data and the decoded first code block data is stored in an external memory. The processed first code block is removed from the IR buffer for decoding a remaining portion of the set of code blocks.

Abstract: In a method, by a first circuit, a plurality of bits is converted in a first format to a second format. By a second circuit, the plurality of bits in the second format is used to program a plurality of memory cells corresponding to the plurality of bits. The first circuit and the second circuit are electrically coupled together in a first chip. The plurality of bits is selected from the group consisting of 1) address information, cell data information, and program information of a memory cell that has an error; and 2) word data information of a first word and error code and correction information corresponding to the word data information of the first word.

Abstract: A system is configured to receive a word on which to perform forward error correction; identify least reliable positions that correspond to encoded bits, within the word, associated with a lowest level of reliability; generate candidate words based on different combinations of inverted encoded bits; identify a pair of candidate words that includes a candidate word and another candidate word, the candidate word includes an inverted most reliable bit of the encoded bits within the candidate word; identify a quantity of errors within the candidate word; determine whether the quantity of errors corresponds to an odd value; invert a parity bit associated with the candidate word when the quantity of errors corresponds to the odd value; select the other candidate word when the parity bit is inverted; and perform forward error correction, on the word, using the other candidate word based on selection of the other candidate word.

Abstract: An encoder module includes P/L parity shift registers that are sequentially coupled, wherein an input of a first parity shift register of the parity shift registers is coupled to the input of the encoder module, an output of the last parity shift register of the parity shift registers is coupled to the output of the encoder module, each of the parity shift registers being configured to store L parity digits. The encoder module also includes a feedback circuit comprising P/L parity generation modules, wherein each of the parity generation modules is coupled to an output of a corresponding one of the parity shift registers by a switch and also coupled to the input of the first parity shift register, wherein each of the parity generation modules is configured to generate L parity digits for transmission to the input of the first parity shift register when its corresponding switch is closed.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate coding in a data processing system.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for mis-correction detection and correction in a data processing system.

Abstract: A decoding device is provided for decoding received data which is coded based on low-density parity-check code. The decoding device includes a variable node operation unit, a check node operation unit, and a circuit in the transmission path between the two units. The variable node operation unit generates secondary probability information based on primary probability information and the coded data. The check node operation unit generates the primary probability information based on the secondary probability information. The circuit transmits the primary probability information and the secondary probability information between the variable node operation unit and the check node operation unit. In addition, at least one of the primary probability information and the secondary probability information transmitted via the transmission path is represented by a time signal.

Abstract: A system and method for performing cryptographic functions in hardware using read-N keys comprising a cryptographic core, seed register, physically unclonable function (PUF), an error-correction core, a decryption register, and an encryption register. The PUF configured to receive a seed value as an input to generate a key as an output. The error-correction core configured to transmit the key to the cryptographic core. The encryption register and decryption register configured to receive the seed value and the output. The system, a PUF ROK, configured to generate keys that are used N times to perform cryptographic functions.

Abstract: Data objects are delivered over a packet-switched network and receivers receive encoded symbols, such as repair symbols, broadcast or multicast, with sufficient information to form requests for additional symbols as needed based on what source symbols or sub-symbols are needed or missing. The requests can be made in a unicast or request fashion. Requesting and broadcasting might be done by different entities. A broadcast server can generate and store repair symbols while a source server can store content in source form. A request can be a unicast HTTP byte-range request, such as a URL, starting position and length. Requests might be aligned with starting positions of files. A receiver can calculate starting and ending byte positions of symbols or sub-symbols in a file and get indications that conventional HTTP servers are usable for file repair. Repair servers can request broadcast of repair data when byte-range requests from multiple receivers overlap.

Abstract: A system and method for data transmissions in a wireless communications system, which accommodates for a periodic blockage of the transmission signal, is provided. A data stream is segmented into packets of a predetermined fixed-size for a burst-mode transmission over a channel of the communications system, wherein the transmission is subject to a periodic blockage. A forward error correction outer code is then applied to the packets of the data stream for recovery of packets subjected to the periodic blockage, and a unique word is added to each packet for acquisition of frequency, carrier phase and symbol timing of the respective packet. The packets of the data stream are interleaved based on an interleaver of a depth based at least in part on a ratio of a blockage free duration between two consecutive blockages of the periodic blockage to a duration of each blockage of the periodic blockage.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate encoding and/or decoding in a data processing system.

Abstract: A method may be performed at a data storage device that includes a memory and a controller. The method includes providing user data to a variable-bit error correction coding (ECC) encoder. The ECC encoder generates a first set of parity bits. A first number of parity bits in the first set of parity bits is determined based on stored counts of read errors. The method also includes storing the user data and the first set of parity bits to a memory of the data storage device.

Abstract: Systems and techniques for serial data stream operations are described. A described system includes a serial bus communicatively coupled with a memory structure to handle a serial data stream from or to the memory structure; generators configured to generate enablement signals that are associated with different bit-groups of the serial data stream, each of the enablement signals including pulses that are aligned with time-slots that are associated with a respective bit-group; logic elements configured to store internal states and produce output signals that are based on the serial data stream, the enablement signals, and the internal states, and circuitry configured to capture values. Each of the enablement signals enables a respective logic element to selectively change a respective internal state responsive to bit-values of a respective bit-group. Each of the captured values represents an output of a respective logic element that is responsive to all bit-values of a respective bit-group.

Abstract: Methods and apparatuses for combining error coding and modulation schemes are described herein. One or more methods include encoding data using linear error correcting code, modulating the encoded data, writing the modulated data to memory, and decoding the written data using a Viterbi algorithm and a linear error correcting code decoder.

Abstract: The present inventions are related to systems and methods for data processing. As one example, a data processing system is discussed that includes a data decoder circuit and a matrix select control circuit. The data decoder circuit is operable to apply a data decode algorithm to a decoder input using a selected parity check matrix to yield a decoder output. The matrix select control circuit operable to select one of a first parity check matrix and a second parity check matrix as the selected parity check matrix.

Abstract: Subject matter disclosed herein relates to error protection of data stored in and/or read from a memory device.

Abstract: A method includes receiving a representation of a set of single error detection (SED) parity bits and a representation of data. The data includes an error correction coding (ECC) codeword including information bits and ECC parity bits. Each SED parity bit of the set of SED parity bits indicates a parity value for a corresponding portion of the data. The method includes, in response to determining that a particular portion of the representation of the data includes a single erasure bit, selectively modifying a bit value of the single erasure bit based on the representation of the SED parity bit that corresponds to the particular portion and generating an updated representation of the ECC codeword when the bit value of the single erasure bit corresponds to the ECC codeword and has been modified. The method may include initiating an ECC decode operation of the updated representation of the ECC codeword.

Abstract: Embodiments of the invention relate to efficiently employing checksums for shared nothing clustered filesystems. Tools are provided to compute the checksum in response to a read transaction and to utilize the computed checksum to prevent serving corrupted data. Multiple levels of data replication are provided. The checksum computation functions within the multiple levels and addresses a specified data block that is the subject of the read transaction.

Abstract: A method for controlling a nonvolatile memory device includes reading a sub stripe including a plurality of sub pages stored in a first region, writing data stored in valid sub pages of the sub stripe to a second region different from the first region, and generating parity data using the data written to the second region and constituting a new sub stripe.

Abstract: An apparatus comprising a decoder circuit and a memory. The decoder circuit may be configured to generate a single address signal to read a first parity data signal, a second parity data signal and read and/or write systematic information data, a first a-priori-information signal and a second a-priori-information signal. The decoder circuit (i) reads the first parity data signal, the systematic information data and the first a-priori-information during even half-iterations of a decoding operation and (ii) reads the second parity data, the systematic information data and the second a-priori-information during odd half-iterations of the decoding operation. The memory may be configured to store the systematic information data and the first and second a-priori-information signals such that each are accessible by the single address signal.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing.

Abstract: Various embodiments of the present invention provide systems and methods for decoding of non-binary LDPC codes. For example, a low density parity check data decoder is disclosed that includes a variable node processor operable to perform variable node updates based at least in part on check node to variable node message vectors, a check node processor operable to perform check node updates and to generate the check node to variable node message vectors, and a scheduler operable to cause the variable node processor to use check node to variable node message vectors from multiple decoding iterations when performing the variable node updates for a given decoding iteration.

Abstract: An apparatus for a dual mode low density parity check (LDPC) decoder including edge random access memory (RAM), last-in-first-out/first-in-first-out (LIFO/FIFO) RAM, channel RAM, and parallel datapath engines, where the datapath engines include a standard belief propagation decoding (SBD) datapath and a layered belief propagation decoding (LBD) datapath, where the SBD datapath includes a shifter, an accumulator, multiplexers, and a g( )_sbd calculator, and where the LBD datapath includes the shifter, the multiplexers, and a g?( )_lbd calculator.

Abstract: In one or more aspects, the present invention improves the efficiency of soft information transfer within a soft-value processing apparatus, by reducing in some sense the “amount” of soft information transferred between constituent processor circuits within the apparatus, without forfeiting or otherwise compromising the transfer of “valuable” soft information. In one example, the soft values produced by a constituent processor circuit are identified as being reliable or unreliable according to a reliability threshold. Some or all of the unreliable values are omitted from a soft value information transfer to another constituent processor circuit, or they are quantized for such transfer. The reduction in memory requirements for soft information transfer advantageously allows the use of lower power, less complex, and less expensive circuitry than would otherwise be required in the apparatus, which may be, as a non-limiting example, a Turbo receiver in a wireless communication device.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, data decoding systems are disclosed that include a data decoder circuit and a decode value modification circuit.

Abstract: Various embodiments of the present invention provide systems and methods for a symbol flipping data processor. For example, a symbol flipping data processor is disclosed that includes a data decoder in the symbol flipping data processor operable to perform error checking calculations, and a data detector in the symbol flipping data processor operable to perform symbol flipping in the data detector based at least in part on the error checking calculations, wherein the output of the data processor is generated at least in part based on the symbol flipping in the data detector.

Abstract: A method of forward error correction in an optical communications system. A signal to be transmitted is logically defined as a super-frame comprising a plurality of frames including a parity frame and a predetermined set of data frames. Each frame of the super-frame is processed in accordance with a first FEC scheme having a known error correlation characteristic. At least the set of data frames is processed in accordance with a second FEC scheme which is selected based on the error correlation characteristic of the first FEC scheme.

Abstract: According to at least one embodiment, a signal processor apparatus includes a Viterbi decoder, a processor, and an adjustment module. The Viterbi decoder calculates a branch metric based on an input signal. The processor outputs a processing result correlated with a processing result of the Viterbi decoder. A latency of the processor for the input signal is lower than a latency of the Viterbi decoder. The adjustment module adjusts a first parameter for calculating the branch metric based on the processing result of the processor.

Abstract: Systems, methods and computer program products for facilitating the recovery of lost real-time media packets within a computer network real-time application implementing Forward Error Control (FEC), such that server performance is not affected from a CPU and memory perspective, are disclosed. In an embodiment, a conference server that is part of a communication network compliant with the Real Time Transport Protocol (RTP) is able to avoid regenerating FEC packets by not performing any FEC coding operation on the packets unless it is flagged to indicate regeneration via an FEC (e.g., Reed-Solomon) coding is necessary. Absent the flag, the conference server updates the received FEC packet as per the RTP and transmits the packet to its ultimate destination. Such disclosed systems, methods and computer program products are independent of the nature of the media being protected and flexible enough to support a wide variety of FEC techniques.

Abstract: Exemplary method, system, and computer program product embodiments for an incremental modification of an error detection code operation are provided. In one embodiment, by way of example only, for a data block requiring a first error detection code (EDC) value to be calculated and verified and is undergoing modification for at least one randomly positioned sub-blocks that becomes available and modified in independent time intervals, a second EDC value is calculated for each of the randomly positioned sub-blocks. An incremental effect of the second EDC value is applied for calculating the first EDC value and for recalculating the first EDC value upon replacing at least one of the randomly positioned sub-blocks. The resource consumption is proportional to the size of at least one of the randomly positioned sub-blocks that are added and modified. Additional system and computer program product embodiments are disclosed and provide related advantages.

Abstract: A method for operating a memory device is disclosed. The method includes receiving a serial data and a serial cyclic redundancy check (CRC) code transmitted sequentially through a channel, converting the serial data into a parallel data and the serial CRC code into a parallel CRC code, outputting the parallel data at a first time point, outputting the parallel CRC code at a second time point later than the first time point, calculating a CRC code by using the parallel data, comparing the parallel CRC code and the calculated CRC code with each other and detecting an error of the serial data transmitted through the channel according to the result of the comparison, and outputting an error detection signal in response to the result of the comparison.

Abstract: Circuits, integrated circuits, and methods are disclosed for interleaved parity computation. In one such example circuit, an interleaved parity computation circuit includes a first parity circuit that receives a first set of bits and a second parity circuit that receives a second set of bits. The first set of bits includes a first parity bit, and is received in the first parity circuit during a first clock cycle. The first parity circuit generates a first signal indicative of the parity of the first set of bits. The second set of bits includes a second parity bit, and is received in the second parity circuit during a second clock cycle. The second parity circuit generates a second signal indicative of the parity of the second set of bits. A combining circuit combines the first signal and the second signal into an alert signal.

Abstract: Provided are a method of decoding an LDPC code for producing several different decoders using a parity-check matrix of the LDPC code, and an LDPC code system including the same. The system includes: an LDPC encoder outputting an LDPC codeword through a channel; a first LDPC decoder decoding the LDPC codeword received through the channel, and when the decoding has failed in a second LDPC decoder, decoding the LDPC codeword according to original parity check matrix of the LDPC codeword, using soft information newly generated after the decoding is ended in the second LDPC decoder; and the second LDPC decoder, when the decoding has failed in the first LDPC decoder, receiving the soft information on each bit from the first LDPC, and decoding the LDPC codeword according to a new parity-check matrix produced from the parity-check matrix of the LDPC codeword using the received soft information on each bit.

Abstract: A system receives a first word on which to perform error correction; identifies combinations in which encoded bits, within the first word, can be inverted; generates candidate words based on the first word and the combinations; decodes the candidate words; determines distances between the decoded words and the first word; selects, as a second word, one of the decoded words associated with a shortest distance; compares the second word to the first word to identify errors within the first word; generates a value to cause a reliability level of the first word to increase when a quantity of the errors is less than a threshold; generates another value to cause a reliability level of the first word to decrease when the quantity of the errors is not less than the threshold; and outputs a third word based on the first word, and the value or the other value.

Abstract: A non-binary quasi-cyclic (QC) low-density parity-check (LDPC) code decoding device comprises a first barrel-shifter, a routing network and a second barrel-shifter. The first barrel-shifter uses a constraint h?v?+h?v?=hv to shift q?1 elements of an input by j0 positions to produce first temporary elements. The routing network connects to the first barrel-shifter, permutes the first temporary elements to produce second temporary elements if v? of the constraint is not zero and designates the first temporary elements as the second temporary elements if v? of the constraint is zero. The second barrel-shifter connects to the routing network and uses the constraint h?v?+h?v?=hv to shift q?1 elements of the second temporary elements by i0 positions. A non-binary QC-LDPC decoding method is also disclosed.

Abstract: An apparatus and method for hierarchical modulation and demodulation in a wireless communication network are provided. A hierarchical modulation apparatus may map information bits to a plurality of levels based on a predetermined level map, may generate an error verification code for each of the levels based on the information bits mapped to the levels, may generate coded information bits for each of the levels, and may map bits in a predetermined position among the coded information bits, to Pulse-Position Modulation (PPM) symbols in a sequence of the levels.

Abstract: In a memory system, a memory controller includes a randomizer and a seed controller. The seed controller provides a seed to the randomizer and includes; a first register block performing a first cyclic shift operation using a first parameter related to the nonvolatile memory device, a second register block performing a second cyclic shift operation using a second parameter related to the nonvolatile memory device, and a seed generating block generating the seed from the first and second cyclic shift results.

Abstract: Methods of reading data from storage devices may include reading data stored in the storage device using normal read voltages; performing a first low density parity check (LDPC) decoding based on the read data; generating reliability bits of each of read bits according to the decoding result, the read bits being bits of the read data; and performing a second low density parity check (LDPC) decoding based on the read data and the reliability bits to perform a first error correction on the read data.

Abstract: Apparatus and methods are disclosed, including a method of programming involving determining an error rate for the memory cells, and programming the memory cells using a charge state level for a charge state that is based at least in part on the determined error rate.

Abstract: A method includes initiating a decoding operation of a first portion of a codeword to generate a set of data bits. The first portion includes first parity bits and is associated with a first error correcting code. The method includes initiating an encoding operation of the set of data bits according to a second error correcting code to generate computed parity bits. The method includes comparing the computed parity bits to a second portion of the codeword to determine a number of bits that differ between the computed parity bits and the second portion of the codeword. The method also includes generating an indication of successful decoding in response to the number of bits that differ being less than a threshold value.