Abstract: An error correction circuit 1 in accordance with an aspect of the invention includes an associative memory 20, a logic circuit 10 disposed in parallel with the associative memory 20, and selection unit 30 that receives an output signal from the associative memory 20 and an output signal from the logic circuit 10 as an input. The associative memory 20 includes a table that handles an input signal as a word and holds an output signal related to the word and an error correction code used to correct the output signal as data. The associative memory 20 further includes error correction unit that outputs a signal in which an error was corrected based on data related to a word corresponding to an input signal. The selection unit 30 selects and outputs one of an output signal from the associative memory 20 and an output signal from the logic circuit 10.

Abstract: k information bits are encoded according to a code with which is associated a parity check matrix H that has n columns. The entire resulting codeword is stored in a storage medium. At least n?<n bits of a representation of the codeword are read from the storage medium and an attempt is made to decode only the n? bits using a matrix H? that has fewer columns than H. Typically, H has m=n?k rows and H? has m?(n?n?) rows and n? columns. If the attempt fails, one or more additional bits are read from the storage medium, if necessary, and are combined with the n? bits, and the decoding attempt is repeated using a matrix H?? that has more columns than H?.

Abstract: The invention is intended to curtail the circuit scale of the error correction circuit of a flash memory. The invention relates to a controller with error correction function capable of controlling writing and reading of data in a plurality of memories, including a buffer memory, an error correction circuit, and a plurality of interface modules provided individually corresponding to each one of the plurality of memories, for exchanging data with the memories, in which the plurality of interface modules have a plurality of syndrome generation function parts for receiving sector data from the memories and error correction codes corresponding to the sector data, and generating syndromes on the basis of the received sector data and error correction codes, the buffer memory.

Abstract: A computer-implemented method of managing a memory of a non-volatile solid state memory device by balancing write/erase cycles among blocks to level block usage. The method includes: monitoring an occurrence of an error during a read operation in a memory unit of the device, wherein the error is correctable by error-correcting code; and programming the memory unit according to the monitored occurrence of the error; wherein the step of monitoring the occurrence of an error is carried out for at least one block; and wherein said step of programming comprises wear-leveling the monitored block according the error monitored for the monitored block. A computer system and a computer program-product is also provided. The non-volatile solid state memory device includes: a memory unit having data stored therein; and a controller with a logic for programming the memory unit according to a monitored occurrence of an error during a read operation.

Abstract: Improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices by increasing the data area of user data being covered by the ECC code. This averages any possible bit errors over a larger data area and allows a greater number of errors to be corrected by a combining the ECC codes in the coverage area without substantially changing the overall size of ECC codes being stored over a single sector approach. In one embodiment of the present invention, the size of the data block utilized for ECC coverage is variable and can be selected such that differing areas of the memory array or data types can have a differing ECC data coverage sizes. It is also noted that the ECC algorithm, math base or encoding scheme can also be varied between these differing areas of the memory array.

Abstract: An error correcting apparatus includes a memory for storing therein second block data at an interval of a time difference while it uses a part of a storage area of first block data having multiple pieces of frame data each having data having a predetermined length as one unit, and an error correcting portion configured to subject the first block data and the second block data each read out from the memory to error correction.

Abstract: Provided is an operation method which can be applied to a PRAM, an ReRAM, and a solid electrolyte memory which stores error correction codes, each of which comprises of symbols, each of which comprises bits, and which codes allow error correction in units of symbols. In the operation method, the respective symbols are read by using different reference cells 12. When a correctable error is detected in read data from data cells forming the error correction codes and corresponding to an input address, a data in a data cell corresponding to the error bit is corrected for a first error symbol of an one bit error pattern, and data in a reference cell that is used to read the second error symbol are corrected for a second error symbol related to a multi-bit error pattern.

Abstract: A method of transmitting content to a wireless display device is disclosed. The method may include receiving multimedia data, encoding the multimedia data, and writing encoded multimedia data into a first predetermined memory location of a shared memory. Further, the method may include encapsulating the encoded multimedia data and writing encapsulation data into a second predetermined memory location of the shared memory. The method may also include calculating error control encoding and writing the error control encoding into a third predetermined memory location of the shared memory. Further, the method may include transmitting the encoded multimedia data, the encapsulation data, and the error control encoding to the wireless display device.

Abstract: A data receiving circuit includes: a first de-interleave circuit configured to de-interleave first data which is demodulated and is soft-decision-processed; a second de-interleave circuit configured to de-interleave second data which is demodulated and is soft-decision-processed; a memory configured to be shared by the first de-interleave circuit and the second de-interleave circuit and store respective hard decision information and respective soft decision information of the first data and the second data; and a memory control circuit configured to vary a first through fourth number of bits stored in the memory, the first number corresponding to the hard decision information of the first data, the second number corresponding to the soft decision information of the first data, the third number corresponding to the hard decision information of the second data, the fourth number corresponding to the soft decision information of the second data.

Abstract: A method for enhancing verification efficiency regarding error handling mechanism of a controller of a Flash memory includes: providing an error generation module, for generating errors; and triggering the error generation module to actively generate errors of at least one specific type in order to increase an error rate corresponding to the specific type. An associated memory device and the controller thereof are provided, where the controller includes: a ROM arranged to store a program code; a microprocessor arranged to execute the program code to control access to the Flash memory and manage a plurality of blocks, and further enhance the verification efficiency regarding error handling mechanism of the controller; and an error generation module arranged to generate errors. The controller that executes the program code by utilizing the microprocessor triggers the error generation module to actively generate errors of at least one specific type to increase an error rate.

Abstract: A method of storing data includes receiving general purpose (GP) data and special Error Tolerant or Streaming (ETS) data, storing the GP data using a data storage method, and storing the ETS data using a different data storage method which affects the access rate, resilience to errors, data integrity, storage density, or storage capacity. The storage medium, which can include a disk drive, flash memory, or holographic memory, is utilized differently depending on the required Quality of Service in aspects including block size, storage of error correction codes, utilization of error correction codes, storage area density, physical format pattern, storage verification, or reaction to failed storage verification. For disk drives these differences include spacing between tracks; overlap between tracks; spiral track formatting; concentric track formatting, and size of blocks, and for flash memories these differences include levels per cell and number of cells.

Abstract: The invention provides a method for performing copy back operations. First, a copy back command is sent to a flash memory for reading a first error correction code (ECC) data from a first address. The first ECC data is then received from the flash memory. The first ECC data is then decoded without performing error correction to calculate a fail count of the first ECC data. The fail count is then compared with a first threshold value. When the fail count is less than the first threshold value, a first program command is sent to the flash memory for storing the first ECC data to a second address of the flash memory. When the fail count is less than the first threshold value, the first ECC data is not sent back to the flash memory.

Abstract: A disk array apparatus includes a plurality of magnetic disks, and a RAID controller that generates redundancy data for host data received from a host apparatus by a primitive polynomial of Galois extension field, generates a redundancy code for the host data and the redundancy data, the redundancy code is a cyclic code calculated by a generating polynomial identical to the primitive polynomial, and writes the host data and the redundancy data to the plurality of magnetic disks.

Abstract: A storage control apparatus includes a storage unit having a plurality of blocks for storing data, each of the plurality of blocks being detected for data error by an error check code (ECC), a processor to execute a process to at least, modify an ECC stored in one of the storage unit, detect data-reading error in at least one block in the storage unit based on the modified ECC, and determine the number of detected blocks in the storage unit.

Abstract: A method of operating a nonvolatile memory device including a memory cell array having first and second main cells for storing external input data, first spare cells for storing data for error correction code (ECC) processing on the data stored in the first and second main cells and second spare cells for storing data for ECC processing on the data stored in the first and second main cells which involves reading the data stored in the first spare cells, reading the data stored in the second main cells and the data stored in the second spare cells, and performing the ECC processing on the data read from the second main cells using the data read from the first spare cells and the data read from the second spare cells.

Abstract: A fault-tolerant approach for updating a compressed read-only file system in embedded devices using a two-step approach. In the first phase an update package creates an intermediate memory image where the data blocks are independently compressed so that, if needed, the data therein can be decompressed and read without access to any other surrounding data blocks. Then in the second phase the intermediate memory image is decompressed in a buffer so that it can be reimaged into its final form and order before being recompressed and written back to non-volatile memory over-writing the intermediate memory image.

Abstract: An electronic storage device for connecting with a host system includes a flash memory including a number of memory segments, and a controller including an error correction segment capable of generating a first correction code and a second correction code according to a written data received by the controller. The written data, the first correction code and the second correction code are written into a memory segment of the flash memory by the controller. The first correction code is used for checking whether there is an error bit in the written data, and the second correction code is used for checking and correcting said error bit in the written data.

Abstract: A semiconductor storage device, a method of controlling the same, and an error correction system allow reduction in power consumption and circuit scale without detriment to error correction capability. An error correction code (ECC) circuit of a solid state drive (SSD) performs first error correction on read data using a first error correction code (Hamming code), and further performs second error correction on the result of the first error correction using a second error correction code (BHC code). Furthermore, the ECC circuit performs third error correction on the result of the second error correction using a third error correction code (RS code).

Abstract: A memory controller includes first and second interface controllers configured to exchange data with external devices, and an internal block connected between the first and second interface controllers. The first and second interface controllers exchange data received from the external devices and at least one parity bit corresponding to the received data through the internal block.

Abstract: A data processing device and a method for error detection and error correction. The data processing device includes an error detection arrangement and an error correction arrangement. The error detection arrangement is able to detect correctable error and uncorrectable error in the data stored in a memory cell of the memory. The error detection arrangement then determines the neighboring memory cells or memory cells that are physically adjacent to the memory cell for which the correctable error was detected and generates a signal indicating a fault depending on the correctable errors detected in the neighboring physically adjacent memory cells. If a signal indicating a fault is not generated, then an error correction arrangement is used to correct the correctable error detected by the error detection arrangement.

Abstract: The invention provides a method, device and system for encoding and decoding data. The method includes receiving information including data units, storing the data units into a memory and encoding the data units by performing a plurality of store and exclusive-or operations on the data units resulting in encoded symbols Sn, where n is a positive integer.

Abstract: An error correction device is provided. When an error of an incorrect data group stored in a memory is detected, a memory controller of the error correction device executes a burst read, burst write or burst read-modify-write (RMW) operations to the memory instead of the conventional single read-modify-write (RMW) operation, thereby reducing the occupied bandwidth of the memory.

Abstract: A recording and/or reproducing method, a recording and/or reproducing apparatus, and a computer readable recording medium storing a program for performing the method. A recording unit block in which invalid data is partially padded is written on an information storage medium along with padding information indicating that the invalid data is included in the recording unit block. The padding information is useful in determining whether the recording unit block includes the padding data. Accordingly, unnecessary retrial processes of a drive system are reduced such that the performance of the drive system is improved and error correction capability is enhanced.

Abstract: A system to improve miscorrection rates in error control code may include an error control decoder with a safe decoding mode that processes at least two data packets. The system may also include a buffer to receive the processed at least two data packets from the error control decoder. The error control decoder may apply a logic OR operation to the uncorrectable error signal related to the processing of the at least two data packets to produce a global uncorrectable error signal. The system may further include a recipient to receive the at least two data packets and the global uncorrectable error signal.

Abstract: An error correction method for correcting an first ECC code from a storage unit, comprising: (a) marking at least a first part of the first ECC code according to a correction result generated by correcting error of the first ECC code, to generate a first error correction reference information; and (b) marking at least a second part of the first ECC code according to the first error correction reference information to generate a second error correction reference information.

Abstract: A system to improve memory failure management may include memory, and an error control decoder to determine failures in the memory. The system may also include an agent that may monitor failures in the memory. The system may further include a table where the error control decoder may record the failures, and where the agent can read and write to.

Abstract: A system to improve error control coding may include memory chips of at least two different kinds. The system may also include error control encoder circuitry to substantially encode data for storage in any memory rank. The system may further include error control decoder circuitry to substantially decode encoded data received from any memory rank. The error decoder circuitry is comprised of a slow decoder and a fast decoder.

Abstract: A system to improve error correction may include a fast decoder to process data packets until the fast decoder finds an uncorrectable error in a data packet at which point a request for at least two data packets is generated. The system may also include a slow decoder to possibly correct the uncorrectable error in a data packet based upon the at least two data packets.

Abstract: An apparatus, system, and method are disclosed to increase data integrity in a redundant storage system. The receive module receives a read request to read data from a logical page spanning an array of N+P number of storage elements. The array of storage elements includes N number of the storage elements each storing a portion of an ECC chunk and P number of the storage elements storing parity data. The data read module reads data from at least a portion of a physical page on each of X number of storage elements of the N+P number of storage elements where X equals N. The regeneration module regenerates missing data. The ECC module determines if the read data and any regenerated missing data includes an error. The read data combined with any regenerated missing data includes the ECC chunk.

Abstract: A system to improve memory reliability in computer systems that may include memory chips, and may rely on a error control encoder to send codeword symbols for storage in each of the memory chips. At least two symbols from a codeword are assigned to each memory chip and therefore failure of any of the memory chips could affect two symbols or more. The system may also include a table to record failures and partial failures of the codeword symbols for each of the memory chips so the error control encoder can correct subsequent partial failures based upon the previous partial failures. The error control coder is capable of correcting and/or detecting more errors if only a fraction of a chip is noted in the table as having a failure as opposed to a full chip noted as having a failure.

Abstract: Provided is a read method for a memory system. The read method determines whether a read data error is correctable. The read method applies a plurality of read operations at a set read voltage level to identify erasure candidates, when the error is uncorrectable. The read method performs erasure decoding using an error correction code or an error detection code for the erasure candidates.

Abstract: A flash memory device connected to a host includes: a flash memory; and a control circuit comprising a first error correcting code unit and a second error correcting code unit. The data length of a redundancy bit generated by the second error correcting code unit is longer than the data length of a redundancy bit generated by the first error correcting code unit. The first error correcting code unit is adopted to process with a data transmitted to the flash memory from the host when a damage risk of the flash memory is lower than a specific value; and the second error correcting code unit is adopted to process with the data transmitted to the flash memory from the host when the damage risk of the flash memory is higher than the specific value.

Abstract: A data transfer method is utilized for saving memory for storing packet in USB protocol. When a transmitter is to send a payload, the protocol layer of the transmitter writes the payload into a shared payload memory. The protocol layer generates a corresponding header according to the payload, and writes the corresponding header into a shared header memory. The data-link layer of the transmitter generates a packet by means of directly combining the payload saving in the shared payload memory and the header saving in the shared header memory, and sends the packet. Hence, when the transmitter is to send the payload, the transmitter only requires a memory of which the size is equal to a packet. In this way, the memory can be saved, reducing the cost.

Abstract: A memory system is provided. The memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a memory cell array and a read/write circuit configured to perform a read/write operation in the memory cell array during a read operation. The controller is configured to receive the read data from the nonvolatile memory, perform an error detection and correction operation on the read data. Upon detecting an error in a received portion of the read data, the controller is further configured to halt further transmission of the read data from the nonvolatile memory, perform the error detection and correction operation on the received portion of the read data to correct the detected error. After correcting the detected error in the received portion of the read data, the controller is configured to resume transmission of the read data from the nonvolatile memory.

Abstract: A data processing apparatus, a data processing method, an encoding apparatus, and an encoding method which can be applied, for example, to a transmission system for transmitting an LDPC code and so forth, and which can improve tolerance to errors. Of an LDPC code which is prescribed in the DVB-S.2 and has a code length of 64,800 and an encoding rate of 2/3, mb code bits are replaced, and the code bits after the replacement become symbol bits of b symbols. When m is 8 and b is 2, where the i+1th bit from the most significant bit of 8×2 code bits and 8×2 symbol bits of two successive symbols are represented by bi and yi, respectively, replacement of allocating b0 to y15, b1 to y7, b2 to y1, b3 to y5, b4 to y6, b5 to y13, b6 to y11, b7 to y9, b8 to y8, b9 to y14, b10 to y12, b11 to y3, b12 to y0, b13 to y10, b14 to y4 and b15 to y2.

Abstract: The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of data. A demultiplexer replaces, in accordance with an allocation rule for allocating code bits of an LDPC code to symbol bits representative of symbols, mb bits from among the code bits and sets the code bits after the replacement as symbol bits of b symbols. According to the allocation rule, where groups into which the code bits and the symbol bits are to be grouped in response to an error probability thereof are set as code bit groups and symbol bit groups, respectively, a combination of any of the code bit groups and the symbol bit group of the symbol bits to which the code bits of the code bit group are to be allocated and bit numbers of the code bits and the symbols bits are prescribed.

Abstract: A method is provided for performing error correction operations in a memory module. A memory hub device, which is integrated in the memory module, receives an access request for accessing a set of memory devices of the memory module coupled to the memory hub device. Data is transferred between a link interface of the memory hub device and the set of memory devices. Error correction logic, which is integrated in the memory hub device, performs one or more error correction operations on the data transferred between the link interface and the set of memory devices. The memory hub device transmits and receives data, via a memory channel between an external memory controller and the link interface, without any error correction code, thereby reducing an amount of bandwidth used on the memory channel.

Abstract: Embodiments of circuits and methods for circuits for the detection of soft errors in cache memories are described herein. Other embodiments and related methods and examples are also described herein.

Abstract: The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of data. A demultiplexer 25 replaces, in accordance with an allocation rule for allocating code bits of an LDPC code to symbol bits representative of symbols, mb bits from among the code bits and sets the code bits after the replacement as symbol bits of b symbols. For example, when m is 12 and b is 1, where the i+1th bits from the most significant bit of the 12×1 code bits and the 12×1 symbol bits of one symbol are represented as bits bi and yi, replacement for allocating, for example, b0 to y8, b1 to y0, b2 to y6, b3 to y1, b4 to y4, b5 to y5, b6 to y2, b7 to y3, b8 to y7, b9 to y10, b10 to y11 and b11 to y9 is carried out. The present invention can be applied, for example, to a transmission system for transmitting an LDPC code and so forth.

Abstract: A low density parity check decoder for performing LDPC decoding based on a layered algorithm applied to a parity check matrix, the decoder including a channel memory, a metrics memory, first and second operand supply paths each arranged to provide operands based on channel values and metrics values; a processor block including a plurality processing units in parallel and arranged to receive operands from the first supply path and to determine updated metric values, a buffer arranged to store at least one of the operands from the first supply path; and an adder coupled to an output of the processor block and arranged to generate updated channel values by adding the updated metrics values to operands from a selected one of the buffer and the second supply path.

Abstract: Embodiments of circuits and method for dual redundant register files with error detection and correction mechanisms are described herein. Other embodiments and related examples are also described herein.

Abstract: Embodiments of the invention are generally directed to improving the reliability, availability, and serviceability of a memory device. In some embodiments, a memory device includes a memory core having a first portion to store data bits and a second portion to store error correction code (ECC) bits corresponding to the data bits. The memory device may also include error correction logic on the same die as the memory core. In some embodiments, the error correction logic enables the memory device to compute ECC bits and to compare the stored ECC bits with the computed ECC bits.

Abstract: The present invention provides a storage device and a method for extending lifetime of storage devices. The storage device comprises: at least a non-volatile memory unit, at least an error correction code (ECC) engine, and a control unit. The non-volatile memory unit comprises a plurality of blocks, and the blocks comprise a plurality of pages, respectively. The ECC engine is coupled to the non-volatile memory unit, and for detecting and correcting errors for the non-volatile memory unit. The control unit is coupled to the non-volatile memory unit and the ECC engine, and for selectively label a specific block in the non-volatile memory unit as an abnormal block according to an error detecting result of the ECC engine.

Abstract: A memory device electrically connectable to a host circuit receives, from the host circuit, data including a first actual data to be written into the first memory area; acquires first parity data associated with the first actual data; generates second actual data that is a copy of the first actual data, and second parity that is a copy of the first parity data; writes the first actual data and the first parity data into the first memory area, and writes the second actual data and the second parity data into the second memory area; and reads the first actual data, the first parity data, the second actual data, and the second parity data from the data memory section for transmission to the host circuit.

Abstract: A data memory system is provided which includes a nonvolatile memory cell array, an error correction code generation circuit, an error correction code decoding circuit, and a first circuit. The nonvolatile memory cell array includes a plurality of memory cells which store digital data each having at least a value of “1” or “0” as a charge of a charge accumulation layer included in each memory cell, and use a difference between charges of the accumulation layer as a writing bit or an erasing bit. The nonvolatile memory cell array erases memory cells in units of pages, each page being formed of adjacent memory cells included in the plurality of memory cells.

Abstract: An exemplary storage controller for controlling data access of a storage device includes a control circuit and a soft decoder. The control circuit is utilized for reading data from the storage device to obtain readout data. The soft decoder is coupled to the control circuit, and utilized for performing a soft decoding operation upon the readout data to generate decoded data. The soft decoder may be a low density parity check (LDPC) decoder, a block turbo code (BTC) decoder, or a convolutional turbo code (CTC) decoder. The storage device may be a flash memory device.

Abstract: A memory controller that has an error correction number correspondence table that stores an error threshold level in correspondence with an error correction number; an error threshold level storage section that stores an error threshold level for each block; an uncorrected number measurement section that measures an uncorrected number of an error correction for each block; an error threshold level modification section that, each time an uncorrected number of a certain block exceeds a predetermined number, modifies the error threshold level of the block; an encoder that performs encoding processing of data stored in memory cells belonging to each block with an error correction number that is based on an error threshold level and the error correction number correspondence table; and a decoder that performs decoding processing of data.

Abstract: A redundant code generation method includes: dividing original data into data strings; dividing each data string into a number of bit strings that accords with an extended Galois field operation; storing each of the bit string in a different memory area of a memory; and executing an exclusive OR operation among vectors, which are extracted from the respective bit strings stored in the memory, according to an operational expression to compute bit strings that make up redundant code data strings without carrying out a bit shift operation within the vectors. A predetermined plural number of bits is taken as a data unit and the number of bits as elements constituting each vector is equal to the data unit. The operational expression includes a companion matrix of a primitive polynomial of the Galois field and defined the generation of the redundant code data strings.

Abstract: A method and apparatus for memory allocation for turbo decoder input with a long turbo codeword, the method comprising computing a bit level log likelihood ratio (LLR) of a demodulated signal over a superframe to generate at least one systematic bit LLR and at least one parity bit LLR; storing the at least one systematic bit LLR and the at least one parity bit LLR over the superframe in a decoder memory; and reading the systematic bit LLR and the parity bit LLR over the superframe to decode at least one codeword from the decoder memory.

Abstract: One exemplary storage controller of controlling data access of a storage device includes an encoding circuit and a control circuit. The encoding circuit is programmable to support a plurality of different finite fields, and implemented for generating encoded data according to an adjustable finite field setting. The control circuit is implemented for controlling the adjustable finite field setting of the encoding circuit and recording data into the storage device according to the encoded data. Another exemplary storage controller of controlling data access of a storage device includes a decoding circuit and a control circuit. The decoding circuit is programmable to support a plurality of different finite fields, and implemented for generating decoded data according to an adjustable finite field setting. The control circuit is implemented for reading data from the storage device to obtain readout data and controlling the adjustable finite field setting of the decoding circuit.