Abstract: A technique for detecting and correcting errors in a memory device, in accordance with one embodiment, includes a data storage area arranged in a plurality of blocks, wherein each block contains a plurality of words. The memory device also includes an error detection/correction storage area for storing error detection/correction bytes corresponding to each word in each block and error detection words corresponding to each block.

Abstract: Systems and methods are provided that confront the problem of failed storage integrated circuits (ICs) in a solid state drive (SSD) by using a fault-tolerant architecture along with one error correction code (ECC) mechanism for random/burst error corrections and an L-fold interleaving mechanism. The systems and methods described herein keep the SSD operational when one or more integrated circuits fail and allow the recovery of previously stored data from failed integrated circuits and allow random/burst errors to be corrected in other operational integrated circuits. These systems and methods replace the failed integrated circuits with fully functional/operational integrated circuits treated herein as spare integrated circuits. Furthermore, these systems and methods improve I/O performance in terms of maximum achievable read/write data rate.

Abstract: A recording apparatus includes a first operation unit that calculates an EDC intermediate value from first data in a first region at least including data to be read after an EDC when reading data in a second sequence in a first sector from a data buffer that stores a block, a data memory that stores at least part of the first data used for operation by the first operation unit, a second operation unit that reads data excluding the first data from the block as second data from the data buffer and calculates the EDC based on the second data and the EDC intermediate value, and an integration unit that integrates the first data, the second data and the EDC, wherein the integration unit receives the EDC and the second data from the second operation unit, receives the first data from the data memory, and integrates and outputs them.

Abstract: A micro controller unit including an error indicator hardware module, the error indicator module being arranged to respond to event signals representative of internal and external fault and error events perturbing the micro controller unit function by registering in non-volatile memory a record of the nature of each of the events, wherein the record of the events is inaccessible to alteration.

Abstract: Non-volatile storage devices and techniques for operating non-volatile storage are described herein. One embodiment includes accessing “n” pages of data to be programmed into a group of non-volatile storage elements. The “n” pages are mapped to a data state for each of the non-volatile storage elements based on a coding scheme that evenly distributes read errors across the “n” pages of data. Each of the non-volatile storage elements in the group are programmed to a threshold voltage range based on the data states to which the plurality of pages have been mapped. The programming may include programming the “n” pages simultaneously. In one embodiment, mapping the plurality of pages is based on a coding scheme that distributes a significant failure mode (for example, program disturb errors) to a first of the pages and a significant failure mode (for example, data retention errors) to a second of the pages.

Abstract: In order to correct an error in input data to thereby obtain write data, in a memory core, an EXOR element performs arithmetic processing based on an output result of an output data latch for latching read data and a result of inputted array input data, and a selector selects a result of the arithmetic processing to prepare write data. Thus, data obtained after performance of the arithmetic processing can be generated in a semiconductor memory by an operation performed immediately after data read. In addition, it is unnecessary to transfer data to an external logic circuit. Therefore, the result of the arithmetic processing can be written to a memory cell block in a subsequent clock.

Abstract: Described herein are a method and apparatuses for providing customizable error correction for memory arrays. In one embodiment, an apparatus includes a memory device having a memory array to store data and an analog to digital sense unit coupled to the memory array. The analog to digital sense unit senses analog signals associated with the memory array and converts the analog signals into distributions of digital values. An error-correcting code (ECC) unit receives the distributions of digital values from the analog to digital sense unit. A configurable non-volatile look-up table generates ECC parameters including error probability data and provides the ECC parameters to the ECC unit for error correction. The error probability data has error probability values that are associated with the distributions of digital values. The ECC unit executes an ECC algorithm to provide error correction using the error probability data.

Abstract: Systems and methods for performing high-speed multi-channel forward error correction using external DDR SDRAM is provided. According to one exemplary aspect, an interleaver/deinterleaver performs both read and write accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The interleaver/deinterleaver accesses data in the DDR SDRAM as read blocks and write blocks. Each block includes two data sequences. Each data sequence further includes a predetermined number of data words to be interleaved/deinterleaved. The PRECHARGE and ACTIVE command for one data sequence is issued when a preceding data sequence is being processed. Data in one read/write data sequence has the same row address within the same bank of the DDR SDRAM.

Abstract: Data move operations in a memory device are described that enable identification of data errors. Error detection circuitry in the memory device can be operated using parity data or ECC data stored in the memory. Results of the error detection can be accessed by a memory controller for data repair operations by the controller.

Abstract: A method is for decoding a block of N information items encoded with an error correction code and mutually correlated. The method includes carrying out a first decorrelation of the N information items of a block is carried out, and storing the block decorrelated. The method also includes a performing a processing for decoding a group of P information items of the block, and decorrelating at least part of the P decoded information items. The processing for decoding the group of P information items and the decorrelation are repeated with different successive groups of P information items of the block until the N information items of the block have been processed, until a decoding criterion is satisfied.

Abstract: A method begins by a processing module receiving a plurality of record requests to record a broadcast of data. The method continues with the processing module encoding the data using an error coding dispersal storage function to produce a plurality of sets of encoded data slices. The method continues with the processing module generating a list of requesting device identities corresponding to the plurality of requests and storing the plurality of sets of encoded data slices and the list of requesting device identities in a dispersed storage network memory. The method continues with the processing module receiving a playback request from a device identified in the list of requesting device identities, generating a unique retrieval matrix for the device, and outputting a unique plurality of sets of encoded data slices from the plurality of sets of encoded data slices in accordance with the unique retrieval matrix.

Abstract: A method is provided for correcting a write defect in a data storage apparatus comprising a storage medium. The method comprises reading information from a track of the storage medium in which a write defect occurs, calculating a number of error-corrected error correction code symbols in sectors of the track based on the read information, determining a number of sectors on which write defect correction is to be performed by comparing the calculated number of error-corrected error correction code symbols with a threshold, and performing a rewrite operation on the track, beginning at a starting sector determined by the number of sectors on which write defect correction is to be performed.

Abstract: A method begins by a processing module receiving a first request to store a program. The method continues with the processing module determining first error coding dispersal storage function parameters and encoding a data segment of the program. The method continues with the processing module determining whether a second request to store the program is received. The method continues with the processing module encoding a second data segment of the program in accordance with the first error coding dispersal storage function parameters when the second request is not received. The method continues with the processing module changing the first error coding dispersal storage function parameters based on the another request to produce second error coding dispersal storage function parameters when the second request is received. The method continues with the processing module encoding the second data segment in accordance with the second error coding dispersal storage function parameters.

Abstract: An LDPC coding system includes a number of LDPC encoders and a number of LDPC decoders. The number of encoders/decoders is between one and one fewer than the total number of tracks on the high density tape are provided. The LDPC encoders are operable to break data from an incoming data sector into the data blocks to be written to the high density tape. The LDPC decoders are operable to assemble the data blocks into data sectors.

Abstract: A method begins by a dispersed storage processing module obtaining data for storage. The method continues with the dispersed storage processing module soliciting dispersed storage (DS) units to store encoded data slices of the data. The method continues with the dispersed storage processing module receiving favorable responses from a set of DS units. The method continues with the dispersed storage processing module encoding the data in accordance with an error coding dispersal storage function and in accordance with the favorable responses.

Abstract: A method and apparatus for distributing dynamically reconfigurable content to a mobile device is provided. One embodiment of a method for encoding a data stream to enable error correction by a receiver of the data stream includes storing a block of the data stream in a first memory array, processing the first memory array to produce a second memory array, inverting the second memory array, and storing the second memory array, as inverted, as a third memory array.

Abstract: The present disclosure includes methods, devices, and systems for error detection/correction based memory management. One embodiment includes performing a read operation with respect to a particular group of memory cells of a memory device and, if the read operation results in an uncorrectable error, determining whether to retire the particular group of memory cells in response to a status of an indicator corresponding to the particular group of memory cells, wherein the status of the indicator indicates whether the particular group of memory cells has a previous uncorrectable error associated therewith.

Abstract: A semiconductor memory device includes a memory array, an error correction code circuit, and a timing control signal generator configured to, based on a first timing control signal used to control a timing at which data to be input to the error correction code circuit is transferred to the error correction code circuit, generate a second timing control signal used to control a timing at which data output from the error correction code circuit is transferred to another circuit. The timing control signal generator includes a circuit which is the same as or corresponds to at least a portion of the error correction code circuit, and is configured to delay a timing of the first timing control signal by a period of time corresponding to a delay time of the error correction code circuit, and output the second timing control signal, depending on the delayed timing.

Abstract: A nonvolatile memory device comprises a memory cell array configured to store one or more bits per memory cell, a read and write circuit configured to access the memory cell array, a control logic component configured to control the read and write circuit to sequentially execute read operations of a selected memory cell at least twice to output a read data symbol, and an error correcting unit configured to correct an error in the read data symbol based on a pattern of the read data symbol to output an error-corrected symbol.

Abstract: Regular chip packages that store user data therein and error-correction chip packages that store an error correction code therein are mounted on a module substrate. The module substrate has first and second mounting areas of different coordinates in an X direction, and the second mounting area has third and fourth mounting areas of different Y coordinates. The regular packages are oppositely arranged in the first mounting area on a surface and the back surface of the module substrate. The error-correction chip packages are oppositely arranged in the third mounting area on the surface and the back surface of the module substrate. A memory buffer that buffers user data and an error correction code is arranged in the fourth mounting area.

Abstract: A data processing system, a turbo decoding system, an address generator and a method of reconfiguring a turbo decoding method is provided. The data processing system (101) comprises the turbo decoding system (100). The turbo decoding system (100) comprises electronic circuits. The electronic circuits comprises: a memory (108), the address generator (102), and a Soft Input Soft Output decoder (106). The address generator (102) is operative to produce a sequence of addresses according to an interleaving scheme. The address generator can support multiple interleaving schemes. The address generator (102) is operative to receive reconfiguration information. The address generator (102) is operative to reconfigure during operational use the interleaving scheme in dependency on the reconfiguration information.

Abstract: A memory system in an embodiment having a host and a memory card, including: a plurality of semiconductor memory cells, each cell being configured to store N-bit coded data based on threshold voltage distributions; an LLR table storage section configured to store a first LLR table that consists of normal LLR data corresponding to predetermined threshold voltages and a second LLR table that consists of LLR data such that two LLRs at each location corresponding to each location in the first LLR table at which a sign is inverted between two adjacent LLRs are “0”; and a decoder configured to perform decoding processing through probability-based repeated calculations using an LLR.

Abstract: A method of generating a Tanner graph includes generating a pseudo-random parameter and selecting a subgraph within the Tanner graph to be designed, and assigning new edges to the subgraph as a function of the value of the pseudo-random parameter and as a function of prior edges, if any, that have been assigned to the subgraph. The method detects whether the subgraph contains a common feature indicative of a trapping set or sets to be avoided during generation of the Tanner graph until either the common feature is not detected or all possible combination of edges have been assigned to the subgraph. The subgraph containing no occurrences of the common feature is included as part of the Tanner graph or one of combinations is selected as the subgraph and is included as part of the Tanner graph. These operations are repeated until the entire Tanner graph is generated.

Abstract: A turbo decoding device includes a memory unit that stores data in an interleaving process performed in a process of decoding a coded signal encoded with a turbo code and an access unit that accesses the memory unit to read and write the data. The memory unit includes memory circuits and is formed as one memory space by coupling the memory circuits. Furthermore, the memory circuit functions as a first bank configuration by which a first capacity is assigned to each bank or a second bank configuration by which a second capacity is assigned to each bank in accordance with a combination of the memory circuits. Moreover, the access unit selects by which of the first bank configuration and the second bank configuration the memory unit functions in accordance with a communication method of a coded signal and accesses the memory unit in accordance with the selected bank configuration.

Abstract: To allow a single LDPC decoder to operate on both 512 B blocks and 4 KB blocks with comparable error correction performance, 512 KB blocks are interlaced to form a 1 KB data sequence, and four sequential 1 KB data sequences are concatenated to form a 4 KB sector. A de-interlacer between the detector and decoder forms multiple data sequence from a single data sequence output by the detector. The multiple data sequences are separately processed by a de-interleaver between the de-interlacer and the LDPC decoder, by the LDPC decoder, and by an interleaver at the output of the LDPD decoder. An interlacer recombines the multiple data sequences into a single output. Diversity may be improved by feeding interleaver seeds for respective codewords into the de-interleaver and interleaver during processing.

Abstract: A storage device and data processing method thereof is described. The invention provides different ECC for different memory pages. The storage device uses the long-bit ECC for easy interference page, and uses the short-bit ECC for hard interference page. Therefore, the accuracy of the data is maintained and the reading/writing speed is increased.

Abstract: The present invention presents methods for improving data relocation operations. In one aspect, rather than check the quality of the data based on its associated error correction code (ECC) in every relocation operation, it is determined whether to check ECC based on predetermined selection criteria, and if ECC checking is not selected, causing the memory to perform an on-chip copy the data from a first location to a second location. If ECC checking is selected, the data is transferred to the controller and checked; when an error is found, a correction operation is performed and when no error is found, an on-chip copy is performed. The predetermined selection criteria may comprise a sampling mechanism, which may be random based or deterministic. In another aspect, data transfer flags are introduced to indicate data has been corrected and should be transferred back to the memory. A further aspect considers the header and user data separately if each has a distinct associated ECC.

Abstract: A memory system having a memory card configured to store frame data composed of a plurality of pieces of sector data and a host configured to send and receive the frame data to and from the memory card, the memory card includes: an ECC1 decoder configured to perform BCH decoding processing with a hard decision code on a sector data basis; an ECC2 decoder configured to perform LDPC decoding processing with an LDPC code on a frame data basis; a sector error flag section configured to store information about presence or absence of error data in the BCH decoding processing; and an ECC control section configured to perform, in the LDPC decoding processing, control of increasing a reliability of sector data containing no error data based on the information in the sector error flag section.

Abstract: Disclosed herein is a nonvolatile memory apparatus including, a nonvolatile memory section, a standard error correction code processing section, an extended error correction code processing section, and a control section.

Abstract: A memory system includes a memory array. The memory array includes a plurality of storage locations arranged in rows and columns. The memory system includes error correction circuitry that generates correct data bits from data bits of the memory array and error correction bits. The data bits received by the error correction circuitry are divided in subgroups where each subgroup of data bits is used to generate a subgroup of the correct data bits. The subgroups of data bits are stored in a row of the memory array at locations that are interleaved with each other.

Abstract: An embodiment may include circuitry that may detect and/or correct at least one error in a data codeword that may include a data word, cyclical redundancy check (CRC) word, and parity word. The circuitry may select whether a portion of the CRC word indicates whether only a single processor has accessed the data word. The data word, CRC word, and the parity word may be accessible in respective distinct memory device sets that each may include one or more respective memory devices. If the circuitry detects, based at least in part upon the data codeword and CRC word, a CRC error, and the at least one error includes fewer than a first predetermined number of errors, the circuitry may determine in which of the one or more respective memory devices in the memory device sets the at least one error resides and may correct the at least one error.

Abstract: An integrated circuit is provided with an array of multilevel flash memory cells. In one embodiment these flash memory cells have a storage signal level which is Gray coded to output data bits thereby increasing the independence between bit errors. The error correction circuitry targets independent identical distributed error patterns. In another embodiment, the storage signal levels are read to generate n-bit symbols which are then subject to error correction with an error correction mechanism targeted at the error properties of those n-bit symbols. The data is read in sets of symbols such that the error correction targeted at those symbols will be more efficient.

Abstract: In a particular embodiment, a data storage device includes a memory array including a target memory cell and one or more other memory cells. The data storage device also includes a controller coupled to the memory array. The controller is configured to directly compute a reliability measure for at least one bit stored in the target memory cell of the memory array based on a voltage value associated with the target memory cell and based on one or more corresponding voltage values associated with each of the one or more other memory cells of the memory array.

Abstract: Various embodiments of the present invention provide systems, methods and circuits for memories and utilization thereof. As one example, a memory system is disclosed that includes a flash memory device and a flash access circuit. The flash access circuit is operable to perform an error code encoding algorithm on a data set to yield an error code, to write the data set to the flash memory device at a first location, and to write the error code to the flash memory device at a second location.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes an error correction code block and a memory. The error correction code block performs error correction encoding for user data to generate parity data. The memory stores the user data and the parity data. The error correction code block generates parity data, including a number of bits equal to at least 2t, wherein t is a natural number, and the bits of the parity data distinguish free page data from user data that is equal to the free page data.

Abstract: A voltage regulating method applied to a memory to regulate a word line voltage corresponding to a set of memory cells of the memory comprises the following steps. Firstly, a first value, which is for indicating an amount of data having a specific data value in a set of written data, is counted, wherein the set of written data is written into the set of memory cells. Next, a second value, which is for indicating an amount of data having the specific data value in a set of read data, is counted, wherein the set of read data is obtained by reading the set of written data. Then, a regulating voltage is determined according to a difference between the first and second values. After that, the word line voltage is regulated to be a sum of the word line voltage and the regulating voltage.

Abstract: A data programming method and a system thereof are provided to program an original data into a memory. In the method, the original data complying with a first data arrangement rule is converted into an intermediate data complying with a second data arrangement rule, wherein the second arrangement rule corresponds to a type of the memory. Next, the intermediate data is analyzed to obtain at least one failure area which causes program disturb, and the content of the at least one failure area is replaced by a corresponding adjustment code. The replaced intermediate data is encoded, and a corresponding encoding information is generated. After the encoded intermediate data and the encoding information are both converted into a non-failure data complying with the first data arrangement rule, the non-failure data is programmed into the memory.

Abstract: A method for execution by a DS storage unit begins with the DS storage unit receiving an encoded slice of a plurality of encoded slices, wherein the plurality of encoded slices was generated from a data segment using an error encoding function. The method continues with the DS storage unit determining whether the encoded slice is to be sub-sliced using a sub-slicing encoding function. The method continues with the DS storage unit generating a plurality of encoded sub-slices from the encoded slices using the encoded sub-slicing encoding function when the encoded slice is to be sub-sliced. The method continues with the DS storage unit outputting the plurality of encoded sub-slices to a plurality of DS storage units.

Abstract: To provide a Chien search device and a Chien search method capable of performing a Chien search process at a high speed. The Chien search device calculates an error position at the time of correcting an error included in data read from a nonvolatile memory, and includes a first processing unit that performs a search process of an error position in at least one-bit unit to an error-correction area of input data, and a second processing unit that processes at one time plural bits in an non-error-correction-target area of the input data.

Abstract: Systems and methods to respond to error detection are provided. First data may be received at a first memory controller port in response to a read command issued from the first memory controller port. The read command may be issued as a second read command from a second memory controller port after determining that the first data contains a first uncorrectable error. Second data may be received at the second memory controller port in response to the second read command. A repair write command may be issued from the first memory controller port after determining that the second data does not contain any errors. The repair write command may initiate writing the second data from the first memory controller port.

Abstract: Methods and apparatus for performing parity and/or ECC operations are disclosed. An example method includes determining that an opcode is being transmitted on a bus and determining if the transmitted opcode is a memory operation. In the event the transmitted opcode is a memory write operation, the example method includes calculating a parity bit for data associated with the opcode, writing the calculated parity bit to a parity table and writing the data to a memory. The example method also includes, in the event the transmitted opcode is the memory read operation, recovering data from a previously written memory, calculating a parity bit for the recovered data, recovering a previously stored parity bit for the recovered data, comparing the parity bit for the recovered data with the previously stored parity bit and, in the event the recovered data parity bit does not match the previously stored parity bit, providing an error notification.

Abstract: Methods, systems, and devices are described for forward error correction for flash memory. Encoded data from flash memory may be used to generate a number of data streams. At each of a number of error detection sub-modules operating in parallel, a different one of the data streams is processed. Each error detection sub-module may detect whether a portion of the respective received stream contains an error, and forward the portion to an error correction module. The error correction module, physically separate from the error detection sub-modules, may correct the forwarded portions of the respective received streams containing an error. The age and error rate associated with the flash memory may be monitored, and a coding rate or other aspects may be dynamically adapted to account for these factors.

Abstract: Redundancy including extra rows and/or columns of memory cells is added to the memory, and ECC parity is used to detect errors. When an error occurs at a location the first time, it is assumed to be a soft error, the data is corrected in this location, and the address of the erroneous cell (e.g., the failed address) is stored in a list. When another error occurs, it is determined whether its failed address is on the stored list. If it is not, then the error is again assumed to be a soft error, the data at this location is corrected, and the failed address is added to the stored address list, etc. If, however, the failed address is already in the stored failed address list, the error is considered either a latent error or VTR, and is repaired on the fly using on-chip redundancy.

Abstract: The embodiments described herein provide a controller and method for providing status and spare block management information in a flash memory system, as well for managing spare block allocation in cooperation with a host. In one embodiment, a controller receives a command from a host, retrieves data from flash memory, analyzes the retrieved data for errors, and transmits status information to the host, wherein the status information comprises information based on a result of the error analysis, such as a read error. Alternatively, the controller stores the status information and transmits an error indicator to the host identifying that the status information regarding the error is available in memory. In another embodiment, the controller may be reselectably initialized to one of a plurality of spare block management modes, wherein in a split management mode, the controller may ask the host to return extra blocks available to the host.

Abstract: The invention provides a data storage device. In one embodiment, the data storage device comprises a memory and a controller. The memory is for data storage. When the data storage device receives first source data to be written to the memory from a host, the controller generates at least one first input data according to the first source data, scrambles the first input data according to a plurality of pseudo random sequences to obtain a plurality of first scrambled signals, calculates a plurality of transmission powers of the first scrambled signals, and selects a target scrambled signal with a lowest transmission power to be stored in the memory from the first scrambled signals.

Abstract: A method for adaptively applying an error-correcting code to a storage device is disclosed. A determination is made that a system is in an idle state of input/output requests. First data symbols are copied into a first location within a buffer. First data symbol errors corrected using a first error-correcting code. Second data symbols including corrected bits are written in a second location on the recording media with a second error-correcting code. An error number for the second data symbols in the second location is determined. If the error number is below a first threshold error number, the first data symbols are deleted. If the error number is above the first threshold error number, the second data symbols are deleted.

Abstract: A nonvolatile random access memory includes: a nonvolatile storage area that is randomly accessible and includes a data area to store data and an error-correcting-code area to store an error correcting code, the data area including at least one data area to which a data area unit size is assigned, the error-correcting-code area including at least one error-correcting-code area to which an error-correcting-code-area unit size is assigned; and a nonvolatile storage area controller to set a data size used when the at least one data area is accessed, as the data area unit size. The nonvolatile storage area controller manages the data area and the error-correcting-code area based on the set data area unit size and assigns the at least one error-correcting-code area with the error-correcting-code-area unit size to the at least one data area with the data area unit size based on the data area unit size.

Abstract: A semiconductor memory system includes a memory area and an error-correcting (ECC) circuit. The memory area includes a plurality of cells, and the ECC circuit is configured to determine whether uncorrectable error data exists or not by using a parity according to cell data of the memory area in a read mode and a parity according to an encoding result of corrected data of the cell data.

Abstract: A memory controller comprises at least a memory control processing module and/or a distributed storage processing module. A method begins by the memory control processing module receiving a memory access request regarding a data segment. The method continues with the memory control processing module interpreting the memory access request to determine whether an error coding dispersal function of the data segment is applicable. The method continues with the memory control processing module sending the memory access request to the distributed storage processing module when the error coding dispersal function is applicable. The method continues with the distributed storage processing module performing the error coding dispersal function on the data segment to produce an error coded processed data segment. The method continues with the distributed storage processing module sending the error coded processed data segment to the memory control processing module.

Abstract: An error correction circuit 1 in accordance with an aspect of the invention includes an associative memory 20, a logic circuit 10 disposed in parallel with the associative memory 20, and selection unit 30 that receives an output signal from the associative memory 20 and an output signal from the logic circuit 10 as an input. The associative memory 20 includes a table that handles an input signal as a word and holds an output signal related to the word and an error correction code used to correct the output signal as data. The associative memory 20 further includes error correction unit that outputs a signal in which an error was corrected based on data related to a word corresponding to an input signal. The selection unit 30 selects and outputs one of an output signal from the associative memory 20 and an output signal from the logic circuit 10.