Abstract: A memory element array includes plural memory elements capable of storing M-value data (M is a natural number not smaller than 2). Among first to M-th data, the first data gives a largest physical impact on memory elements. A data processing unit can execute a data process on an aggregate of program data stored in a data storing unit. It is determined that which of the first to the M-th data is least existing data, the number of pieces of which is the smallest in the aggregate of the program data. When the least existing data is other than the first data, the least existing data in the aggregate of program data is replaced with the first data, and the first data with the least existing data. When the least existing data is the first data, the aggregate of program data is maintained without any data replacement.

Abstract: A method for enhancing error correction capability of a controller of a memory device without increasing an Error Correction Code (ECC) engine encoding/decoding bit count includes: regarding a plurality of rows of a data bit array, respectively calculating a plurality of first parity codes; regarding a plurality of sets of columns of the data bit array, respectively calculating a plurality of second parity codes, wherein each set of the sets includes two or more of the columns, and the sets do not overlap; and performing encoding/decoding corresponding to the first and the second parity codes. An associated memory device and the controller thereof are further provided.

Abstract: In a storage apparatus: a write-address counter outputs a write address; an input-data inverter inverts input data to be inputted into a storage unit; an input-data selector selects one of the input data and the inverted input data on the basis of one or more first bits constituting the write address, and writes the one of the input data and the inverted input data in the storage unit on the basis of one or more second bits constituting the write address; a read-address counter outputs the read address; an output-data inverter inverts output data outputted from the storage unit on the basis of one or more third bits constituting the read address; and an output-data selector selects and outputs one of the output data and the inverted output data on the basis of one or more fourth bits constituting the read address.

Abstract: Methods and apparatus for soft data generation for memory devices using decoder performance feedback. At least one soft data value is generated in a memory device, by obtaining performance feedback from a decoder; obtaining an error statistic based on the performance feedback; and generating the at least one soft data value based on the obtained error statistic. The performance feedback comprises one or more of decoded bits, a number of erroneous bits based on data decoded by the decoder and a number of unsatisfied parity checks.

Abstract: According to one embodiment, a memory system includes a semiconductor memory, a converter configured to convert an input data input from the semiconductor memory into a log likelihood ratio based on a conversion function, a conversion function optimizing unit configured to optimize the conversion function used for the converter, and a decoding operation unit configured to input the log likelihood ratio output from the converter to execute a decoding operation of an error correcting code. The conversion function optimizing unit optimizes the conversion function based on information related to a number of times of using the semiconductor memory.

Abstract: This can relate to non-regular parity distribution of a non-volatile memory (“NVM”), such as flash memory, and detection of the non-regular parity via a metadata tag. For example, each codeword of the NVM can include one or more parity pages that may be distributed at random through the NVM. To identify the page as a parity page, a parity page marker can be included in the metadata of that page. During power-up of the NVM, an address table including the logical-to-physical address mapping of the pages can be created. Pages including a parity page marker, however, can be skipped during the creation of this address table. Additionally, by having two or more parity pages associated with a codeword, an additional layer of protection can be provided for repairing errors in that codeword.

Abstract: A method begins by a processing module determining a performance based indication regarding storage of a data segment as a set of encoded data slices and comparing the performance based indication with a performance threshold. When the performance based indication compares unfavorably with the performance threshold, the method continues with the processing module decoding the set of encoded data slices to reproduce the data segment, adjusting error coding dispersal storage function parameters based on the unfavorable comparison of the performance based indication with the performance threshold to produce performance adjusted error coding dispersal storage function parameters, encoding the reproduced data segment in accordance with the performance adjusted error coding dispersal storage function parameters to produce a second set of encoded data slices, and selecting a storage set of encoded data slices from the set of encoded data slices and the second set of encoded data slices.

Abstract: An error correcting method for a memory chip is provided. The memory chip has a plurality of physical blocks, each of the physical blocks has a plurality of physical pages, and the physical pages belonging to the same physical block are individually written and simultaneously erased. The error correcting method includes sequentially writing a plurality of data into the physical pages of a first physical block and generating a parity information according to the data. The error correcting method further includes writing the parity information into one of the physical pages of the first physical block following the data and correcting the data in the first physical block according to the parity information. Accordingly, the parity information can be used for correcting error bits in the data when an error checking and correcting circuit can not correct the error bits. Thereby, the error correcting ability is enhanced.

Abstract: A static RAM redundancy memory for use in combination with a non-volatile memory array, such as ferroelectric RAM (FRAM), in which the power consumption of the SRAM redundancy memory is reduced. Each word of the redundancy memory includes data bit cells for storing addresses of memory cells in the FRAM array to be replaced by redundant elements, and also enable bits indicating whether redundancy is enabled for those addresses. A logical combination of the enable bits in a given word determines whether the data bit cells in that word are powered-up. As a result, the power consumption of the redundancy memory is reduced to the extent that redundancy is not enabled for segments of the FRAM array.

Abstract: According to one embodiment, an error correction decoding apparatus including a hard-decision decoding module which performs hard-decision decoding using a signal with 2 levels per bit as input data and runs a parity check on the input data, a soft-decision decoding module which performs soft-decision decoding using a signal with the number of multiple levels per bit larger than 2 as input data, a start-up control module which controls the start-up of each of the decoding modules, and an output selection module which selects one of the output signals of the decoding modules. The start-up control module causes the output selection module to select the decoding result of the hard-decision decoding module when the parity errors is a permitted value and causes the output selection module to select the decoding result of the soft-decision decoding module when the parity errors has exceeded the permitted value.

Abstract: Methods, devices and computer readable code for reading data from one or more flash memory cells, and for recovering from read errors are disclosed. In some embodiments, in the event of an error correction failure by an error detection and correction module, the flash memory cells are re-read at least once using one or more modified reference voltages, for example, until a successful error correction may be carried out. In some embodiments, after successful error correction a subsequent read request is handled without re-writing data (for example, reliable values of the read data) to the flash memory cells in the interim. In some embodiments, reference voltages associated with a reading where errors are corrected may be stored in memory, and retrieved when responding to a subsequent read request. In some embodiments, the modified reference voltages are predetermined reference voltages.

Abstract: An electronic circuit (200) for use with an accessing circuit (110) that supplies a given address and a partial write data portion and also has dummy cycles. The electronic circuit (200) includes a memory circuit (230) accessible at addresses, an address buffer (410), a data buffer (440) coupled to the memory circuit (230), and a control circuit (246) operable in the dummy cycles to read data from the memory circuit (230) to the data buffer (440) from a next address location in the memory circuit (230) and to store that next address in the address buffer (410).

Abstract: A method for operating a memory (28) includes storing data, which is encoded with an Error Correction Code (ECC), in analog memory cells (32) of the memory by writing respective analog input values selected from a set of nominal values to the analog memory cells. The stored data is read by performing multiple read operations that compare analog output values of the analog memory cells to different, respective read thresholds so as to produce multiple comparison results for each of the analog memory cells. At least two of the read thresholds are positioned between a pair of the nominal values that are adjacent to one another in the set of the nominal values. Soft metrics are computed responsively to the multiple comparison results. The ECC is decoded using the soft metrics, so as to extract the data stored in the analog memory cells.

Abstract: A decoder includes a first decoder configured to iteratively decode input data, accumulate iteratively decoded data in bit units, compare an accumulated value obtained for each bit of the iteratively decoded data with a plurality of reference values, and output decision data and indicator data according to a comparison result. The decoder includes a second decoder configured to perform error correction on a symbol including the decision data according to the indicator data.

Abstract: An method of operating a memory system including a nonvolatile memory device and a controller. The method includes receiving a source word, converting the received source word to a codeword, and programming the converted codeword in the nonvolatile memory device. A length of the converted codeword can be greater than a length of the received source word, and a difference between the numbers of first and second digital bits of the converted codeword can be less than a reference value.

Abstract: A decoding device comprises two check node processing devices of feedback shift register type, each of which node processing includes a plurality of registers and a plurality of comparator circuits. A multiplexer and a demultiplexer switch between the two check node processing devices, and a memory holds the two sorts of data. The comparator circuits are interposed between registers of the check node processing device.

Abstract: A semiconductor integrated circuit pertaining to the present invention comprises a plurality of storage elements for storing and holding an input signal, a majority circuit that outputs a result of a majority decision of outputs from the plurality of storage elements; an error detector circuit that detects a mismatch among the outputs of the plurality of storage elements and outputs error signals; and a monitor circuit that monitors the error signals from the error detector circuit, wherein the monitor circuit, based on the error signals, orders a refresh action that rewrites data for rectification to a storage element in which an output mismatch occurs out of the plurality of storage elements and, if rewrite and rectification by the refresh action are unsuccessful, sends a notification to an external unit or process.

Abstract: A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data.

Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

Abstract: Methods of operating nonvolatile memory devices include testing a plurality of strings of nonvolatile memory cells in the memory device to identify at least one weak string therein having a higher probability of yielding erroneous read data error relative to other ones of the plurality of strings. An identity of the at least one weak string may be stored as weak column information. This weak column information may be used to facilitate error detection and correction operations. In particular, an error correction operation may be performed on a first plurality of bits of data read from the plurality of strings using an algorithm that modifies a weighting of the reliability of one or more data bits in the first plurality of bits of data based on the weak column information. More specifically, an algorithm may be used that interprets a bit of data read from the at least one weak string as having a relatively reduced reliability relative to other ones of the first plurality of data bits.

Abstract: Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a memory unit configured to receive data flow from two directions. The memory unit can be configured serially in a chain with other memory units. The chain can include an error check and correcting unit (ECC). Additional apparatus, systems, and methods are disclosed.

Abstract: The non-volatile memory system includes a non-volatile memory and a controller. The non-volatile memory includes a data region including a sector region for storing sector data, and an uncorrectable information region for storing uncorrectable sector information on the sector region. The controller includes an information generation unit for generating the uncorrectable sector information that indicates whether the sector region is assigned to an uncorrectable sector region, according to a command output from a host.

Abstract: A receiver to receive a signal associated with a low-density parity-check (LDPC) code. The receiver includes a memory device, an address generator, and an LDPC decoder. The LDPC decoder includes a row designator and a position designator. The memory device stores data related to an LDPC decoding process. The address generator generates an access address to the stored data. The LDPC decoder performs the LDPC decoding process. The row designator designates a row from a parity-check matrix as a parent row and designates a plurality of corresponding rows from the parity-check matrix as child rows. The position designator designates an original position order of each parent non-zero element of 10 the parent row according to an actual position order of each parent non-zero element in the parent row. The actual position order includes a numerical order of the parent non-zero elements.

Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

Abstract: When coding user data, it may be desirable to mark user data as invalid. This may arise, by way of example, in applications in which a stored data item needs to be updated by virtue of an updated data item additionally being stored and the old stored data item being marked as invalid. In order to mark the invalidity of a stored data item by means of the value of the data item and to be able to apply an error-recognizing or error-correcting coding dependably, the user data are extended by supplementary data and the coding is applied to the extended user data.

Abstract: In processing quasi-cyclic low-density parity-check (QC-LDPC) data, an input signal is received which includes decision and reliability information corresponding to unpadded data. Decision and reliability information corresponding to padded data is introduced into the input signal. Message passing is performed one or more times to obtain decoded data. This includes using (1) the decision and reliability information corresponding to the unpadded data and (2) the decision and reliability information corresponding to the padded data, where a preference is given to the decision and reliability information corresponding to the padded data over the decision and reliability information corresponding to the padded data during message passing. Zero padding is removed from the decoded data.

Abstract: Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.

Abstract: An apparatus includes a memory that is allocated to reported portions and overprovisioned portions. The apparatus includes an error correction circuit that communicates with the memory in error correction coded data that has a controllable ECC length. The ECC length is a function of a history of error reports. A memory allocation engine balances a size of the overprovisioned portions to maintain a size of the reported portions. The balancing is performed as a function of an average of ECC lengths in the ECC length table over a time interval in which a size of the memory decreases with accumulated erase cycles of the memory.

Abstract: A memory device includes an error detection and correction system with an error correcting code over GF(2n), wherein the system has an operation circuit configured to execute addition/subtraction with modulo 2n?1, and wherein the operation circuit has a first operation part for performing addition/subtraction with modulo M and a second operation part for performing addition/subtraction with modulo N (where, M and N are integers which are prime with each other as being obtained by factorizing 2n?1), and wherein the first and second operation parts perform addition/subtraction in parallel to output an operation result of the addition/subtraction with modulo 2n?1.

Abstract: A method begins by a processing module receiving a data storage request that includes metadata and data. The method continues with the processing module determining a base-line set of error coding dispersal storage function parameters based on the metadata. The method continues with the processing module identifying candidate dispersed storage (DS) units based on the base-line set of error coding dispersal storage function parameters. The method continues with the processing module selecting DS units of the candidate DS units based on the metadata to produce selected DS units. The method continues with the processing module dispersed storage error encoding the data in accordance with at least a representation of the base-line set of error coding dispersal storage function parameters to produce a set of encoded data slices. The method continues with the processing module sending the set of encoded data slices to the selected DS units for storage therein.

Abstract: Data is read from a memory array. Before being stored in a data buffer, a Hamming code detection operation and a Reed-Solomon code detection operation are operated in parallel to determine if the data word has any errors. The results of the parallel detection operations are communicated to a controller circuit. If an error is present that can be corrected by the Hamming code correction operation, this is performed and the Reed-Solomon code detection operation is performed on the corrected word. If the error is uncorrectable by the Hamming code, the Reed-Solomon code correction operation is performed on the word.

Abstract: Data storage control circuitry for controlling storage and retrieval of data in a data store in which data is stored in data blocks. A group data store stores data by grouping together blocks that have at least one faulty bit into groups of at least two blocks. For each group of blocks at least one of the blocks has a non-faulty bit for each of the bit locations in the blocks. A selector data store stores indicators for each group indicating which bits of the blocks within a group are the non-faulty bits. When storing data to a data block within a group, the data is stored in each of the blocks within the group. When retrieving data from a data block within a group, the data is read from respective bits of the blocks within the group as indicated by the indicators.

Abstract: A nonvolatile memory device comprises overwritable memory cells. In an overwrite operation, data is read from a selected region of the nonvolatile memory device and combined with overwrite data to produce combined data. An error correction code is then generated for the combined data and the overwrite data and the error correction code are stored in the selected region.

Abstract: A memory utilization method of low density parity check code (LDPC), a LDPC decoding method and a decoding apparatus thereof are provided, applicable for a decoding process in a wireless receiver. The memory utilization method of LDPC includes the following steps. First, variable node processes (VNPs) or check node processes (CNPs) required to be executed at a same time stage are determined. Next, the VNPs or the CNPs executed at the same time stage are allocated in different VNP groups or different CNP groups. Further, a folding factor of memory units is determined according to a desired data throughput. Then, according to the folding factor and the allocated VNP groups or the allocated CNP groups, the memory units are connected serially as a plurality of parallel processing memory modules.

Abstract: A method for checking reading errors of a memory includes the following steps. A first data fragment is received. A first count index according to the first data fragment is generated, wherein the first count index is corresponding to a quantity of one kind of binary value in the first data fragment. The first data fragment is written into the memory. The first data fragment is read from the memory as a second data fragment. A second count index is generated according to the second data fragment. The first count index is compared with the second count index.

Abstract: A semiconductor storage system includes: a memory region having a plurality of memory cells; and a memory controller having a data control unit. The data control unit includes a write control unit which, during a write operation, performs first error check correction (ECC) encoding on an input data to generate a first encoded input data, compresses the first encoded input data to generate a compressed input data, and performs second ECC encoding on the compressed input data to generate a second encoded input data. The write control unit then writes the second encoded input data into the memory region as a write data.

Abstract: A method of RAID migration comprising reading first and second blocks from a first RAID array. Said first blocks are written to a second RAID array within a first write cycle. Said second blocks are read simultaneously with a portion of said first write cycle in a pipelined fashion. In a first embodiment, pipelining increases the speed of RAID migration from a one-disk stripe array to a two-disk mirror array. In a second embodiment, pipelining and the use of duplicate blocks increases the speed of RAID migration from a two-disk mirror array to a three-disk RAID 5 array. In a third embodiment, pipelining and the use of duplicate blocks increases the speed of RAID migration from a three-disk RAID 5 array to a four-disk RAID 5 array.

Abstract: A storage apparatus includes: a host control unit for sending/receiving data to/from a host server; a drive control unit for sending/receiving the data to/from a storage device; a cache memory for temporarily storing the data sent and received between the host control unit and the drive control unit; a switch for switching between a transfer source and a transfer destination when transferring the data by selecting the transfer source and the transfer destination from among the host control unit, the cache memory, and the drive control unit; and a controller for controlling the host control unit, the drive control unit, and the switch; wherein processing for generating an error check code for the data and error check processing using the error check code are executed by the switch or are distributed among and executed by the host control unit, the drive control unit, the switch, and the controller.

Abstract: A data writing method for a flash memory, and a flash memory controller and a flash memory storage apparatus using the same are provided. First, data is received from a host system. Next, the data is divided into at least one frame. Afterwards, an error checking and correcting (ECC) code corresponding to the frame is generated so as to form at least one ECC frame. Then, the ECC frame is divided into a plurality of frame segments. Finally, the frame segments are written into a flash memory chip according to a non-sequentially ranking order.

Abstract: Systems and processes may be used to retrieve metadata from a nonvolatile memory of a portable device and transmit the retrieved metadata to an external host. Metadata may be analyzed using the external host and/or at least a portion of the metadata may be modified based on the analysis. Modified metadata may be transmitted from the external host to a memory controller of the host.

Abstract: Provided is a Forward Error Correction (FEC) encoding method of a variable-length packet using a three-dimensional (3D) storage apparatus. In the FEC encoding method, an FEC coding may be performed to calculate a corresponding parity packet while an input data packet is imaginarily connected to the 3D storage apparatus having a predetermined storage width and data area height to be arranged, the calculated parity packet may be stored and arranged in a vertical direction and a depth direction of the 3D storage apparatus, and an expansion data packet including both information for restoration of a data packet and the data packet may be transmitted together with the parity packet.

Abstract: A controller coupled to a memory array includes an error correction coding (ECC) engine and an ECC enhancement compression module coupled to the ECC engine. The ECC enhancement compression module is configured to receive and compress control data to be provided to the ECC engine to be encoded. Compressed encoded control data generated at the ECC engine is stored as a codeword at the memory array.

Abstract: A disk drive for encrypting user data. A motor configured to rotate a disk which stores encoded user data and an encryption flag which has not been encoded. An encoder/decoder processor configured to encode the user data that is written into the disk without encoding the encryption flag, and decodes the user data that is read out from the disk without decoding the encryption flag that is read out from the disk. An encryption processor configured to encrypt the user data at the encryption flag, wherein the encryption flag indicates encryption before the encoder/decoder processor starts encoding, and wherein the encryption processor obtains an encryption flag read out from the disk before the encoder/decoder processor completes decoding of the user data read out from the disk, commencing decryption of decoded data where the encryption flag indicates encryption before decoding of the user data is complete.

Abstract: Storing, retrieving, transmitting and receiving data (20) by a) separating the data into a plurality of data subsets (A, B); b) generating parity data (P) from the plurality of data subsets (A, B) such that any one or more of the plurality of data subsets may be recreated from the remaining data subsets and the parity data (P). Steps a and b may be repeated on any one or more each of the plurality of data subsets and parity data providing further data subsets and further parity data; and d) storing each of the further data subsets and further parity data in separate storage locations (380) or transmitting the further data subsets and further parity data.

Abstract: Methods and apparatuses for including synchronization data to be used for parallel processing in a block of data having error correcting code symbols. The block of data is encoded using an error correcting code. The resulting encoding includes three check symbols per 32 data symbols. At least one synchronization symbol corresponding to the data symbols is generated. The data symbols, the check symbols and the at least one synchronization symbol are combined. The combined data symbols, the check symbols and the at least one synchronization symbol are transmitted.

Abstract: Systems, methods, and other embodiments associated with soft decoding for a quantized channel are described. According to one embodiment, an apparatus includes a soft decoder configured to decode a signal received from a quantized channel based, at least in part, on one or more log likelihood ratios (LLRs). The apparatus may also include a reliability memory configured to store one or more known LLRs, and a controller configured to repetitively and selectively provide the soft decoder with known LLRs chosen from the reliability memory, to control the soft decoder to decode the signal, and to selectively update the reliability memory upon determining that the soft decoder successfully decoded the signal.

Abstract: A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device. The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller also causes a flag bit having a first value to be stored in the DRAM device when a corresponding ECC syndrome is stored. The ECC controller changes the flag bit to a second value whenever the corresponding data bits are modified, this indicating that the stored syndrome no longer corresponds to the stored data. In such case, the ECC controller causes a new ECC syndrome to be generated and stored, and the corresponding flag bit is reset to the first value. The flag bits may be checked in this manner during a reduced power refresh to ensure that the stored syndromes correspond to the stored data.

Abstract: A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first set can be refreshed at a relatively slow rate to reduce the power consumed by the DRAM device. Error checking and correcting circuitry in the DRAM device corrects any data retention errors in the first set of memory cells caused by the relatively slow refresh rate. The memory cells in the second set are refreshed at a normal rate, which is fast enough that data retention errors do not occur. A mode register in the DRAM device may be programmed to select the size of the second set of memory cells.

Abstract: According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area.