Abstract: Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.

Abstract: Embodiments of the present disclosure relate to a system and method for testing an embedded circuit in a semiconductor arrangement as part of an overall circuit that is located on a semiconductor wafer, the system and method comprising an arrangement comprising an overall circuit with at least one input and output. The overall circuit may be provided with an embedded circuit that is not directly connected to the inputs and outputs or may be connected thereto by being specially switched. Switching elements and test islands that are connected thereto may be provided such that the input or the output of the embedded circuit may be connected to the test islands via the switching elements in case of a test. The switching elements may be switched to said test mode in case of a test by applying a voltage to the test island, or the switching elements may be switched in this manner.

Abstract: The present invention provides a semiconductor testing apparatus and method capable of reliably determining whether a semiconductor memory is good or bad. A “1” reading test of each cell corresponding to one bit at a first step is first performed on a memory cell array. “0” writing of each cell corresponding to one bit at a second step and a “0” reading test of each cell corresponding to one bit at a third step are executed on the memory cell array. Thus, the time taken from the supply of power to the start of the “0” reading test of the reference cell at the third step can be significantly shortened. As a result, a defect of a reference bit line due to a breaking or high resistance of a gate of a reference column switch transistor corresponding to a normally ON transistor can be screened.

Abstract: A testing apparatus for analyzing a memory module under test operating within an application system, wherein the memory module under test is coupled to a processor of the application system, is disclosed herein. In at least one embodiment, the testing apparatus comprises a first interface for coupling to the application system, a second interface for coupling to a reference memory module, a controller coupled to the first and second interfaces, at least one comparator, and a data logging unit. The data logging unit is configured to receive logging data from the controller and at least one test result from the at least one comparator, and to record, in a memory, at least a subset of the logging data, such that more specific details of memory errors revealed during behavioral testing of memory modules may be identified, examined, and stored for subsequent analysis.

Abstract: A semiconductor memory apparatus having stacked first and second chips includes a first chip test signal generation unit disposed in the first chip and configured to generate a first chip test signal in response to a first chip compression data determination signal in a test mode, a second chip test signal generation unit disposed in the second chip and configured to generate a second chip test signal in response to a second chip compression data determination signal in the test mode, and a final data determination unit configured to generate a final test to signal in response to the first and second chip test signals in the test mode.

Abstract: A semiconductor memory device includes a memory region including memory cells configured to store data, a redundant region including memory cells configured to store data, and a control unit.

Abstract: REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.

Abstract: Provided is a test apparatus that tests a device under test, comprising (i) a master domain that includes a master period signal generating section, which generates a master period signal, and that operates based on the master period signal and (ii) a slave domain that includes a slave period signal generating section, which generates a slave period signal, and that operates based on the slave period signal. The master period signal generating section receives a control signal and resumes generation of the master period signal, which is being held, and the slave period signal generating section receives the control signal, initializes phase data of the slave period signal, and resumes generation of the slave period signal, which is being held.

Abstract: In an embodiment, the effect of signal phase difference on a memory system is tested for various operating states. The various operating states may be represented as respective sample points on a plane defined by a range of values for a difference in signal phases and a range of values for another operating state parameter. In various embodiments, sample points for a round of crosstalk testing may include two sample points which are offset from the same reference point on the plane along different respective axes, where the axes are oblique to one another.

Abstract: A technique for detecting an imminent read failure in a memory array includes determining a first incident count for a memory array that does not exhibit an uncorrectable error correcting code (ECC) read during an array integrity check. In this case, the first incident count corresponds to an initial number of ECC corrections that are performed when the array integrity check of the memory array initially fails. The technique also includes determining a current count for the memory array when the memory array does not exhibit an uncorrectable ECC read during subsequent array integrity checks. In this case, the current count corresponds to a subsequent number of error correcting code (ECC) corrections required during the subsequent array integrity checks. An indication of an imminent read failure for the memory array is provided when the current count exceeds the first incident count by a predetermined amount.

Abstract: A technique for detecting an imminent read failure in a memory array includes determining whether a memory array, which does not exhibit an uncorrectable error correcting code (ECC) read during an initial array integrity check at a normal read verify voltage level, exhibits an uncorrectable ECC read during a subsequent array integrity check at a margin read verify voltage level. The technique also includes providing an indication of an imminent read failure for the memory array when the memory array exhibits an uncorrectable ECC read during the subsequent array integrity check. In this case, the margin read verify voltage level is different from the normal read verify voltage level.

Abstract: A memory using techniques to extract the data content of its storage elements, when the distribution of stored states is degraded, is presented. If the distribution of stored states has degraded, secondary evaluations of the memory cells are performed using modified read conditions. Based upon the results of these supplemental evaluations, the memory device determines the read conditions at which to best decide the data stored.

Abstract: A method to detect potential problems within a heterogeneous and diverse application environment. Operations data is received from a plurality of application servers within the application environment. The operations data pertains to operations performed at the plurality of application servers over a predetermined time interval. The operations data is aggregated. The aggregated data is compared to reference data, and a potential problem within the application environment is detected if the aggregated data deviates from the reference data in a predetermined manner.

Abstract: In an embodiment, code, such as the boot code for an integrated circuit or set of integrated circuit products, is provided in a system. The code may be a unified code base including multiple code blocks. Additionally, a signature is provided which describes the integrated circuit on which the boot is being performed. The signature may be processed (e.g. by a processor included in the integrated circuit) to determine which of the code blocks to execute. Accordingly, a single image of the boot code may be used for a variety of different integrated circuits and/or different integrated circuit implementations. For example, the same unified boot code may be used with one or more simulation models, or various programmable logic device models, that include various subsets of the components of the integrated circuit. The code blocks may correspond to various components, and may include tests for the corresponding components.

Abstract: A test apparatus testing a device under test includes a main pattern generating section that generates a main pattern, a plurality of sub-pattern generating sections each of which generates a sub-pattern corresponding to a different one of segment cycles based on a main pattern, the segment cycles formed by dividing a test cycle period, a test signal supplying section that supplies, to the device under test, a multiplexed test pattern formed by switching sub-patterns generated by the plurality of sub-pattern generating sections at each of the segment cycles, and a plurality of delay selecting sections each of which selects one of a main pattern that is from the main pattern generating section and a delayed main pattern that is formed by delaying the main pattern from the main pattern generating section by a test cycle, to supply the selected one to the corresponding sub-pattern generating section.

Abstract: A method for testing a dynamic random access memory (DRAM) includes copying a test program from the DRAM to a random access memory (RAM). Start and end physical addresses of the DRAM are respectively stored in first and second registers. First test data is written to the start physical address, and second test data is read from the start physical address. The method further includes determining whether the second test data is the same as the first test data. A fixed value is added to the start physical address to obtain a next start physical address if the second test data is the same as the first test data. The method further includes determining whether the next start physical address is less than the end physical address. A test success result is returned if the next start physical address is not less than the end physical address.

Abstract: A method is for testing a non-volatile memory. A base data pattern is defined for a first pageset of the non-volatile memory. The non-volatile memory has a plurality of pages which comprise words. The base pattern is arranged so that each bitpair of a plurality of bitpairs that includes one of a group consisting of even bitpairs and odd bitpairs formed from all of the words exhibits all possible bitpair transitions during sequential accesses of the pages of the plurality of pages. The base pattern is stored in the first pageset. The pages of the plurality of pages of the first pageset are accessed sequentially.

Abstract: A memory is disclosed comprising: a storage array for storing data; and access circuitry for transmitting data to and from the storage array. The access circuitry forms a data path for inputting and outputting data to the storage array. The access circuitry comprises a latch configured to latch in response to a first phase of a first clock signal and a further latch configured to latch in response to a second phase of a second clock signal, the further latch comprises an output latch for outputting the data from the storage array, and the first and second clock signals are synchronised with each other.

Abstract: The semiconductor integrated circuit including a memory macro includes a memory cell unit, input data holding units, and output data holding units. The input data holding units hold one of values of input data signals and a scan value depending on a scan control signal in accordance with an operating clock. The output data holding units hold one of values held by the input data holding units and data values stored by the memory cell unit depending on a test control signal in accordance with a phase different from a phase to operate the input data holding units. Further, the input data holding units and the output data holding units are alternately connected in series, and one input data holding unit is arranged at the top. A value held by one output data holding unit is transmitted to another input data holding unit arranged at a subsequent stage of the one output data holding units as the scan value.

Abstract: A processor has an ALU, a load/store unit, a timer, an ECC calculator, and a plurality of ECC registers. When the load/store unit writes data in a main memory, the load/store unit writes written data and a count value of a timer in the main memory, and sets ECC status flag which indicates that an ECC about the written data is not correct in the main memory, and causes the ECC calculator to calculate the ECC about the written data after setting the ECC status flag, and writes the calculated ECC in the main memory and resets the ECC status flag after the ECC is calculated.

Abstract: A motherboard error detection system includes a pluggable error detection board and a motherboard having a boot management chip. When the motherboard enters a device-driven status from a standby status, the boot management chip is used to manage power-on timings of different voltage sources; to collect a plurality of sets of status information; and to check whether the sets of status information and the power-on timings have errors. The pluggable error detection board includes an interpreting unit, a message-reading interface and a connector which is pluggably disposed on the motherboard. When the boot management chip notifies the pluggable error detection board to read an error message, the interpreting unit converts the error message to human-readable information, and the human-readable information is outputted through the message-reading interface.

Abstract: A test-ahead feature for non-volatile memory-based mass storage devices to anticipate device failure. The test-ahead feature includes a method performed with a solid-state mass storage device having a controller, a cache memory, and at least one non-volatile memory device. At least a first block is reserved on the at least one non-volatile memory device as a wear-indicator block and a plurality of second blocks are used for data storage. Information is stored corresponding to the number of write and erase cycles encountered by the second blocks during usage of the mass storage device, and the information is accessed to perform wear leveling among the second blocks. The wear-indicator blocks are subjected to an offset number of write and erase cycles in excess of the number of write and erase cycles encountered by the second blocks, after which an integrity check of the first block is performed.

Abstract: The present disclosure includes various method, device, and system embodiments for reducing non-volatile memory cell read failures. One such method embodiment includes performing a first read operation, using an initial read potential, to determine a state of a selected memory cell in a string of non-volatile memory cells. This method includes determining whether the state of the selected memory cell is an incorrect state by performing a first check using a data checking technique, and if the incorrect state is determined, performing a number of subsequent read operations using read potentials stepped to a higher and a lower read potential to a particular count of read operations.

Abstract: Disclosed are methods, systems and devices, such as a device including a data location, a quantizing circuit coupled to the data location, and a test module coupled to the quantizing circuit. The quantizing circuit may include an analog-to-digital converter, a switch coupled to the memory element and a feedback signal path coupled to the output of the analog-to-digital converter and to the switch.

Abstract: In one embodiment, the invention is a method, apparatus, and design structure for built-in self-test for embedded memory in integrated circuit chips. One embodiment of a method for built-in self-test of an embedded memory includes setting up a plurality of test patterns at a speed of a test clock, where the speed of the test clock is slow enough for a tester to directly communicate with a chip in which the memory is embedded, and where the setting up includes loading a plurality of signal states used to communicate the test patterns to one or more components of a built-in self-test system, applying the test patterns to the embedded memory as a microburst at-speed, capturing output data from the embedded memory at-speed, the output data corresponding to only one of test patterns, and comparing the output data to expected data at the speed of the test clock.

Abstract: A network having a plurality of subscribers has at least one message transmitter and at least one message receiver. The at least one message transmitter sends messages at predefined time intervals. The message receiver receives the messages at the predefined time intervals. A delay time of the messages is monitored on the basis of time outs. In addition, at least one of the subscribers repeatedly estimates a current delay time using a time measurement between sending out a request message and receiving a response message. The estimated delay time is compared with a predefined threshold value. If the estimated delay time exceeds the defined threshold value, an error signal is generated.

Abstract: An integrated circuit configured for at-speed scan testing of memory arrays. The integrated circuit includes a scan chain having a plurality of serially coupled scan elements, wherein a subset of the plurality of scan elements are coupled to provide signals to a memory array. Each scan element of the subset of the plurality of scan elements includes a flip flop having a data input, and a data output coupled to a corresponding input of the memory array, and selection circuitry configured to, in an operational mode, couple a data path to the data input, and further configured to, in a scan mode, couple to the data input one of a scan input, the data output, and a complement of the data output. The scan elements of the subset support at-speed testing of a memory array coupled thereto.

Abstract: Herein described is at least a method and system for processing a read or write operation when one or more defects are mapped using one or more fractional sectors. The method comprises using one or more fractional sectors to map defects and to store data symbols. Furthermore, a first algorithm is used for translating a logical block address into a physical starting location such that one or more fractional sectors may be processed during a read or write operation. A second algorithm is used for temporally processing one or more portions of a track of a disk drive, wherein the one or more portions may comprise one or more defective fractional sectors, non-defective fractional sectors, frame remainders, and servo sectors. The system comprises a memory, a processor, and software resident in said memory. The process executes the software that implements the first and second algorithms.

Abstract: A test apparatus is for testing a memory device including a memory cell. The test apparatus includes a storage and a controller. The storage stores a first value. The controller executes, at a given timing, determining a second value which is a threshold limit value to read data of the memory cell correctly on the basis of an output of the memory cell, calculating a difference between the first value and the second value, outputting a deterioration information on the basis of the difference between the first value and the second value, and updating the first value stored in the storage to the second value.

Abstract: A semiconductor memory device includes: a plurality of RAM macros; and a test control circuit configured to correlate the plurality of RAM macros with a plurality of memory test execution periods. The test control circuit outputs control signals to the plurality of RAM macros such that one RAM macro of the plurality of RAM macros is tested during one memory test execution period of the plurality of memory test execution periods, the one RAM macro being correlated with the one memory test execution period.

Abstract: Detecting brown-out in a system having a non-volatile memory (NVM) includes loading data in the NVM, wherein a next step in loading is performed on a location in the NVM that is logically sequential to an immediately preceding loading. A pair of adjacent locations include one with possible data and another that is empty. Determining which of the two, if at all, have experienced brownout includes using two different sense references. One has a higher standard for detecting a logic high and the other higher standard for detecting a logic low. Results from using the two different references are compared. If the results are the same for both references, then there is no brownout. If the results are different for either there has been a brownout. The location with the different results is set to an invalid state as the location that has experienced the brownout.

Abstract: A memory checking system according to the present invention includes a memory that stores a data to be checked, a check circuit that checks the memory by using the data to be checked and a reference check code of the data to be checked, and a transfer circuit that transfers the data to be checked from the memory to the check circuit based on a transfer setting information of the data to be checked. The transfer setting information is registered in advance in the memory.

Abstract: A method for managing a bad cell is provided. The method includes reading status data from a page buffer and detecting a location of a bad cell from the status data. The method may further include remapping a bad address for the bad cell to a spare address for a spare cell in the same page.

Abstract: A method of testing a memory includes generating a plurality of addresses, such as a test address, accessing contents of each of the plurality of addresses and storing them in storage circuitry, performing a test on the plurality of addresses, accessing the memory test circuitry by sending an access address to snooping circuitry, determining if the access address matches at least one of the plurality of addresses and generating at least one hit indicator in response thereto, generating a snoop miss indicator, determining if it indicates a miss, if it indicates a miss, accessing the memory in response to the access address, and if it does not indicate a miss, either storing snooped data from a interconnect master to a selected portion of the storage circuitry or reading the snooped data from the selected portion of the storage circuitry to the interconnect master.

Abstract: An instruction-based programmable memory built-in self test (P-MBIST) circuit and an address generator thereof are provided. The P-MBIST circuit generates control signals according to the decoding of compact test instructions provided by an external automatic test equipment (ATE). The address generator generates memory addresses according to the control signals. The control signals and the memory addresses are sent to an embedded memory to perform the MBIST. The algorithm-specific design of the P-MBIST circuit and the address generator enables them to support multiple test algorithms at full clock speed and occupy smaller chip area.

Abstract: An electronic card (4) comprising a processing unit (7), able to receive a command originating from a diagnostic module (6) and a command originating from a simulation system (3). The electronic card (4) comprises means of managing the execution priority of the command originating from the simulation system (3) relative to the command originating from the diagnostic module (6). A diagnostic system of an electronic card comprising a diagnostic module and means of managing the execution priority of the commands. A simulation method is associated with the electronic card (4). For use in particular for analysing malfunctions on electronic cards (4) incorporated in integration simulators (1).

Abstract: A semiconductor integrated circuit has a data generation circuit configured to generate first data used for function verification of a built-in self test circuit and a built-in redundancy allocation circuit of a memory, a failure data generation circuit configured to generate second data for conducting a built in self test by inverting at least one bit of the first data based on a failure injection indication signal, and a timing circuit configured to adjust timing of at least one of the first and the second data in order to use one of the first and the second data as writing data to the memory and to use the other as an output expected value compared with data read out from the memory.

Abstract: An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one embodiment, the IC includes: (1) an external test bus interface, (2) read-write memory coupled to the external test bus interface, (3) other circuitry and (4) BIST circuitry, coupled to the external test bus interface, the read-write memory and the other circuitry and configured to test the read-write memory to identify a good data block therein, store in a predetermined data block in the read-write memory multiple instances of a pointer to the good data block, conduct a test of at least the other circuitry and store at least some results of the test in the good data block.

Abstract: Fault diagnosis techniques for non-volatile memories are disclosed. The techniques are based on deterministic partitioning of rows and/or columns of cells in a memory array. Through deterministic partitioning, signatures are generated for identification of failing rows, columns and single memory cells. A row/column selector or a combined row and column selector may be built on chip to implement the process of deterministic partitioning. An optional shadow register may be used to transfer obtained signatures to an automated test equipment (ATE).

Abstract: A semiconductor memory device includes a determination circuit that generates a determination signal by determining an error of read data read out from a memory cell array, and an I/O circuit that outputs the read data or the determination signal to outside via a data input/output terminal. The I/O circuit outputs the read data to outside at a first timing in a normal: operation mode, and in a test mode, outputs the determination signal to outside at a second timing later than the first timing. A difference between the first timing and the second timing is an integer times of a cycle of a clock signal. In this way, the determination signal can be correctly output in the test mode, because an output timing of the determination signal is controlled to be delayed from an output timing of the read data within the device.

Abstract: An information processing system includes an electronic device and an information processing unit. The electronic device includes a fault detection unit; a data generating unit for generating, as data, the content of the detected fault; a data dividing unit for dividing the generated data into plural division data in the case where the data exceeds a predetermined capacity; a data compression unit for compressing each of the plural division data; an identification information adding unit for adding identification information to each of the plural compressed division data; and a data transmission unit for transmitting the plural compressed division data with the identification information. The information processing unit includes a data receiving unit for receiving the plural compressed division data, and a data restoration unit for restoring the plural compressed division data into original data based on the identification information.

Abstract: The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface.

Abstract: Configuration information including number of normal cell areas and number of spare cell areas arranged in a memory macro and a size of each cell area is extracted from circuit design information, and electrical test results of the normal cell areas and the spare cell areas arranged in the memory macro are collected. Arrangement information corresponding to a collection order of the electrical test results is converted to a two-dimensional coordinate value for two-dimensionally displaying the arrangement information corresponding to a collection order of the electrical test results in a unit of cell area in association with a physical layout of a memory cell in the memory macro based on the configuration information. The collected electrical test results are displayed based on the two-dimensional coordinate value so that the normal cell areas and the spare cell areas can be distinguished.

Abstract: An I/O compression apparatus, for testing a memory array and/or a logic circuit, is comprised of a selectable compression circuit that outputs compressed test data from the memory array/logic circuit. An I/O scan register is coupled to each I/O pad for converting serial data to parallel and parallel data to serial in response to a test mode select signal, a test data input, and a test clock.

Abstract: The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. A number of method embodiments include reading data from memory cells corresponding to a sector of data, determining a number of the memory cells in a non-erased state, and, if the number of the memory cells in a non-erased state is less than or equal to a number of errors correctable by an ECC engine, determining the sector is erased.

Abstract: Methods and structure described herein provide for adjusting an error correction capability of an LDPC error correction code. For example, the system of one embodiment includes a decoder adapted to decode data that has been encoded with a LDPC error correction code. The system also includes a detector communicatively coupled to the decoder and adapted to estimate bit values in the data prior to decoding by the decoder. The detector is further adapted to change bit values based on bit value estimations to reduce the error correction capability of the LDPC error correction code. The reduction in error correction capability is adjustable such that sector failure rates of storage devices may be incrementally analyzed.

Abstract: A data displacement bypass system is disclosed, wherein the data displacement bypass system comprises a CPU (Central Processing Unit), a first memory, a plurality of address lines, a plurality of data lines, an OE (Output Enable) line, a CS (Chip Select) line and a data displacement unit. The CPU could output a plurality of address characters, an OE signal and a CS signal, and receive a plurality of data characters. The first memory and the data displacement unit could output the plurality of data characters according to the plurality of address characters, the OE signal and the CS signal received by the first memory and the data displacement unit, wherein the data displacement unit could govern the plurality of data characters inputting to the CPU by outputting high or low voltage.

Abstract: An electronic control apparatus comprises a nonvolatile memory, operating means, determining means and retrying means. The nonvolatile memory stores predetermined data and has a memory region which is divided into a plurality of sub-regions. The operating means executes a check operation for each of the sub-regions in order to check whether the data stored in the nonvolatile memory are normal or not. The determining means determines whether the check operation has detected any data errors. The retrying means allows the operating means to retry the check operation for a predetermined number of times for the sub-regions that have been determined to be in data error by the determining means.

Abstract: A memory testing method is provided, by using the computation capability of a controller to receive the testing command the program code of a testing PC to generate random data or use an algorithm to generate testing data of specific format. Then, the method writes the data directly to the flash memory and read the data from the memory again to compare with the original data. The comparison result is transmitted back to the testing PC. The method greatly reduces the memory access frequency and I/O load of the testing PC so as to improve the testing efficiency.

Abstract: A semiconductor integrated circuit includes memories, a BIST circuit, and an analyzer. The BIST circuit includes a test controller performing the test and generating a memory selection signal selecting a memory to be tested, an address generator generating write and read addresses, a data generator generating write data and an expected output value, and a control signal generator generating a control signal. The analyzer includes a memory output selector selecting output data, a bit comparator comparing the output data with the expected output value, an error detection unit determining whether there is an error in the memory, a plurality of pass/fail flag registers capable of storing a pass/fail flag, a repair analyzer analyzing a memory error and generating a repair analysis result, a plurality of repair analysis result registers capable of storing the repair analysis result, and an output unit outputting the pass/fail flag and the repair analysis result.