Abstract: The invention presents a Wake On LAN (WOL) test system and method thereof, wherein the system is applied for a client/server structure with the ILO (Integrated Lights-Out) inside server platform. The system is composed of an examiner end, an examinee end and a network domain. And through the WOL test module automates the WOL test procedure.

Abstract: A semiconductor integrated circuit which can perform repair of at least one memory circuit in RAM, etc. and can promote improvement in the degree of integration is provided. The encoding circuit 3 receives the failure bit data fail [0]-fail [7], encodes these eight-bit failure bit data fail [7:0], and outputs four-bit (the number of compressed bits) encoded data ef [3:0] sequentially. This encoded data ef [3:0] can indicate various kinds of failure information about RAM1. The capture circuit 4 latches the encoded data ef [3:0] which satisfies a predetermined latch condition, as latch data cf [3:0]. The capture circuit 4 can perform a serial shift operation of the latch data cf [3:0], and can output serially the latch data cf [3:0] as the serial data output So.

Abstract: A system and method for remotely diagnosing and repairing a computer controlled asset comprises an access point connected to a computer controlled asset thereby allowing electronic access to the computer system of the computer controlled asset, a service center remotely connected to the access point for providing diagnostic review and repair of the computer controlled asset, and an interface linking the access point to the service center thereby allowing the service center to communicate with the computer controlled asset via the access point.

Abstract: Tracing of test information from a hardware device for debugging is formatted for transmission via a high-speed serial protocol. Data from various components in the hardware device is transmitted to an external test board using high speed serial ports. The number of serial ports needed for data transfer is significantly less than a complimentary parallel port configuration. Additional functional blocks on the chip process the data for high speed serial output. The functional blocks format information into subchannels, arbitrate data, append protocol, perform data integrity checks, and serialize the data. The additional blocks built on the chip to support the serial ports consume less chip space than the space consumed by the number of parallel ports required to provide equivalent data transfer rates. The process operates in near real time and may use time stamping to correlate and reconstruct data from different information sources.

Abstract: A method and system for testing a chip at functional (operational) speed. The chip may include an integrated circuit having a number flops and memory arrays arranged into logically functioning elements. Additional flops may be included to output to one or more of the other flops in order to provide inputs to the flops at the functional speed such that the receiving flops executing at the functional speed according to the received input at a next functional clock pulse to facilitate testing the chip at the functional speed.

Abstract: A method, system, and computer program product for integrated circuit recovery testing using simulation checkpoints is provided. The method includes executing an error injection test on an integrated circuit that includes a plurality of domains and latches. The error injection test includes injecting an error into one of the domains, clock stopping the domain with the error, performing fencing between the domain with the error and the other domains, and quiescing the other domains. A checkpoint is created of a state of the integrated circuit after the clock stopping, fencing and quiescing have been completed. A mainlines test of the integrated circuit is executed. The mainline test includes applying the checkpoint to the integrated circuit, and performing a recovery reset of the stopped domain. It is determined if the mainline test executed correctly and the results of the determining are output.

Abstract: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip.

Abstract: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip. The present invention supports devices adapted for dynamically modifying the scan path of a system-on-chip (referred to herein as crossroad devices), including methods for describing such devices and use of such devices to perform testing of system-on-chips.

Abstract: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip. The present invention supports parallel access to one or more system-on-chip devices, including methods for describing and using parallel access for testing.

Abstract: A field programmable object array integrated circuit has built-in self-testing capability. The integrated circuit comprises an array of programmable objects, a plurality of interfaces, and a controller. The array of objects is designed to operate at an operational clock speed during non-testing operation, wherein the design of the objects is not constrained to require within an object extra circuitry not essential to non-testing operation to facilitate built-in self-testing. The interfaces are connected to the objects to enable communication with the objects and to thereby facilitate built-in self-testing of the objects. The controller causes a selected subset of the objects to be activated and configured for testing, to stimulate the selected subset for some time with an input test pattern delivered via the interfaces while the selected subset of objects operates at the operational clock speed, and to observe a response of the selected subset of objects.

Abstract: A method and circuit for capturing and observing the internal state of an integrated circuit that utilizes a scan chain capable of capturing the functional state of an integrated circuit during functional testing without interrupting the functional testing. The functional state may be captured by and shifted out of the scan chain concurrently with functional testing. The scan chain includes sequential elements, each having a functional state and a scan state that operate in parallel. The method and circuit may further include a signature analyzer for compressing the contents of the scan chain into a signature. The method and circuit may capture and compress multiple functional states into a combined signature.

Abstract: A method for controlling a DRAM includes detecting failed memory cells of the DRAM, recording the rows corresponding to the failed memory cells, receiving a control signal for accessing the memory cell with column address X and row address Y, determining if the row address Y is in the recorded failed rows list, and if yes, replacing the memory cell to be accessed with the memory cell with the column address X and row address Z which is not same as Y.

Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

Abstract: A plurality of diagnosis methods are provided for enabling hardware debugging. A first diagnosis method enables hardware debugging by means of time abstraction. A second diagnosis method enables hardware debugging by means of abstraction and refinement. A third diagnosis method enables hardware debugging by means of QBF-formulation for replicated functions. A fourth diagnosis method enables hardware debugging by means of a max-sat debugging formulation. A system and computer program for implementing the diagnosis methods is also provide.

Abstract: Embodiments of the invention relate to an apparatus for repairing and/or testing at least one memory device having a plurality of memory cells, the apparatus comprising an interface which is adapted to accommodate a memory device; means for determining the type of memory device; a selection memory for storing at least one repair and/or test program; and selection means for selecting a repair and/or test program from the selection memory.

Abstract: A programmable memory built-in self-test circuit and a clock switching circuit thereof are provided. The memory built-in self-test circuit is able to provide more self-test functions preset by a user, simplify the redundant circuit in the prior art and reduce chip area and lower the cost by means of an instruction decoder and a built-in self-test controller. The present invention also provides some peripheral control circuits of a memory. The control circuits occupies less area and enables the memory to be tested more flexibly. The present invention further provides a clock switching circuit enabling a chip to be correctly tested under different clock speeds, which benefits to advance the testability and the analyzability of the memory embedded in a chip and thereby increase fault coverage.

Abstract: A device and a method for testing SAS channels which are applied to a plurality of pairs of SAS interfaces. The testing device includes a control terminal, a PCI-E microprocessor, a PCI-E-to-SAS adaptor, and a signal feedback module. The control terminal is used for selecting SAS channels and sending a control command; the PCI-E microprocessor is used for receiving the control command and sending a test signal to a PCI-E channel according to the control command; the PCI-E-to-SAS adaptor is used for converting a transmission signal between the PCI-E channel and the SAS channels; and the signal feedback module is used for connecting a first SAS interface to a second SAS interface in the SAS back plate. The PCI-E microprocessor compares whether the test signal sent to the first SAS channel is consistent with the test signal received from the second SAS interface.

Abstract: Method, apparatus and computer program product are configured to perform computer monitoring activities; to collect information regarding computer system status during the computer monitoring activities; to detect a problem in dependence on the information collected during the computer monitoring activities; and to determine whether to launch a diagnostic probe when the problem is detected. The monitoring activities may be performed on a periodic or event-driven basis. The determination whether to launch a diagnostic probe is based on a rule included in a hierarchy of rules. The hierarchy of rules is based on problem tickets; system logs; and computer system configuration information.

Abstract: In order to detect problematic drives in random arrays of independent disks, the system measures the latency of executing command sets which are broadcast to all disks in the data storage system and the results are compared to identify which disks take substantially longer to complete the requests. Disks that take longer to complete requests are likely to be problematic and are candidates for further examination and replacement. The disks in each tier group are compared to determine if any disk in that group exhibits problems. Also, counters for each tier group are compared to determine if the problem is with the disk or with the channel of the tier group. The latency of each disk in the tier group is saved in a table to provide a histogram of the latency of the disks in the tier group. Histograms of the disks in a single tier group are compared to determine if a specific disk is problematic.

Abstract: Disclosed are embodiments of a system, method and service for detecting and analyzing systematic conditions occurring in manufactured devices. Each embodiment comprises generating a unique signature for each of multiple tested devices. The signatures are generated based on an initial set of signature definitions and the values for those signature definitions that are derived at least in part from selected testing data. A systematic condition is detected based on commonalities between the signatures. The systematic condition is then analyzed, alone or in conjunction with additional information, in order to develop a list of underlying similarities between the devices. The analysis results can be used to refine the systematic condition detection and analysis processes by revising the signature definitions set and/or by modifying data selection.

Abstract: Systems and methods are disclosed herein to provide improved communication system test techniques. For example, in accordance with an embodiment of the present invention, a wireless device test system is disclosed having a channel emulator for multipath and/or MIMO applications to allow the testing of wireless devices (e.g., WLAN devices) in a cabled environment.

Abstract: The present invention provides a semiconductor testing apparatus and method capable of reliably determining whether a semiconductor memory is good or bad. A “1” reading test of each cell corresponding to one bit at a first step is first performed on a memory cell array. “0” writing of each cell corresponding to one bit at a second step and a “0” reading test of each cell corresponding to one bit at a third step are executed on the memory cell array. Thus, the time taken from the supply of power to the start of the “0” reading test of the reference cell at the third step can be significantly shortened. As a result, a defect of a reference bit line due to a breaking or high resistance of a gate of a reference column switch transistor corresponding to a normally ON transistor can be screened.

Abstract: Embodiments of a scannable IO circuit featuring reduced latch count for pipelined memory architectures and test methodology are described. For a pipelined memory system performing at speed tests, the timing sequence for processing a test command comprises a precharge-read-precharge-write sequence for each clock cycle starting with the rising clock edge. The memory circuit utilizing this test command timing sequence comprises a sense amplifier and a single latch. The sense amplifier itself is used as a latch to implements scan functionality for the memory circuit. The memory device is incorporated into an integrated test wrapper circuit that executes back-to-back commands through serial compare operations using integrated scan flip-flop circuits. The test wrapper includes a fanout block and padded address scheme for testing multiple and disparate size memory devices in parallel.

Abstract: A method for storing a memory defect map is disclosed whereby a memory component is tested for defects at the time of manufacture and any memory defects detected are stored in a memory defect map and used to optimize the system performance. The memory defect map is updated and the system's remapping resources optimized as new memory defects are detected during operation.

Abstract: A method for performing memory diagnostics using a programmable diagnostic memory module provides enhanced testability of memory controller and memory subsystem design. The programmable diagnostic memory module includes an interface for communicating with an external diagnostic system, and the interface is used to transfer commands to the memory module to alter various behaviors of the memory module. The altered behaviors may be changing data streams that are written to the memory module to simulate errors, altering the timing and/or loading of the memory module signals, downloading programs for execution by a processor core within the memory module, changing driver strengths of output signals of the memory module, and manipulating in an analog domain, signals at terminals of the memory module such as injecting noise on power supply connections to the memory module.

Abstract: A method of testing a memory module comprising converting a hub of the memory module into a transparent mode, providing first data corresponding to a first address to the hub of the memory module, providing the first data of the hub of the memory module to a first address of a memory, providing first expected data to the hub of the memory module, outputting second data stored at the first address of the memory to the hub of the memory module, and comparing the second data with the first expected data.

Abstract: A virtual appliance environment (VAE) consists of components residing on a computer BIOS ROM and also on a mass storage device. The VAE includes a virtual appliance (VA) for diagnosing malfunctioning hardware or software. The VA for diagnosing malfunctions tests the hardware and/or software resident in the computer and transmits the results of the test to a server, which diagnoses the problem and transmits instructions to the VAE for saving the data, determining whether the computer is under warranty, and providing shipping information to a user. The VAE can also download a VA for scanning viruses. The VAE transmits the results of the virus scan to the server, which determines the type of virus infecting the computer and transmits instructions to the virtual appliance for downloading the appropriate VA for removing the virus. The VAE can save the data to another source, remove the virus, and restore the data or simply remove the virus.

Abstract: A level of indirection is utilized when writing to a microprocessor array structure, thereby masking hard faults in the array structure. Among other benefits, this minimizes the use of a backward error recovery mechanism with its inherent delay for recovery. The indirection is used to effectively remove from use faulty portions of the array structure and substitute spare, functioning portions to perform the duties of the faulty portions. Thus, for example, faulty rows in microprocessor array structures are mapped out in favor of substitute, functioning rows.

Abstract: A method and system for improving Field Replacement Unit (FRU) isolation in memory sub-systems by monitoring Voltage Regulator Module (VRM) induced memory errors. A comparator compares the output voltage coming from the VRM to memory. If the comparator detects a VRM output voltage transient that is outside a rated threshold, then a counter is increased by one. If the counter exceeds a count threshold, a VRM error is posted. If a memory failure occurs within a predetermined period of time, then the VRM error pinpoints the VRM output voltage transient as being the likely cause of the memory failure.

Abstract: A system and method for creating different start cache and bus states using multiple test patterns for processor design verification and validation is presented. A test pattern generator/tester re-uses test patterns in different configurations that alter cache states and translation lookaside buffer (TLB) states, which produces different timing scenarios on a broadband bus. The test pattern generator/tester creates multiple test patterns for a multi-processor system and executes the test patterns repeatedly in different configurations without rebuilding the test patterns. This enables a system to dedicate more time executing the test patterns instead of building the test patterns. By repeatedly executing the same test patterns in a different configuration, the invention described herein produces different start cache states, different TLB states, along with other processor units, each time the test patterns execute that, in turn, changes the bus timing.

Abstract: A system and method to reduce verification time by sharing memory between multiple test patterns and performing results checking after each test pattern executes one time is presented. A test pattern generator generates multiple test pattern sets, each of which including multiple test patterns. Each test pattern set is executed by a corresponding thread/processor until each test pattern included in the test pattern set has executed at least once. After all test patterns have executed at least once, a test pattern executor performs a memory error detection check to determine whether the system is functioning correctly. Since the invention described herein waits until all test patterns have executed before performing a memory error detection check, less time is spent on memory error detection checks, which allows more time to execute test patterns.

Abstract: A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows containing DRAM memory cells that are likely to lose data during normal refresh of the memory cells. Upon power-up, the data from the non-volatile memory are transferred to a comparator in the memory controller. The comparator compares the row addresses to row addresses from a refresh shadow counter that identify the rows in the DRAMs being refreshed. When a row of memory cells is being refreshed that is located one-half of the rows away from a row that is likely to loose data, the memory controller causes the row that is likely to loose data to be refreshed. The memory controller also includes error checking circuitry for identifying the rows of memory cells that are likely to lose data during refresh.

Abstract: A system and method for verifying cache snoop logic and coherency between instruction cache and data cache using instruction stream “holes” that are created by branch instructions is presented. A test pattern generator includes instructions that load/store data into instruction stream holes. In turn, by executing the test pattern, a processor thread loads an L2 cache line into both instruction cache (icache) and data cache (dcache). The test pattern modifies the data in the dcache in response to a store instruction. In turn, the invention described herein identifies whether snoop logic detects the change and updates the icache's corresponding cache line accordingly.

Abstract: In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block.

Abstract: The service life of memory cards is to be substantially elongated against the occurrence of faulty blocks. A control logic searches blocks in a nonvolatile memory cell array for any acquired fault on the basis of a fault-inviting code in a management information section. If any faulty block is detected, the faulty block will be subjected to write/read comparison of data to judge whether or not the data in the block are normal. Any block determined to be normal will undergo rewriting of its fault-inviting code and registered as a normal block. Further, the registered block is stored into a write management table in the management area as a writable block. This enables an essentially normal block judged faulty on account of an erratic error or some other reason to be restored.

Abstract: A semiconductor memory device includes: a pattern selector configured to receive a first test control signal and a second test control signal to output a plurality of pattern selection signals and a selection end signal in response to an entry signal; a shifting controller configured to receive the first test control signal and the second test control signal to output a shifting control signal in response to the selection end signal; and a pattern test signal generator configured to select a stress pattern corresponding to the pattern selection signals to generate a plurality of test mode signals for controlling a sequential entry into a plurality of test modes for executing the stress pattern in response to the shifting control signal.

Abstract: A method of correcting defects in a storage array of a microprocessor, such as a cache memory, by operating the microprocessor to carry out a functional test procedure which utilizes cache memory, collecting fault data in a trace array during the functional test procedure, identifying a location of the defect in the cache memory using the fault data, and repairing the defect by setting a fuse to reroute access requests for the location to a redundant array. The fault data may include an error syndrome and a failing address. The functional test procedure creates random cache access sequences that cause varying loads of traffic in the cache memory using a test pattern based on a random seed. The functional test procedure may be carried out after completion of a nonfunctional, built-in self test of the microprocessor which sets some of the fuses.

Abstract: A semiconductor memory device includes a test address generating circuit configured on the device. The test address generating circuit generates a plurality of test addresses for a test of the semiconductor memory device in response to at least one externally applied test address generation signal. As a result, the number of DUTs can increase, based on a reduction of required address pins, and manufacturing productivity and test efficiency of semiconductor memory devices can increase.

Abstract: A method, system and apparatus for testing a removable storage media drive device are disclosed. According to teachings of the present disclosure, a simulated storage media may be disposed within a removable storage media drive device. In the event removable storage media is not present in the drive device when testing of the device is desired, the simulated storage media may be substituted for at least purposes of testing the operability of one or more device components. In one embodiment, the simulated storage media may be in the form of an annular ring of CD-ROM material. In a further embodiment, the simulated storage media may be in the form of a hologram designed to mimic one or more removable storage media characteristics.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence.

Abstract: A defect analysis method for semiconductor memory includes: reading out an address bit map corresponding to an input kind of the memory macro from a database which stores address bit maps respectively corresponding to memory macro kinds; inputting size information of the memory macro; translating a logical address of a defective cell of the memory macro detected on the basis of results of an electric test measured by using a tester to a physical address of a memory macro in a standard disposition by using the input size information and the address bit map read out, of the memory macro, and generating a fail bit map in the standard disposition; inputting disposition information of the memory macro; and translating a physical address of the fail bit map in the standard disposition to a physical address of the memory macro by using the input disposition information of the memory macro, and generating a fail bit map of the memory macro.

Abstract: It is aimed to efficiently test devices that can transfer data at a very high bit rate. A test apparatus for testing a device under test includes a capture memory that stores thereon an output pattern received from the device under test, a header detecting section that reads the output pattern from the capture memory and detects a portion matching a predetermined header pattern in the output pattern, and a judging section that judges whether the output pattern is acceptable based on a result of comparison between a pattern, in the output pattern, which starts with the portion matching the predetermined header pattern and a corresponding expected value pattern.

Abstract: The test method, integrated circuit and test system embodiments disclosed herein relate to testing at least one integrated circuit which uses an internal operating clock and has a first number of address pins, a second number of command pins and an address generation circuit which receives at least one encoded address information item using a third number of the address pins, which is smaller than the first number, and provides the other address pins as a fourth number of free address pins, where at least one first command is transferred using the command pins and at least one second command is transferred using at least one portion of the fourth number of the address pins from a test apparatus to the integrated circuit using a test clock which has a lower rate than the internal operating clock.

Abstract: An integrated circuit on a semiconductor chip with a plurality of registers distributed across the semiconductor chip. The registers are writeable and readable. The integrated circuit comprises a central control block. The integrated circuit comprises a plurality of circuit units. The circuit unit includes a functional portion with a local clock controller and one or more of the registers. The circuit unit includes a satellite portion. The central control block and the satellite portions are serially connected together and form a scan chain, wherein the scan chain is formed as a ring.

Abstract: A method for recording at least one information block in a first volatile memory external to a circuit, a first digital signature being calculated based on information and data internal to the circuit and a second digital signature being calculated based on first signatures of a group of information blocks and on a digital quantity internal to the circuit and assigned to said group. A method for checking the content of an information block recorded by this recording method.

Abstract: To provide a mobile terminal apparatus with the lower communication cost in sending a log at the occurrence of a malfunction, abnormality or fault in the mobile terminal apparatus to a network. A diagnostic process for the malfunction is performed in accordance with a diagnostic policy acquired from the outside. An error code corresponding to the diagnostic result is generated. The generated error code is outputted. With an automatic fault diagnostic function of automatically analyzing the fault in the mobile terminal apparatus without directly sending the log collected in the mobile terminal apparatus to an analytic server, the communication cost can be reduced.

Abstract: According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at least one register to store an acceptable number of unreliable storage locations for the cache, a detector to measure a thermal environment of the processor, and circuitry to raise an operating voltage of the processor if the actual number of unreliable storage locations exceeds the acceptable number of unreliable storage locations, and if the thermal environment is acceptable.

Abstract: A method, apparatus, and program for systematically testing the functionality of all connections in a multi-tiered bus system that connects a large number of processors. Each bus controller is instructed to send a test version of a snoop request to all of the other processors and to wait for the replies. If a connection is bad, the port associated with that connection will time out. Detection of a time-out will cause the initialization process to be halted until the problem can be isolated and resolved.

Abstract: There is provided a failure diagnostic apparatus that diagnoses a semiconductor integrated circuit device for failure based on a compressed signal obtained by compressing a plurality of signals outputted from a plurality of scan chains in which a plurality of scan flip-flops, to which signals from the semiconductor integrated circuit device are inputted, are connected in series. For each stage of the scan chains, the failure diagnostic apparatus sets a virtual space compression circuit that compresses output signals of the scan flip-flops in the stage and a virtual pin connected to the output terminal of the virtual space compression circuit, and the output signal of the virtual pin is compared with the compression signal to diagnose the semiconductor integrated circuit device for failure.

Abstract: An architecture for testing a pipeline (14) in an integrated circuit comprises an input port and an output port, and is operable to process a data word having a plurality of data bits. The architecture comprises a multiplexer (18) provided at each input of the input port of the pipeline (14), each multiplexer being operable to allow a data bit or test data bit to be input to the pipeline. A write test block (15) is operable to control the writing of data bits or test data bits to the pipeline (14) during a normal or test mode of operation, and a read test block (16) is operable to control the reading of data bits or test data bits from the pipeline during a normal or test mode of operation. The write test block (15) and the read test block (16) are operable in a test mode to control the pipeline (14) as a scan chain. The architecture requires less hardware and hence less silicon area than conventional test architectures.