Abstract: A method for setting an operating frequency of a memory card includes the following steps: performing an operating frequency adjusting flow to select a target operating frequency, and utilizing the target operating frequency to set the operating frequency of the memory card, where the step of performing the operating frequency adjusting flow includes: selecting a plurality of candidate operating frequencies; testing an accessing performance of the memory card operated under the plurality of candidate operating frequencies to generate a plurality of testing results, respectively; and selecting one of the plurality of candidate operating frequencies as the target operating frequency according to the plurality of testing results.

Abstract: A method of testing the operational margin of an information storage device having marked random variations, and an information storage device having the function of self-diagnosing the operational margin, are provided. The test method includes testing an information storage device including a plurality of memory bits as the test condition is set so as to be outside a range of conditions that may be presupposed in real use of the information storage device and of counting the number of memory bits that fail in operation. The test method also includes verifying the size of the operational margin of the information storage device based on the count value. The test condition is made severe and the reference value is set to a fairly large value to enable the operational margin against the noise to be tested highly accurately.

Abstract: A mechanism is provided for verifying a register-transfer level design of an execution unit a set of instruction records associated with a test case are generated and stored in a buffer. For each instruction record in the set of instruction records associated with the test case: the instruction record is retrieved from the buffer and sent to both a reference model and an execution unit in the data processing system. Separately, the reference model and the execution unit execute the instruction record and send results of the execution of the instruction record to a result checker in the data processing system.

Abstract: Methods and apparatus automatically identify certain types of data storage system problems, such as a flawed storage device or an incompatibility between a data storage system and a data storage device or an incompatibility between the storage system and a user computer. The existence of such a problem may be highlighted to a user through an indicator on the storage system and/or through a “dashboard” application being executed by the user computer, and the problem may be automatically corrected by automatically downloading a fix (e.g., new firmware or a “patch”) from a server (e.g., a server managed by the storage device manufacturer, a server managed by the storage system manufacturer and/or a server managed by a third party) and automatically implementing the fix.

Abstract: A system includes a plurality of devices that are connected in series and a controller that communicates with the devices. Each of the devices has a plurality of input ports and corresponding output ports. The outputs of one device and the inputs of a next device are interconnected. The controller is coupled to the first device and the last device of the series-connection. The controller applies a test pattern to the plurality of input ports at the first device connected in series, by the controller. Each data channel defines a data path between corresponding pairs of input and output ports of the first and last devices. A data channel is enabled if the test pattern is detected at its corresponding output port.

Abstract: According to one embodiment, electrical test results of a semiconductor memory arrayed in a logical address order are stored in a first memory secured in a main memory, a plurality of second memory areas in each of which loading and storing of each data in a unit size is performed is secured in the main memory, FBMs in which pass/fail information is arrayed in a physical address order are generated based on different parts of the electrical test results stored in the first memory area, respectively, the FBMs generated from the different parts of the electrical test results are stored in the second memory areas, respectively, and the FBMs stored in the second memory areas, respectively, are output.

Abstract: A repetitive bit value pattern associated to a predetermined bit position of a sequence of data words, the data words having two or more bits in a bit order, a bit position describing a position within the bit order being indicative of a value represented by the bit at the bit position, can be determined from program loop information, the program loop information having a program expression for determining an updated data word of the sequence of data words. Using the predetermined bit position, a sequence length value associated to the predetermined bit position is determined. The program expression is evaluated for a number of loop iterations indicated by the sequence length value, to obtain updated bit values associated to the predetermined bit position. The repetitive bit value pattern is determined using the updated bit values of the number of loop iterations.

Abstract: A system for testing a computing device includes a test device, a switch module connected between the test device and the computing device, and a display module connected to the test device for displaying a plurality of test parameters. The testing device is connected to the computing device via a USB connection. The test device has a power cycling test program and a display driving program. The test device sends trigger signals to turn the computing device on or off and receives signals from computing device via the USB connection, for detecting the occurrence of errors during testing. A method utilizing the system is also disclosed.

Abstract: An integrated bus controller and power supply device includes a typical or standard bus controller and a bus power supply disposed in a common housing, the size and external configuration of which may match a standard bus controller device associated with a typical I/O communication network. The bus controller may store and implement one or more control routines using one or more field devices connected to the I/O communication network while the bus power supply generates and provides the appropriate power signal to the bus of the I/O communication network, the power signal being used to power the field devices connected to the I/O communication network.

Abstract: The semiconductor memory testing device includes a test signal decoder decoding burn-in test mode signals which generates a first test signal for use in controlling entire main wordlines and which generates a second test signal for use in controlling sub wordlines. When the first and second test signals are in an disabled state, the semiconductor memory testing device also includes a plurality of bank control units generating a multi wordline test mode signal as a multi wordline test signal corresponding to a bank control signal, and simultaneously enabling a plurality of wordlines in accordance to the multi wordline test signal to perform a test. The semiconductor memory testing device reduces a testing time and current consumption and thus enhances a more stable voltage drop when performing continuous multi wordline test on a per bank basis.

Abstract: A support element for verifying an array repair code solution includes a memory subsystem element including product data read from multichip modules utilized in a mainframe computing device, a wafer test repair algorithm, and a system test repair algorithm. The support element also includes a CPU emulator that causes the support element to perform an initial microcode load that includes a memory test, the memory test applying the wafer test repair algorithm to the product data to generate a wafer test repair solution and the system test repair algorithm to the product data to generate a system test repair solution and one or more repair rings for storing the wafer test repair solution and the system test repair solution.

Abstract: A computer-implemented method, system, and article of manufacture for parallelizing a code configured by coupling a functional block having an internal state and a functional block without any internal state. The method includes: creating and storing a graphical representation where functional blocks are chosen as nodes and connections between functional blocks are chosen as links; visiting the nodes on the graphical representation sequentially, detecting inputs from functional blocks without any internal state to functional blocks having an internal state and storing these functional blocks as a set of use blocks, and detecting inputs from functional blocks having an internal state to functional blocks without any internal state and storing these functional blocks as a set of definition blocks; and forming strands of functional blocks based on information on the set of use blocks and information on the set of definition blocks stored in association with the functional blocks.

Abstract: The present invention provides a CEC communications device which eliminates a troublesome process to solve the CEC-related communication malfunction when the CEC communications device detects a CEC-related communication malfunction caused by a software malfunction and improves serviceability of the CEC communications by automatically resetting the CEC to execute a CEC communication recovery. In the CEC communications device, when a CEC communications line monitoring unit detects a CEC-related communication malfunction caused by a software malfunction, a CEC control unit determines a reset order of a CEC appliance found on a CEC network, and notifies the CEC resetting unit of a CEC resetting request. The CEC resetting unit resets the CEC of a CEC appliance found on the CEC network via an HDMI line (DDC in FIG. 1) other than the CEC to recover the CEC communications.

Abstract: Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one circuit, such as circuit 1, as the scan test stimulus data for another circuit, such as circuit 2. After reset, a scan path captures the output response data from the reset stimulus from all circuits. A tester then shifts the captured data only the length of the first circuit's scan path while loading the first circuit's scan path with new test stimulus data. The new response data from all the circuits then is captured in the scan path. This shift and capture cycle is repeated until the first circuit is tested. The first circuit is then disabled and any remaining stimulus data is applied to the second circuit. This process is repeated until all the circuits are tested. A data retaining boundary scan cell used in the scan testing connects the output of an additional multiplexer as the input to a boundary cell.

Abstract: A disclosed example method involves at a network management module, receiving a request for logical circuit data associated with a network circuit. In addition, the example method involves requesting the logical circuit data from a legacy logical element in communication with a network device of the network circuit. The logical circuit data is received from the legacy logical element. The logical circuit data is indicative of whether the network circuit has failed.

Abstract: A method begins by a processing module receiving data for storage. The method continues with the processing module determining storage metadata regarding the data the method continues with the processing module. The method continues with the processing module determining memory device capabilities based on the storage metadata. The method continues with the processing module identifying memory devices based on the memory device capabilities to produce identified memory devices. The method continues with the processing module encoding the data into a plurality of data slices in accordance with an error coding dispersal function. The method continues with the processing module storing the plurality of data slices in the identified memory devices.

Abstract: Provided are a method and apparatus for performing diagnostic functions of an external device such as a printer, connected to a host computer. The apparatus and method receive information about diagnostic functions supported by the external device from the external device; receive one or more of the diagnostic functions which are selected by a user; request the external device to perform the selected diagnostic functions; and receive the results of the requested diagnostic functions from the external device.

Abstract: A method and system for performing a smart repair of a target device is initiated by establishing a connection to a smart repair processing system. System components on the target device may then be analyzed, followed by an analysis of system software and user data. The target device user data may be secured by transfer to a backup server. A smart repair script may be generated based on user input and the results of the analysis. The smart repair script may then be executed on a secondary operating system loaded on the target device to attain a desired system configuration of the target device. The target device user data may then be restored on the target device.

Abstract: A semiconductor test apparatus includes an inputting module, a monitor, a converter, a storage, and a tester. The inputting module inputs addresses for first test, in which the addresses of a plurality of semiconductor memories are arrayed in an arbitrary order. The monitor monitors test time of the first test on each semiconductor memory. The converter sorts the addresses of the semiconductor memories based on the test time in order to convert the address for the first test to addresses for a second test. The storage stores the addresses for the second test. The tester tests each semiconductor device based on the addresses for the second test stored in the storage.

Abstract: An electronic device is provided which comprises a microprocessor for executing a program code and a first hardware code path verifying (CPV) stage coupled to the microprocessor. The hardware CPV stage comprises a first error detection code (EDC) generator configured to continuously determine an error detection code on a continuous sequence of code relating to an actually executed portion of the program code and to compare the actual error detection code with a predetermined error code so as to verify correct execution of the program code and to indicate an error.

Abstract: A personal computer component diagnostic method is executed to recognize the status or potential problems of a computer before executing an operating system. The personal computer component diagnostic method comprising: calling a BIOS program; executing a component basic diagnostic program; and executing a component functional test after executing a predetermined step. The component functional test includes a CPU MSR/MTRR test, a hard disk S.M.A.R.T. test, a boot path test and a PCI device scanning test.

Abstract: The invention describes an electronic device and a method for operating the electronic device. The electronic device includes one or more circuit components. The electronic device further includes one or more fuses and one or more non-volatile memories to disable the access of at least one of the one or more circuit components. Each of the one or more non-volatile memories includes one or more firmware, which are used to program at least one bit to manage the access of the at least one circuit component. The method includes performing a power-up sequence in a power cycle for the electronic device. The method further includes determining a state of circuit and a state of a bit for selectively enabling a test function.

Abstract: A method and circuit for implementing enhanced memory reliability using memory scrub operations to determine a frequency of intermittent correctable errors, and a design structure on which the subject circuit resides are provided. A memory scrub for intermittent performs at least two reads before moving to a next memory scrub address. A number of intermittent errors is tracked where an intermittent error is identified, responsive to identifying one failing read and one passing read of the at least two reads.

Abstract: The present invention relates to an automatic testing apparatus, which comprises a device under test and a testing module. The device under test has a testing program and includes a plurality of functional modules. The testing module is coupled to the device under test. The device under test executes a testing program and communicates with the testing module so that the testing module can test the plurality of functional modules of the device under test. By adopting automatic testing, no tester is needed for performing testing. Thereby, the personnel cost can be reduced and the total testing time can be shortened.

Abstract: A microcontroller device comprising a receiver component configured to receive a one or more reset signals for the microcontroller device; an identification component configured to identify a source of the or each reset signals received by the receiver component; a time interval determining component configured to determine a length of a time interval in accordance with the identified source of the or each reset signals received by the receiver component; a voltage setting component configured to set a voltage of an output of the microcontroller device to a first value on receipt of a reset signal by the receiver component; and a control component configured to maintain the voltage of the output at the first value for the duration of the determined length of the time interval; and set the voltage of the output to a second value on substantial completion of the determined length of the time interval.

Abstract: An approach is provided for automatic disabling of network debugging. A debugging command is received for initiating debugging of a router that includes a processor configured to execute a debugging procedure. Utilization of the processor is monitored. A determination is made whether the utilization exceeds a utilization threshold. The debugging procedure is disabled based on the determination that the utilization threshold is exceeded.

Abstract: Systems and methods are provided for testing a non-volatile memory, such as a flash memory. The non-volatile memory may be virtually partitioned into a test region and a general purpose region. A test application may be stored in the general purpose region, and the test application can be executed to run a test of the memory locations in the test region. The results of the test may be stored in the general purpose region. At the completion of the test, the test results may be provided from the general purpose region and displayed to a user. The virtual partitions may be removed prior to shipping the electronic device for distribution.

Abstract: A method for enhancing verification efficiency regarding error handling mechanism of a controller of a Flash memory includes: providing an error generation module, for generating errors; and triggering the error generation module to actively generate errors of at least one specific type in order to increase an error rate corresponding to the specific type. An associated memory device and the controller thereof are provided, where the controller includes: a ROM arranged to store a program code; a microprocessor arranged to execute the program code to control access to the Flash memory and manage a plurality of blocks, and further enhance the verification efficiency regarding error handling mechanism of the controller; and an error generation module arranged to generate errors. The controller that executes the program code by utilizing the microprocessor triggers the error generation module to actively generate errors of at least one specific type to increase an error rate.

Abstract: A semiconductor memory apparatus according to the embodiment includes a test mode controller, a first data alignment unit, a decoder, a test executing unit and a second data alignment unit. The test mode controller is configured to generate test enable signals in response to a test mode setting signal and a read command. The first data alignment unit is configured to parallely align first input data that are input in series, generate first alignment data, and transmit it to the first data driver. The decoder is configured to decode the first alignment data in response to the test enable signal and generate the decoding signal. The test executing unit is configured to execute the preset test mode in response to the decoding signal. The second data alignment unit is configured to parallely align second input data, which are input in series, in response to the test enable signal, generate second alignment data, and transmit it to a second data driver.

Abstract: An electronic circuit includes a first processor (100) operable to perform processing operations, a first trace buffer (230) coupled to the first processor (100), a first triggering circuit (210) coupled to the first processor (100), the first triggering circuit (210) operable to detect a specified sequence of particular processing operations in the first processor (100); a second processor (101), a second trace buffer (231) coupled to the second processor (101), a second triggering circuit (211) coupled to the second processor (101), the second triggering circuit (211) operable to detect at least one other processing operation in the second processor (101); and a cross trace circuit (330) having a trace output and having inputs coupled to the first triggering circuit (210) and to the second triggering circuit (211), the cross trace circuit (330) configurably operable to respond to a sequence including both a detection of the sequence of particular processing operations of the first processor (100) by the fir

Abstract: In an embodiment, a method is provided for tracking a test. In this method, a test session identifier is transmitted to a test system. The test session identifier identifies a particular test session. A test of a component is triggered at the test system, and this test provides test results, which are received from the test system. The test results include the test session identifier, which allows the tests to be associated with the particular test session.

Abstract: Disclosed are embodiments of a system, method and service for detecting and analyzing systematic conditions occurring in manufactured devices. Each embodiment comprises generating a unique signature for each of multiple tested devices. The signatures are generated based on an initial set of signature definitions and the values for those signature definitions that are derived at least in part from selected testing data. A systematic condition is detected based on commonalities between the signatures. The systematic condition is then analyzed, alone or in conjunction with additional information, in order to develop a list of underlying similarities between the devices. The analysis results can be used to refine the systematic condition detection and analysis processes by revising the signature definitions set and/or by modifying data selection.

Abstract: A failure probability for a system having multi-fail regions is computed by generating failure directions in a space whose dimensions are the system parameters under consideration. The failure directions are preferably uniform, forming radial slices. The failure directions may be weighted. The radial slices have fail boundaries defining fail regions comparable to broken shells. The distribution of the system parameters is integrated across the broken shell regions to derive a failure contribution for each failure direction. The failure probability is the sum of products of each failure contribution and its weight. Failure contributions are computed using equivalent expressions dependent on the number of dimensions, which can be used to build lookup tables for normalized fail boundary radii. The entire process can be iteratively repeated with successively increasing failure directions until the failure probability converges.

Abstract: Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed.

Abstract: A method for manufacturing a multiple-chip memory device includes making a volatile memory element on a semiconductor substrate, examining the volatile memory element for one or more initial errors, correcting the one or more initial errors on the semiconductor substrate, incorporating the volatile memory element into the multiple-chip memory device, and incorporating a non-volatile memory element into the multiple-chip memory device. The volatile memory element is examined for one or more secondary errors, after incorporating the volatile memory element and the non-volatile memory element into the multiple-chip memory device. Repair information is stored in a non-volatile memory element, the repair information identifying the one or more secondary errors.

Abstract: Example embodiments are directed to a method of writing an Operating System (OS) image to a semiconductor device having a data storage device, an Application Specific Integrated Circuit (ASIC), and a non-volatile memory. The method includes initializing a DRAM interface of the ASIC using a boot loader, receiving the OS image input from a data writer to the semiconductor device through the DRAM interface; and writing the OS image into the non-volatile memory of the semiconductor device using a Flash Translation Layer (FTL) code.

Abstract: Software (such as server products) operating in a complex networked environment often run on multi-machine installations that are known as machine clusters. A server product can be tested on a server machine type. The server product can be tested by tracking the constituent machines of a machine cluster, and configuring and recording the roles that each machine in the machine cluster plays. Scenarios targeting a single server machine-type can be seamlessly mapped from the single machine scenario to a machine cluster of any number of machines, while handling actions such as executing tests and gathering log files from all machines of a machine cluster as a unit.

Abstract: Apparatus and methods for effecting bad-block testing operations are disclosed herein. In some embodiments, instead of effecting bad-block testing for the majority of the flash memory blocks of a flash memory device during manufacture, most or all bad-block testing is postponed until the end user is in possession of the flash memory device. In some embodiments, after user data is received by the flash memory device from a host device, one or more blocks of the flash memory device are subjected to bad-block testing.

Abstract: In an embodiment, data is captured in a first processor-based system. The captured data is serialized into an XML format. The XML-formatted data is transmitted to a second processor-based system, and the XML-formatted data is deserialized into a non-XML format. The deserialized data is processed on the second processor-based system to determine a cause of an error on the first processor-based system, and the first processor-based system or the second processor-based system is altered as a function of the processing of the deserialized data on the second processor-based system. The processing of the deserialized data on the second processor-based system relates to a support of the first processor-based system, and the first processor-based system is a production system and the second processor-based system is a test or reference system.

Abstract: Storage volumes are provided across a plurality of storage devices, where the storage volumes include at least a first storage volume and a second storage volume. A storage controller detects fault in a portion of a particular one of the plurality of storage devices, where the portion corresponds to the first storage volume. The storage controller identifies the particular storage device as faulty for the first storage volume without identifying the particular storage device as faulty for the second storage volume.

Abstract: An automatic keyboard testing system includes a computer, an automatic testing program and a testing frame. A keyboard circuit board to be tested in placed on the testing frame. The automatic testing program is installed in the computer for generating a testing signal and has a predetermined time period. The testing frame generates a simulating signal according to the testing signal and conducts a key intersection point corresponding to the simulating signal, so that the keyboard circuit board output a key scanning code corresponding to the conducted key intersection point to the computer. The automatic testing program discriminates whether the key scanning code is transmitted to the computer within the predetermined time period.

Abstract: A main board according to example embodiments may include a substrate and at least one socket. The at least one socket may directly connect a memory module to the substrate in a direction parallel to the substrate. A memory mounting test system including the main board may occupy a smaller space, because the memory module is connected to the main board in a direction parallel to the main board.

Abstract: A memory control device is provided. The memory control device is configured to control access to a storage device including a plurality of storage areas. The memory control device includes a defect detecting unit configured to detect a defective area of a storage area into which data may not be stored. The memory control device also includes a storage processing unit configured to store defect information including address information of the defective area detected using the defect detecting unit into a memory area. A data writing unit is also included in the memory control device. The data writing unit is configured to write data, which has been written into the defective area, into a storage area other than the storage area comprising the defective area based on the defect information stored using the storage processing unit.

Abstract: A test system for testing a communication system having a plurality of communication links is disclosed. The test system has a single tester for performing various measurement and diagnostic tasks on a single link. The test system also has a switching system for independently testing any link by coupling the tester into any one link. The tester is coupled into the link by coupling the tester input to the link's transmitter and the tester output to the link's receiver. The switching system couples the tester such that all remaining links of the communication system have a unique one of the plurality of transmitters coupled to a unique one of the plurality of receivers, whereby the operation of the communication system can be maintained while testing individual links.

Abstract: Provided are apparatus and method of testing solid state drives. The method includes accommodating solid state drives to be tested in a magazine with one or more cassettes, sorting the solid state drives into operable solid state drives or defective solid state drives by testing electrical characteristics, and loading the sorted solid state drives.

Abstract: When the system state transition diagram creator sequentially generates transition events based on a system operation specification to create a system state transition diagram, the creator restricts the transition event to be next executed by a scenario state transition diagram restricting the order of execution of the transition events, and test case generator generates a test case based on thus created system state transition diagram.

Abstract: A memory test circuit for testing a memory including a first circuit for performing a logic operation of a test signal, which determines whether the memory is operated in a test mode or in an ordinary operation mode, and an expected value representing a value which is expected to be set to data read from the memory, and a second circuit for outputting an exclusive OR of an output signal from the first circuit and the data read from the memory.

Abstract: An apparatus for use in testing at least a portion of a system under test via a Test Access Port (TAP) is provided. The apparatus includes a memory for storing a set of instructions of a test instruction set architecture and a processor executing the set of instructions of the test instruction set architecture for testing at least a portion of the system under test via the TAP. The set of instructions of the test instruction set architecture includes a first set of instructions including a plurality of instructions of an Instruction Set Architecture (ISA) supported by the processor and a second set of instructions including a plurality of test instructions associated with the TAP. The instructions of the first set of instructions and the instructions of the second set of instructions are integrated to form the set of instructions of the test instruction set architecture.

Abstract: In an embodiment, a system is disclosed. The system has a bus interface port, a selection circuit coupled to the bus interface port, a first bus interface circuit coupled to the selection circuit and a second bus interface circuit coupled to the selection circuit. The selection circuit is configured to select between the first bus interface circuit and the second bus interface circuit. The system also has an initialization circuit configured to detect a first codeword written to the bus interface port, and activate the second bus interface circuit if the first codeword is detected.

Abstract: A life parameter generator generates life parameters related to the life of a nonvolatile memory device by using parameters related to allowable capacity for memory defect and occurrence capacity for memory defect. The life parameters are stored in a life parameter storing block of a nonvolatile memory. An access device reads and displays the stored life parameters. Thus, the user can precisely know the life of the nonvolatile memory device or the moment when a device having a built in nonvolatile memory such as a portable audio becomes unusable.