Abstract: Deterioration of performance due to diagnosis processing performed when a failure occurs is prevented. A storage apparatus 10 includes a controller 11A and a plurality of expanders 112A, 121A coupled to the controller 11A to form a first system, and includes a controller 11B and a plurality of expanders 112B, 121B coupled to the controller 11B to form a second system. The controller 11A accesses the storage drive 171 through the expanders 112A, 121A, and the second controller 11B accesses the storage drive through the expanders 112B, 121B. In the storage apparatus 10, the controller 11A stores a maximum number (concurrently-executable maximum number) of communication ports 80 that are concurrently diagnosable in the first system, and repeatedly executes a process of selecting the communication ports 80 not exceeding the concurrently-executable maximum number and a process of causing the expanders 112A, 121A to diagnose the selected communication ports 80.

Abstract: Disclosed in a method of optimizing a voltage reference signal. The method includes: assigning a first value to the voltage reference signal; executing a test pattern while using the voltage reference signal having the first value; observing whether a failure occurs in response to the executing and thereafter recording a pass/fail result; incrementing the voltage reference signal by a second value; repeating the executing, the observing, and the incrementing a plurality of times until the voltage reference signal exceeds a third value; and determining an optimized value for the voltage reference signal based on the pass/fail results obtained through the repeating the executing, the observing, and the incrementing the plurality of times.

Abstract: Example embodiments relate to a bad area managing method of a nonvolatile memory device. The nonvolatile memory device may include a plurality of memory blocks and each block may contain memory layers stacked on a substrate. According to example embodiments, a method includes accessing one of the memory blocks, judging whether the accessed memory block includes at least one memory layer containing a bad memory cell. If a bad memory cell is detected, the method may further include configuring the memory device to treat the at least one memory layer of the accessed memory block as a bad area.

Abstract: Various embodiments of the present invention provide systems and methods for detecting storage medium defects. As one example, a media defect detection system is disclosed that includes a data detector circuit that applies a detection algorithm to the data input and provides a hard output and a soft output. A first circuit combines a first derivative of the hard output with a derivative of the data input to yield a first combined signal. A second circuit combines a second derivative of the hard output with a derivative of the first combined signal to yield a second combined signal. A third circuit combines a derivative of the soft output with the second combined signal and a threshold value to yield a defect signal.

Abstract: Embodiments related to methods and systems for determining support for a memory card, where the memory card is accessible to a card reader and the card reader is in communication with an accessing device. One embodiment comprises transmitting a first test command to the memory card, receiving a response to the first test command, and determining that the response to the first test command indicates that a card type is not supported by a plurality of card drivers. In response to said determining, at least one additional test command specific to a card type supported by a selected card driver is automatically transmitted, and if the response is successful, the selected card driver, which was previously determined not to support the card type of the memory card, is indicated to support the card type of the memory card.

Abstract: Embodiments are described for managing memory faults. An example system can include a memory controller module to manage memory cells and report memory faults. An error buffer module can store memory fault information received from the memory controller. A notification module can be in communication with the error buffer module. The notification module may generate a notification of a memory fault in a memory access operation. A system software module can provide services and manage executing programs on a processor. In addition, the system software module can receive the notifications of the memory fault for the memory access operation. A notification handler may be activated by an interrupt when the notification of the memory fault in the memory access operation is received.

Abstract: A system, a non-transitory computer readable medium and a method for wear estimation of a flash memory device, the method may include: programming information to a first portion of the flash memory device during a test programming process; measuring a duration of the test programming process; and estimating a wear characteristic of the first portion of the flash memory device thereby providing an estimated wear characteristic, wherein the estimating is responsive to the duration of the test programming process.

Abstract: A method of testing a semiconductor memory apparatus is provided. The data alignment units other than the one data align unit being tested are deactivated. Serial data is input to the activated data alignment unit to generate parallel data. The parallel data is decoded. A test mode signal corresponding to the decoded result is enabled to perform the test. Different serial data is input where the test mode signal is enabled to generate and decode parallel data. Both tests are then performed simultaneously based on a test mode signal corresponding to a result of the decoded parallel data.

Abstract: Performing wear-leveling and bad block management of limited lifetime memory devices. A method for performing wear-leveling in a memory includes receiving logical memory addresses and applying a randomizing function to the logical memory addresses to generate intermediate addresses within a range of intermediate addresses. The intermediate addresses are mapped into physical addresses of a memory using an algebraic mapping. The physical addresses are within a range of physical addresses that include at least one more location than the range of intermediate addresses. The physical addresses are output for use in accessing the memory. The mapping between the intermediate addresses and the physical addresses is periodically shifted. In addition, contents of bad blocks are replaced with redundantly encoded redirection addresses.

Abstract: A storage device includes: a printed circuit board; a semiconductor memory package mounted on the printed circuit board via solder joints, the semiconductor memory package incorporating semiconductor memories; a sensor configured to measure a physical quantity relating to a state of the storage device; a database including a damage estimation model base to be used for estimating damage of the solder joints from the physical quantity measured by the sensor; a damage estimating module configured to calculate a damage estimation value of the solder joints from the physical quantity using the damage estimation model base; and a controller configured to control writing, reading, and erasure of electronic data to or from the semiconductor memories based on the damage estimation values calculated by the damage estimating module.

Abstract: Provided is a test apparatus that tests a memory under test, comprising a testing integrated circuit device that tests the memory under test and includes an internal memory storing test information including at least one of a test result and test data for a partial memory region of the memory under test; an external memory that stores the test information for an entire memory region of the memory under test; and a memory controller that is connected to the external memory and transmits test information for a memory region of a test target between the external memory and the internal memory. Also provided is a test method.

Abstract: A method for detecting faulty operation of a multi-variable system is described. The method includes receiving operational data from a plurality of components of the multi-variable system and processing the operational data in accordance with a plurality of dynamic machine learning fault detection models to generate a plurality of fault detection results. Each fault detection model uses a plurality of variables to model one or more components of the multi-variable system and is adapted to detect normal or faulty operation of an associated component or set of components of the multi-variable system. The plurality of fault detection results are output.

Abstract: Provided is a storage system, including: one or more disk drives storing data; a disk controller for controlling data access to the disk drive; a power supply controller for autonomously turning off a power source of the disk drive according to the data access status to the disk drive, and autonomously turning on the power source of the disk drive, which was turned off, after the lapse of a prescribed period from the time the power source was turned off irrespective of the data access status to the disk drive; and a media inspection unit for inspecting a failure in the disk drive in which the power source thereof was autonomously turned on irrespective of the data access status to the disk drive.

Abstract: To provide a memory system which determines a memory state such as an exhaustion level and allows a memory to be efficiently used. The memory system includes a NAND type flash memory 1 in which data can be electrically written/erased, a nonvolatile memory 2 which counts the number of erase operations of the NAND type flash memory 1 and retains the number of erase operations and a maximum number of erase operations, and a controller 3 which has a connection interface 31 to be given a self-diagnosis command from a computer 4, and retrieves the number of erase operations and the maximum number of erase operations from the nonvolatile memory 2 based on the self-diagnosis command and outputs the number of erase operations and the maximum number of erase operations to the computer 4 through the connection interface 31.

Abstract: A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells, a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads; a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads, a path selection unit configured to transfer the first data, which are input through the first data pads, to both the first and second memory cells, during a test mode, and a test mode control unit configured to compare the first data of the first and second memory cells, and to control at least one of the first data pads to denote a fail status based on a comparison result, during the test mode.

Abstract: An integrated circuit 2 provided with multiple functional units 6, 8, 10, 12, 14, and 16 for performing data processing operations as part of advancing execution of a data processing task by the integrated circuit 2. Activity detection circuitry 26 determines which of these functional circuits is inactive at the given time. If a functional is inactive, then scan control circuitry 28 may perform a scan test operation thereon using an associated serial scan chain 34, 36, 38, 40, 42, 44.

Abstract: System and method for construction, fault isolation, and recovery of cabling topology in a storage area network (SAN) is disclosed. In one embodiment, in a method for construction, fault isolation, and recovery of cabling topology in a SAN, subsystem information associated with each subsystem in the SAN is obtained. Then, an IP port and zoning information associated with connections of each subsystem is obtained. Component information associated with each component is also obtained. Any other relevant information associated with each subsystem and each component is obtained from users. The obtained subsystem information, IP port and zoning information, component information, and any other relevant information are compiled. Test packets are then sent from end-to-end in SAN using compiled information. The sent test packets are tracked via each component in each subsystem in the SAN. The cabling topology of the SAN is then outputted based on the outcome of the tracking.

Abstract: A testing method for a unit under test is provided. At least one unit under test is electrically connected to a testing machine. The testing machine creates a test script and executes the test script, so as to perform a non-operating system (OS) test and an OS test on the unit under test, and the testing machine is capable of combining the testing results, so a testing process is simplified, a test time is shortened, and test accuracy is improved.

Abstract: When an update disable signal is at an inactivation level, a latch signal is activated in accordance with an active signal and a mode register set signal. When the update disable signal is at an activation level, the latch signal is activated in accordance with the active signal while being not activated in accordance with the mode register set signal. Based on the latch signal, the address signal is latched. Based on the latched address signal, an internal test signal is generated. With this structure, a target chip can be selectively controlled simply by activating the update disable signal in the target chip.

Abstract: A method, computer program storage device and apparatus are provided for flexible observability during a scan. In one aspect of the present invention, a method is provided. The method includes providing a selector load input to at least a portion of a scan chain, selecting an observe-only scan mode for the at least a portion of the scan chain based at least upon the selector load input, and providing a data input to a storage element in the scan chain based at least upon the observe-only scan mode. The apparatus includes a first scan chain multiplexor comprising a selector input, a first input terminal, a second input terminal and an output terminal. The apparatus also includes a first scan chain storage element comprising an input terminal and an output terminal, where the input terminal of the first scan chain storage element is communicatively coupled to the output terminal of the first scan chain multiplexor.

Abstract: A method and apparatus to improve the efficiency of debugging a processor is provided. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes receiving a first test data, which identifies a state of a state machine, wherein the state machine performs reset and initialization operations for a processor. The method also includes halting the state machine in the state identified by the first test data upon reaching the state.

Abstract: Verification of a system-under-test (SUT) supporting the functionality of operating a self modifying code is disclosed. A generator may generate a self modifying code. In response to identification that a simulator is about to simulate code generated by the self modifying code, the simulator may simulate the execution in a “rollover mode”. The code may include instruction codes having variable byte size, branching instructions, loops or the like. The simulator may further simulate execution of an invalid instruction. The simulator may perform rollback the simulation of the rollover mode in certain cases and avoid entering the rollover mode. The simulator may perform rollback in response to identifying a termination condition, as to insure avoiding endless loops. The simulator may perform rollback in response to reading an initialized value that is indefinite.

Abstract: An automated emergency power supply system (EPSS) and testing solution that records generator load values and engine exhaust temperature values to evaluate whether an EPSS test satisfies legislated test criteria. The EPSS test is carried out under software control, which initiates a test by instructing an automatic transfer switch (ATS) to change its status to a test status, causing the essential loads to be powered by a generator instead of a main utility power source. Power monitors record the ATS and generator status during the test as well as electrical parameter data from the ATS and generator and exhaust temperature data and other engine parameter data from the generator. When the test is concluded, the ATS is instructed to return the status to normal so that power delivery is resumed from the main power source. The electrical and engine parameter data is analyzed and compared against legislated test criteria to determine a pass/fail result of the EPSS test.

Abstract: A storage device testing system (100) includes at least one 310 robotic arm (200) defining a first axis (205) substantially normal to a 300 floor surface (10). The robotic arm is operable to rotate through a predetermined arc about and extend radially from the first axis. Multiple racks (300) are arranged around the robotic arm for servicing by the robotic arm. Each rack houses multiple test slots (310) that are each configured to receive a storage device transporter (550) configured to carry a storage device (500) for testing.

Abstract: A user of a user computer whose hard disk drive (HDD) is “fried” can press a special key to cause BIOS to automatically gather location information about the computer from its GPS receiver and gather information about the HDD, activate a WWAN transceiver, and automatically send the location and HDD information over the WWAN to a service computer, which may return a location of a nearest service center to the user computer and any other advice including recovery advice for the HDD that the service center might be able to divine from the information sent to it by the user computer.

Abstract: Systems and methods are provided for performing diagnostics on a removable media drive. An example system includes a monitoring unit configured to collect information about a media access to the media drive and a media access to a removable media contained in the media drive. The example system also includes a storage unit having a threshold table with at least one threshold value for the media access to the media drive. A processing unit is configured to compare the collected information of the monitoring unit to the at least one threshold value contained in the threshold table. The processing unit is also configured to determine diagnostic data relating to the removable media drive in accordance with the comparison.

Abstract: Electronic test system including hardware and software components and method of use which provide obsolescence mitigation. A test program set (TPS) including a test program test is created to enable units to be tested. When a new component is introduced, the change is detected and a new TPS is created with at least part of the test program test. If the new TPS complies with defined, governing rules for the system, testing using the new TPS is possible. If not, a determination is made as to whether any component of the TPS is obsolete and if not, the units can be tested using the new TPS without redefining the rules. When a component of the TPS is obsolete, the rules are reviewed to ascertain the effect of removal of the component and optionally redefined to enable the new component to be used in combination with the remaining components.

Abstract: In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.

Abstract: A scan test of a first latch and a second latch couples a given scan value to the input of the first latch, to switch the first latch to a state corresponding to the scan value, uncouples the scan value from the first latch to latch the first latch at that state, couples the output of the first latch while latched at that state to the input of the second latch to switch the second latch to that state, and uncoupling the output of the first latch from the input of the second latch to latch the second latch at that state.

Abstract: A method for identifying non stuck-at faults in a read-only memory (ROM) includes generating a golden value of a victim cell, providing a fault-specific pattern through an aggressor cell, generating a test reading of the victim cell in response to the provided fault-specific pattern, and determining whether the ROM has at least one non stuck-at fault. The determination is based on a comparison of the golden value and the test reading of the victim cell.

Abstract: A method tests peripheral component interconnect express (PCI-E) switches. A second PCI-E switch to be tested electronically connects to a first PCI-E switch of a computing device. A first data packet is created by the computing device and sent from the first PCI-E switch to the second PCI-E switch. A second data packet sent back by the second PCI-E switch is received by the computing device. The second PCI-E switch works normally if the first data packet is identical to the second data packet. The second PCI-E switch does not work normally if the first data packet is not identical to the second data packet.

Abstract: Systems and methods are disclosed for generating dynamic super blocks from one or more grown bad blocks of a non-volatile memory (“NVM”). In some embodiments, a dynamic super block can be formed by striping together a subset of memory locations of grown bad blocks from one or more dies of a NVM. The subset of memory locations may be selected based on at least one reliability measurement of the subset of memory locations. In some embodiments, in response to detecting one or more access failures in a portion of the dynamic super block, the NVM interface can retire at least a portion of the dynamic super block. In some embodiments, the NVM interface can reconstruct a new dynamic super block from the dynamic super block by progressively increasing the size of the new dynamic super block.

Abstract: A computer turning on/off testing apparatus for turning on a computer automatically includes a control module, a switch module, and a power supply module. The control module outputs control signals and receives a turn on signal from the computer to determine whether the computer turns on successfully. The switch module receives the control signals and turns on/off the computer according to the control signals. The power supply module provides power to the control module and the switch module. The control module stores a predetermined test time. The control module records abnormal information and test times when the computer turns on/off, and outputs the control signals to turn on the computer again when the computer cannot restart. The computer is turned on and off until a turning on/off time of the computer is equal to the predetermined test time.

Abstract: A hot button can be pressed to cause a computer to execute a series of diagnostic tests to identify the cause of poor computer performance. When a cause is determined a website address can be presented that a user can access to purchase goods or services to alleviate the cause, and billing information may be generated in response to presentation of the website.

Abstract: An identification code generation method and a management method for a non-volatile memory, and a controller and a storage system using the same are provided, and the non-volatile memory has a plurality of physical blocks. The identification code generation method includes testing the physical blocks to obtain an availability state of the physical blocks and identifying a plurality of good physical blocks or bad physical blocks among the physical blocks according to the availability state. The identification code generation method also includes generating a memory identification code corresponding to the non-volatile memory according to the good physical blocks or the bad physical blocks. Thereby, in the present invention, a unique memory identification code is generated and is prevented from being stolen.

Abstract: A data processing system and method for regulating a voltage supply to functional circuitry of the data processing system is provided. The functional circuitry is configured to operate from a voltage supply whose voltage level is variable, the functional circuitry having at least one error correction circuit configured to detect errors in operation of the functional circuitry and to repair those errors in operation. Voltage regulator circuitry provides the voltage supply to the functional circuitry, and modifies the voltage level of the voltage supply based on a feedback control signal. Error rate history circuitry receives error indications from the error correction circuit during operation of the functional circuitry and generates error rate history information therefrom.

Abstract: Methods, apparatuses and systems are disclosed involving a memory device. In one embodiment, a memory device is disclosed that includes a command error module of the memory device operably coupled to at least one of a command signal and an address signal and configured to detect and report a parity error on the command signal, the address signal, or combinations thereof In some embodiments, a memory device may include a temperature sensor operably coupled to a mode register. The temperature sensor may be configured to sense a device temperature and report a temperature status. Furthermore, the memory device may be incorporated into a memory module, which may be included in an electronic system.

Abstract: The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures using the rising edge of the test/scan clock. According to the disclosure, device test leads serve to input different test signals on the rising and falling edge of the test/scan clock which reduces the number of interconnects between a tester and the device under test.

Abstract: Described are techniques for detecting data collisions between a first portion and a second portion of an application executing on a computer, the first portion and the second portions executing concurrently with respect to each other. While the first portion and second portion are executing, before the first portion accesses a memory location shared by the first portion and the second portion, a value stored in the memory location is captured and the first portion is delayed. While the second portion continues to execute the first portion is delayed. After a period of the first portion having been paused or slowed, the current content of the memory location is compared with the captured content to determine if there is a data collision. The first and second portions may be threads, and the capturing, delaying, and determining may be performed by code inserted to the application after it has been compiled.

Abstract: Monitoring and repairing memory includes selecting a first memory bank comprising a plurality of memory cells to analyze. The plurality of memory cells are copied from the first memory bank to a second memory bank, wherein a request to access the first memory bank is redirected to the second memory bank. A determination is made whether the first memory bank comprises an error of the memory cell.

Abstract: An objective is to allow a storage apparatus to accurately locate a failure site upon occurrence of a failure. Provided is a storage apparatus 10 including: a controller 11 that performs data input and data output into and from a storage drive 171 in response to a data input/output request sent from an external device 2; and expanders 112, 121 each having a switch circuit 1122 provided with a physical port (Phy 1121). In this storage apparatus 10, the controller 11 performs a loopback diagnosis on the expanders 112, 121, and performs a connection-based diagnosis on a target device by sending a connection frame thereto, the target device being a device detected as having a failure. When a response to the connection frame includes information indicating a failure, the controller 11 disables the physical port to which the target device is coupled, or the physical port of the switch circuit 1121 existing on a path from the controller 11 to the target device.

Abstract: Example methods, apparatus and articles of manufacture to diagnose temperature-induced memory errors are disclosed. A disclosed example method to diagnose a temperature-induced memory error includes detecting a memory error associated with a memory device, and writing a highest measured temperature of the memory device in the memory device when the memory error is detected, the highest temperature measured temporally near the detected memory error.

Abstract: An apparatus and method for determining an abnormal ROM update in a portable terminal. The apparatus includes a ROM update unit for increasing a value of an update start counter when a ROM update process is performed, and increasing a value of an update finish counter when the ROM update process is finished. The ROM update unit loads the values of the update start counter and the update finish counter, and compares the values of the two counters to determine that the ROM update process has been normally performed before the portable terminal abnormally operates.

Abstract: A test and measurement instrument includes a pattern detector for detecting a beginning sequence in a signal under test (SUT), and generates a synchronization signal. In response to the synchronization signal, a memory outputs a reference test pattern. A symbol comparator compares the reference test pattern with the SUT. The symbol comparator can produce a symbol error rate. One or more 8b to 10b converters receives the SUT from the input and the digitized data from the memory, and converts the data from an 8b coded format to a 10b coded format. A bit comparator compares the 10b coded reference test pattern with the 10b coded SUT in response to the symbol comparator. The bit comparator is coupled to a bit error counter, which produces a bit error rate independent of any disparity errors that may be present in the incoming digitized data received by the test and measurement instrument.

Abstract: A boot test apparatus and method can repeatedly execute actions of power-on and power-off for a cold boot test of a computer to test whether the computer is operable. The boot test apparatus includes a microprocessor, a controller, and a power switch. The microprocessor generates a control signal according to a period voltage provided by an internal power supply. The control signal includes a pulse signal and a voltage signal. The controller controls a power switch to send the pulse signal to the computer through a power button of the computer, and controls the power switch to send the voltage signal to the computer through a power input port of the computer. The microprocessor further obtains test information from the computer when the computer executes a cold boot process according to the control signal, and displays the test information on an LED when the cold boot process is abnormal.

Abstract: A device for testing a serial interface of a circuit board. The device includes a testing serial interface, a memory, a processor. The testing serial interface is coupled to the serial interface of the circuit board. The processor is electrically connected between the memory and the at least one testing serial interface. The processor is configured for receiving first serial data from the circuit board via the testing serial interface, converting the first serial data to parallel data, and writing the parallel data into the memory, and also configured for reading the parallel data from the memory, converting the parallel data to second serial data and transmits the second serial data to the circuit board via the testing serial interface.

Abstract: An apparatus for generating and managing logical units (LUNs) in a storage network environment is disclosed herein. In one embodiment, such an apparatus includes an identification module to identify a type of LUN, one or more servers that will access the LUN, and a storage system that will host the LUN. A mapping module maps the type, the one or more servers, and the storage system to one more abbreviations. A naming module then generates a LUN name that encapsulates the abbreviations. An assignment module may then assign the LUN name to the LUN. A corresponding method and computer program product are also disclosed herein.

Abstract: A testing device for testing an embedded system includes an interface capable of being coupled to the embedded system by means of insertion, a storage unit for storing data, and a processor for receiving a testing message corresponding to a testing command from the embedded system via the interface according to an enabling signal and storing the testing message into the storage unit when the interface is coupled to the embedded system.

Abstract: Systems and methods are disclosed for managing a non-volatile memory (“NVM”), such as a flash memory. The NVM may be managed based on results of a test performed on the NVM. The test may indicate, for example, physical memory locations that may be susceptible to errors, such as certain pages in the blocks of the NVM. Tests on multiple NVMs of the same type may be compiled to create a profile of error tendencies for that type of NVM. In some embodiments, data may be stored in the NVM based on individual test results for the NVM or based on a profile of the NVM type. For example, memory locations susceptible to error may be retired or data stored in those memory locations may be protected by a stronger error correcting code.

Abstract: A system for detecting memory corruption in an engine control module includes a variable selection module, an output module, an input module, and a response comparing module. The variable selection module selects a variable of a control system for testing. The output module outputs a predetermined value of said variable to a memory location where said variable is stored in said engine control module. The input module receives a response of said control system to said predetermined value when said predetermined value is written in said memory location. The response comparing module compares said response to a predetermined range and determines that said memory location is defective when said response is not within said predetermined range.