Abstract: In an integrated circuit device, a power circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The device includes a power circuit disposed along the periphery of the device, the power circuit configured to maintain power when the device is placed in a low-power mode. A plurality of input output blocks are included in the device and are for receiving external inputs for the integrated circuit device and for providing outputs from the integrated circuit device. The power circuit is coupled to provide power to at least one of the input output blocks to maintain state when the integrated circuit device is in the low-power mode.

Abstract: Methods reduce the number of newly created cells when creating new cells to optimize a design. Cells are created to optimize a design, but neighbor cells fitting a distribution of drive strengths and P/N ratios are used instead. This allows reducing the number of newly created cells to optimize the design, through uniquification of neighbor instances with respect to the distribution grid.

Abstract: A high-level synthesis device, which converts a behavior description file describing a function of an integrated circuit using a high-level language without timing description, into a hardware description file describing the integrated circuit including timing description, has: a processor; a high-level synthesis unit in which the processor converts a behavior description file having a functional portion describing the function and a control portion controlling timing, into a first hardware description file; a variable extraction unit; a loop information generation unit; a static latency extraction unit; a latency calculation circuit generation unit in which the processor generates a second hardware description file describing a latency calculation circuit which generates the latency information based on loop count and static latency; and an insertion unit in which the processor inserts the second hardware description file into the first hardware description file to generate a third hardware description file.

Abstract: Systems and methods for identifying a Boolean function as either a threshold function or a non-threshold function are disclosed. In one embodiment, in order to identify a Boolean function as either a threshold function or a non-threshold function, a determination is first made as to whether the Boolean function satisfies one or more predefined conditions for being a threshold function, where the one or more predefined conditions include a condition that both a positive cofactor and a negative cofactor of the Boolean function are threshold functions. If the one or more predefined conditions are satisfied, a determination is made as to whether weights for the positive and negative cofactors are equal. If the weights for the cofactors are equal, then the Boolean function is determined to be a threshold function. Further, in one embodiment, this threshold function identification process is utilized in a threshold circuit synthesis process.

Abstract: A method is provided to convert an analog mixed-signal schematic design to a digital netlist: digital blocks within the schematic design are converted to digital netlist modules; analog blocks within the schematic design are converted to analog netlist modules: at least one digital netlist module includes a first identifier for a component that is shared between at least one digital block and at least one analog block within the schematic design; an analog netlist module that corresponds to the at least one analog block within the design includes a second identifier for the shared component that is different from the first identifier; the analog netlist modules are converted to corresponding digital netlist modules; the first identifier is substituted for the second identifier in the course of translating the analog netlist module that corresponds to the at least one analog block.

Abstract: Methods, systems, and computer program products may provide planning for hardware-accelerated functional verification in data processing systems. A method may include receiving, by a computer system, a description of architecture of a hardware accelerator for accelerating functional verification of a circuit design, the architecture including a plurality of logical processors. The method may additionally include receiving, by the computer system, a description of the circuit design having a plurality of gates, and representing, by the computer system, each gate, each stage of the functional verification, and each logical processor as a separate object based on the received description of the architecture and the circuit design.

Abstract: A logical and topological based software method of detecting level shifter circuits in complex integrated circuit designs. The method, which identifies level shifters by various design rules such as suitably connected PFET and NFET pairs in various circuit contexts, rather than prior art simulation methods, can identify and mark various devices and circuits as being part of a level shifter, and also place the identified level shifters within the context of the integrated circuit chip's various power domains. In some embodiments, the method, working with little or no a-priori information other than the integrated circuit's netlist computer file, can automatically trace power and signal lines, automatically determine power domains, and automatically flag when signal lines between different power domains are not adequately protected by level shifters.

Abstract: Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.

Abstract: A computer-implemented method simplifies a netlist, verifies the simplified netlist using induction, and remaps resulting inductive counterexamples via inductive trace lifting within a multi-algorithm verification framework. The method includes: a processor deriving a first unreachable state information that can be utilized to simplify the netlist; performing a simplification of the netlist utilizing the first unreachable state information; determining whether the first unreachable state information can be inductively proved on an original version of the netlist; and in response to the first unreachable state information not being inductively provable on the original netlist: projecting the first unreachable state information to a minimal subset; and adding the projected unreachable state information as an invariant to further constrain a child induction process.

Abstract: A programmable transistor array circuit is disclosed comprising a semiconductor substrate; and a plurality of basic transistor units (BTUs) arranged in rows and columns of uniformly spaced cells, the BTUs further comprising PMOS transistor units (PTUs), NMOS transistor units (NTUs) and dummy transistor units (DTUs) each BTU having conductors arranged in a single direction running through the BTUs and the conductors being uniformly spaced with respect to each other. The arrangement of the BTUs is subject to restricted design rules. Logical transistor units (LTUs) are formed from the BTUs using first and second layers of metallization. Additional embodiments are disclosed incorporating the programmable transistor array circuit.

Abstract: An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLMDFG and HLMDFG. RTLMDFG and HLMDFG are then put into timestep form and are called RTLMts and HLMts. A test bench CSts is selected that couples RTLMts and HLMts. The combination of RTLMts[t], HLMts [t] and CSts[t] can have parts designated as datapath. Parts designated as datapath can be subject to a form of equivalence checking that seeks to prove equivalence by a form of inductive theorem proving that propagates symbolic values indicative of whether a node carries the same data content as another node. The theorem proving starts from initial conditions for HLMts [t] determined by partial execution of the HLM. Propagation to a combinational function output can be determined from equivalence relationships between it and another combinational function. Propagation through a multiplexer can produce a conditional symbolic value.

Abstract: A system and methods are disclosed for inferring higher level descriptions of circuit connectivity from register transfer level (RTL) netlists in order to provide more understandable and manageable design descriptions for complex System-on-Chip (SOC) designs. In particular, rule-based interface matching is automatically performed by analyzing actual port names on instances of functional elements and blocks to form signal groupings that comprise a higher-level abstracted description. An example syntax is provided for defining rules that are used to define how various analysis are performed. Data describing standard interfaces on common Intellectual Property (IP) blocks is optionally made available to facilitate interface matching. Also, a facility is included to allow user-guided mapping on instantiated interfaces with respect to actual port names in an RTL-level design.

Abstract: An embodiment includes an integrated circuit (IC) for using direct memory access (DMA) to initialize a programmable logic device (PLD), the IC operably coupled to the PLD. The IC includes an input/output (I/O) interface and a PLD interface. The I/O interface converts a signal format between the IC and the PLD. The PLD interface includes a configuration and status register, a data buffer, and pacing logic. The configuration and status register is adapted to manipulate a control line of the PLD to configure the PLD in a programming mode via the I/O interface. The data buffer temporarily holds PLD programming data received from a DMA control at a DMA speed. The pacing logic controls the speed of transmitting the PLD programming data to a programming port on the PLD via the I/O interface at a PLD programming speed.

Abstract: Circuit elements are characterized for effects of proximity context on electrical characteristic. Based on the characterization, proximity context cell models, and corresponding modeled electrical characteristic values are obtained. Logic cells are characterized and modeled according to the proximity context cell models. Optionally the electrical characteristic can be time delay, leakage, dynamic power, or coupling noise among other parameters.

Abstract: A novel set of reconfiguration tools combine the RTL (Register Transfer Language) construct detection of synthesis compilers with a more advanced implementation of expansion syntax. HDL (Hardware Description Language) coding constructs are automatically detected and recoded and/or modified, for both behavioral and structural HDL code. Configuration file(s) may be used to define the transformations, and transformation commands within the configuration file(s) may define where and how to apply RTL changes. The tool may automatically identify sections of code as the file is parsed (e.g. like a compiler). The transformations are written out in RTL, and the resulting reconfigured RTL file(s) may be processed by a synthesis tool, or may be simulated using a suitable simulator. This allows for automated detection and configurable modification of HDL-coding constructs. Design changes may therefore be verified earlier in the design process, since changes are embedded in RTL, instead of being embedded in the netlist.

Abstract: To include a first semiconductor chip including driver circuits, a second semiconductor chip including receiver circuits, and through silicon vias provided in the second semiconductor chip. The first semiconductor chip includes an output switching circuit that exclusively connects an output terminal of an i-th driver circuit (where i is an integer among 1 to n) to one through silicon via among an i-th through silicon via to an (i+m)-th through silicon via. The second semiconductor chip includes an input switching circuit that exclusively connects an input terminal of an i-th receiver circuit (where i is an integer among 1 to n) to one through silicon via among the i-th through silicon via to the (i+m)-th through silicon via. With this configuration, because a difference in wiring lengths does not occur between signal paths before and after replacement of through silicon vias, the signal quality can be enhanced.

Abstract: A semiconductor device having a tensile and/or compressive strain applied thereto and methods of manufacturing the semiconductor devices and design structure to enhance channel strain. The method includes forming a gate structure for an NFET and a PFET and forming sidewalls on the gate structure for the NFET and the PFET using a same deposition and etching process. The method also includes providing stress materials in the source and drain regions of the NFET and the PFET.

Abstract: A method for designing a system on a target device is disclosed. A system is synthesized by converting a high level description of the system into gates, registers, and reset circuitry. An analysis is performed to identify and remove redundant reset circuitry. The system is optimized after the redundant reset circuitry has been removed. Other embodiments are disclosed.

Abstract: Methods and apparatus are described in which, at design-time a thorough analysis and exploration is performed to represent a multi-objective “optimal” trade-off point or points, e.g. on Pareto curves, for the relevant cost (C) and constraint criteria. More formally, the trade-off points may e.g. be positions on a hyper-surface in an N-dimensional Pareto search space. The axes represent the relevant cost (C), quality cost (Q) and restriction (R) criteria. Each of these working points is determined by positions for the system operation (determined during the design-time mapping) for a selected set of decision knobs (e.g. the way data are organized in a memory hierarchy). The C-Q-R values are determined based on design-time models that then have to be “average-case” values in order to avoid a too worst-case characterization. At processing time, first a run-time BIST manager performs a functional correctness test, i.e. checks all the modules based on stored self-test sequences and “equivalence checker” hardware.

Abstract: Methods and apparatuses for circuit design to reduce power usage, such as reducing temperature dependent power usage, and/or to improve timing, such as reducing temperature dependent delay or transition time. At least one embodiment of the present invention reduces the power dissipation and improves the timing of an integrated circuit to optimize the design. A thermal analysis is used to determine the temperature dependent power dissipation of a circuit and the temperature distribution of the circuit resulting from dissipating the heat created by the temperature dependent power dissipation. Then, the components of the design are selectively transformed to reduce the power dissipation and to improve timing based on the temperature solution. The transformation may include placement changes and netlist changes, such as the change of transistor threshold voltages for cells or for blocks of the circuit chip.

Abstract: Methods for fabricating a device structure such as a bipolar junction transistor, device structures for a bipolar junction transistor, and design structures for a bipolar junction transistor. The device structure includes a collector region formed in a substrate, an intrinsic base coextensive with the collector region, an emitter coupled with the intrinsic base, a first isolation region surrounding the collector region, and a second isolation region formed at least partially within the collector region. The first isolation region has a first sidewall and the second isolation region having a second sidewall peripherally inside the first sidewall. A portion of the collector region is disposed between the first sidewall of the first isolation region and the second sidewall of the second isolation region.

Abstract: In a particular embodiment, a method is disclosed that includes automatically adding a first power line in a channel between at least two macros when less than two system power supply lines with opposite polarities are detected within the channel.

Abstract: The present disclosure relates to a computer-based method and apparatus for determining datapath bit slices. A first two-way search is performed between an input vector and an output vector to identify gates in a datapath. A network flow is then constructed including the gates identified, and a min-cost max-flow algorithm is applied to the network flow to derive matching bit pairs between the input vector and the output vector. Next, the datapath bit slices are determined by performing a second two-way search between each of a starting bit in the input vector and an ending bit in the output vector of each of the matching bit pairs.

Abstract: A design data dependency managing apparatus comprises an input/output data storing unit for storing design input/output dependency information indicating a dependency between design input/output data, which becomes an input/output of a design, and other design input/output data in association with the design input/output data, and a design execution environment constructing unit for generating design data dependency information indicating a version number, on which a dependency is made, of the design input/output data required for the design by using the design input/output dependency information, and for constructing a design execution environment.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure comprises: a conductive structure surrounding and accommodating a circuit or a circuit device arranged on a substrate and at least one feed through capacitor and one transmission line associated with the conductive structure and providing the power supply and signals to the circuit or circuit device respectively. The design structure also comprises a shielding structure surrounding a circuit or a circuit device arranged on a substrate and at least one feed through capacitor or a transmission line arranged on a side of the shielding structure.

Abstract: Mechanisms are provided for generating a physical layout of an integrated circuit design. A logic description of the integrated circuit design is received that comprises a first logic description of an irregular logic block of the integrated circuit design and a second logic description of a regular logic block of the integrated circuit design. A manual design of the regular logic block of the integrated circuit design is performed based on user input and an automated design of the irregular logic block of the integrated circuit design is performed without user input. The manual design of the regular logic block and the automated design of the irregular logic block are then integrated into the integrated circuit design to generate a hybrid integrated circuit design.

Abstract: A method of parsing integrated circuit layout design data. According to some implementations, the segment boundaries are designated by first identifying data in the integrated circuit layout design data that matches a cell record start value. Next, the subsequent data is parsed, until a threshold amount of subsequent data has been parsed without identifying another cell record start value. When the threshold amount of subsequent data has been parsed without identifying another cell record start value, the next data in the integrated circuit layout design data matching a cell record start value is designated as a segment boundary. Integrated circuit layout design data can be segmented sequentially, or by using dyadic division. Once the integrated circuit layout design data has been broken up into segments, the segments can be provided to a parallel processing computing system for parsing in parallel.

Abstract: A power gate includes a series of electrical contacts along at least a portion of an integrated circuit and a series of power gate transistors electrically coupled to the electrical contacts on the integrated circuit to form a power gate boundary, e.g., at the integrated circuit periphery. The electrical contacts along at least a portion of a running length of the power gate boundary define a substantially non-linear profile. The non-linear profile provides increased contact density which improves current balancing across the electrical contacts and current throughput through the power gate. The non-linear profile is a sinusoidal or zigzag pattern with intermediate offset bump contacts. The contact profiles along the power gate boundary can include both linear and non-linear profiles.

Abstract: A computer-readable medium stores therein a correcting program that causes a computer to execute a process. The process includes decomposing a correction subject assertion, based on a logical structure of the correction subject assertion; detecting by simulation of a circuit-under-test and from among properties obtained by decomposing the correction subject assertion, a property that has failed; concatenating to the detected property and by logical OR, a failure source; and outputting the concatenated property.

Abstract: An efficient method for selecting a minimal and statistically relevant set of SER sensitive logic devices critical to the SER robustness for a design, through identification by device type, identification nomenclature, connectivity and context. The minimal set of devices comprise the set of fault injection test points using a conventional fault injection test verification environment to establish an SER induced failure rate a logic design. The selection method affords a design independent means to evaluate any design regardless of the origin, source language or documentation by working at the common logic device level “gate-level” netlist format for the design data. The selected set of devices is distilled from the design data by successively filtering the design through a series of heuristic rule-based device identifier computer programs that group and annotate the devices into specific database records.

Abstract: A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.

Abstract: The invention concerns a computer implemented method of circuit conception of a clock tree (200) comprising: a plurality of pulse generators (202) each being coupled to the input of one or more pulsed latches and being arranged to generate a pulsed signal (PS); and a tree of buffers (204) for supplying a clock signal (CLK) to the pulse generators, the method comprising: the conception of the clock tree without pulse generators based on a timing analysis by the computer of the propagation of clock edges in the clock tree; and replacing by the computer in the clock tree at least one buffer, coupled to the input of each pulsed latch, by a pulse generator.

Abstract: A programmable circuit includes a physical interface at an input output (IO) periphery of the programmable circuit. The programmable circuit also includes a partial reconfigurable (PR) module, at the IO periphery of the programmable circuit, to implement a sequencer unit operable to configure the physical interface during a first instance of the PR module, and a controller unit operable to translate commands to the physical interface during a second instance of the PR module.

Abstract: In one embodiment of the invention, an object oriented autorouter is disclosed for routing nets in a circuit. The object oriented autorouter includes a routing data model (RDM); at least one routing engine, such as a single connection router (SCR), a topographical (TOPO) transformation engine, and a detail geometric (DETAIL) engine, and a command and control module (CCM) coupled together. The RDM reads and write data with a design database as well as reading one or more object oriented design constraints. Each of the routing engines have at least one action to operate on the design database to improve compliance of the circuit to a constraint. The CCM controls the overall routing process of the nets in the circuit and includes at least one director to invoke at least one of the routing engines to achieve compliance with one or more constraints.

Abstract: Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into multilayer cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a multilayer structure and a method of manufacture are presented.

Abstract: Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for instance, a circuit description indicative of the layout of signal wires and ground wires in the circuit is received. The signal wires and the ground wires are grouped into at least a first bundle and a second bundle, wherein the first bundle and the second bundle each comprise a respective signal-wire segment and one or more corresponding ground-wire segments. A representative dipole moment is calculated for the first bundle. Using the representative dipole moment, the mutual inductance between the first bundle and the second bundle is calculated. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing design databases created or modified using any of the disclosed techniques are also disclosed.

Abstract: A method of optimizing power and timing for an integrated circuit (IC) chip, which uses an IC technology that exhibits temperature inversion, by modifying a voltage supplied to the IC chip, while meeting power consumption and timing delay performances across lower and higher temperature ranges. A high voltage is selected that meets a closed timing analysis across a full temperature range to meet a timing performance and a low voltage is selected to meet the timing performance and the power performance across a lower temperature range to a temperature cut point in the higher temperature range. The IC chip is turned on at the high voltage and the high voltage is lowered to the low voltage when the temperature cut point is exceeded to meet the power performance while maintaining the timing performance.

Abstract: A method for identifying and removing redundant signal paths includes determining whether a given input to a logic circuit is coupled to both an input of a cone of logic of a data input of a clocked state element and a clock gate circuit that is coupled to disable a clock input to the clocked state element. The method may include removing the given input from the cone of logic such that the given input is no longer coupled to the input of the cone of logic responsive to determining that the given input is coupled to both the input of the cone of logic and the clock gate circuit. The method may include preserving the given input to the clock gate circuit such that the given input continues to be coupled to the clock gate circuit after being removed from the input of the cone of logic.

Abstract: A processing device programming system automatically provides a user interface comprising a selectable list of one or more processing devices based on a system level solution, automatically generates an embedded programmable system solution from the system level solution and a processing device selected from the selectable list of one or more processing devices, and automatically programs the processing device according to the embedded programmable system solution.

Abstract: A system and method for increasing processor throughput by decreasing a loop critical path. In one embodiment, a table comprises multiple stack entries, each comprising an x87 floating-point (FP) stack specifier. The combinatorial logic for operand translation of N FP instructions per clock cycle may require N instantiated copies of a combinatorial logic block. Each instantiated copy may determine a new ordering of the stack entries. Control logic may receive necessary information from the corresponding N FP instructions and determine a corresponding combined computational effect, or stack reordering, on entries within the table based on two or more instructions. Resulting control signals are conveyed to the N instantiated copies. A resulting accumulative delay from an input of the first copy to the output of the Nth copy may be less than or equal to (N?1)*time_delay versus a longer N*time_delay.

Abstract: An apparatus is disclosed that may include an integrated circuit (IC) with an initialization bus configured to communicate with at least one low power mode latch operating during a initialization mode to set a value into the low power mode latch and configured to respond to the assertion of a low power mode signal by selecting the low power mode latch state to drive at least one logic gate to minimize leakage current during the low power mode. The IC may similarly configure and operate a RAM. A leakage control table may be used during initialization mode and created by other embodiments. The net list of a circuit block including at least part of the configuration block and lower power control latch may be used and/or modified to create a new net list to further minimize leakage current during low power mode. Installation packages and program systems are disclosed.

Abstract: A method and apparatus for performing template-based classification of a circuit design are disclosed. A template file is read that defines a plurality of channel-connected-region (CCR) templates. A graph is formatted for each of the CCR templates. A plurality of CCRs are identified based on a partitioned netlist file that defines a given circuit design. A graph is generated for each of the identified CCRs. A matching CCR template graph is identified for each generated CCR graph. The template file may further defines super-CCR templates, and a graph may be formatted for each of the super-CCR templates. All possible combinations of CCRs and previously-matched super-CCRs that are candidates to match the formatted super-CCR template graph may be determined in an interative manner, for each formatted super-CCR template graph. A determination may be made as to which of the candidate combinations actually match the formatted super-CCR template graph.

Abstract: A method for calculating an indicator value includes: extracting features, which are mutually independent, by using data stored in a data storage unit storing, for each group of circuits implemented on a semiconductor device, the number of actual failures occurred in the group and a feature value of each feature that is a failure factor; generating an expression of a failure occurrence probability model, which represents a failure occurrence probability, which is obtained by dividing a total sum of the numbers of actual failures by the number of semiconductor devices, as a relation including a sum of products of the feature value of each of the extracted features and a corresponding coefficient, by carrying out a regression calculation using data stored in the data storage unit; and calculating an indicator value for design change of the semiconductor device from the generated expression of the failure occurrence probability model.

Abstract: By carrying out circuit simulations, paretos that are non-dominated solutions in a solution specification space for respective items in the requirement specification are obtained for all of circuit configurations having possibility that requirement specification is satisfied, and a provisional optimal solution, which is on a pareto curved surface identified by the obtained paretos and whose distance with the requirement specification is shortest, is identified. Furthermore, a circuit configuration corresponding to the provisional optimal solution is identified and the provisional optimal solution is mapped to values of circuit parameters. Then, the pertinent circuit configuration and values of the circuit parameters, which are obtained by the mapping, are outputted.

Abstract: There is provided with a device that includes a first inputter inputting design description which includes functions; a second inputter inputting type specifying description corresponding to the functions, each of which specifies a type for a return value of each corresponding function, and the description of at least one function of the functions specifies a type for a return value of a first function which is an other function of functions; a determiner determining a type of the return value of the first function to a comprehensive type to comprehend the types specified by the type specifying description corresponding to the first function and the at least one function and a type of the return value of a second function which is a function than the first function to the type specified thereto.

Abstract: A method includes simulating a first design of a semiconductor memory that includes at least one device disposed between and coupled to a memory bit cell and to a power supply line, determining if at least one simulated operational value of the semiconductor memory is above a threshold value, and adjusting at least one of a size of the device or a type of the device if the at least one simulated operational value is below the threshold value. The memory bit cell is disposed in a column including a plurality of bit cells. The size or type of the device is repeatedly adjusted and the design of the semiconductor memory is repeatedly simulated until the at least one simulated operational value is at or above the threshold value.

Abstract: A reference generator with programmable m and b parameters and methods of use are provided. A circuit includes a first generator operable to generate a first voltage including a fraction of a supply voltage. The circuit further includes a second generator operable to generate a second voltage. The circuit further includes a mixer and buffer circuit operable to output a reference voltage including a sum of the first and second voltages.

Abstract: In one embodiment, the invention is a method and apparatus for soft hierarchy-based synthesis for large-scale, high-performance circuits. One embodiment of a method for physically synthesizing a design of an integrated circuit includes compiling a logical description of the design into a flattened netlist, extracting a soft hierarchy from the flattened netlist, wherein the soft hierarchy defines a boundary on a die across which cells of the integrated circuit are permitted to move, and placing a cell of the integrated circuit on the die in accordance with the soft hierarchy.

Abstract: A method and circuit for implementing die stacking to distribute a logical function over multiple dies, die identification and sparing in through-silicon-via stacked semiconductor devices, and a design structure on which the subject circuit resides are provided. Each die in the die stack includes predefined functional logic for implementing a respective predefined function. The respective predefined function is executed in each respective die and a respective functional result is provided to an adjacent die in the die stack. Each die in the die stack includes logic for providing die identification. An operational die signature is formed by combining a plurality of selected signals on each die. A die signature is coupled to a next level adjacent die using TSV interconnections where it is combined with that die signature.

Abstract: Techniques and tool for selecting compilation parameter values for compiling a first description of a circuit design, such as a register transfer language description, into a second description of the circuit design, such as a model description for implementation with an emulator are provided. According to various examples of the invention, a compilation tool “elaborates” the first description of the circuit design into a third description for the circuit design. Typically, the third description or “elaboration” will cross one or more hierarchical boundaries represented in the first description of the circuit design, so that the elaboration will represent at least a portion of two or more hierarchical modules in the first description design according to a non-hierarchical or “flat” manner. Also, with some implementations of the invention, the elaboration may include only a simple representation of a corresponding portion of the circuit design.