Abstract: A method and system to map density and temperature of a chip, in situ, is disclosed. The method includes measuring a propagation time that a mechanical propagation wave travels along at least one predefined path in a substrate. The method further includes calculating an average substrate density and temperature along the at least one predefined path as a function of the propagation time and distance. The method further includes determining a defect or unauthorized modification in the substrate based on the average substrate density being different than a baseline substrate density.

Abstract: A technique validates results from a circuit simulation estimation program. The technique determines whether the estimated results satisfy Kirchhoff's current law (KCL), Kirchhoff's voltage laws (KVL), and power conservation for the original circuit. A reporting tool shows the validation results and may be customized by the user. The tool can show in the original circuitry where the estimated results may be inaccurate.

Abstract: A semiconductor integrated circuit device is disclosed. The semiconductor integrated circuit device includes a first circuit whose output never or seldom changes when the output from an Enable generator is off, a second circuit whose output frequently changes, an input controller which receives the respective outputs from the second circuit and the Enable generator and passes through the input from the second circuit only when the output from the Enable generator is on, a combination circuit which receives the respective outputs from the first circuit and the input controller, and a memory which receives the output from the combination circuit and is driven by the output from the clock controller.

Abstract: A counter/timer circuit and a method of operating the counter/timer circuit are described. In one embodiment, a method of operating a counter/timer circuit involves determining a match condition by comparing a count value of the counter/timer circuit with a value stored in a match register of the counter/timer circuit and delaying an assertion of the match condition based on a value programmed in a match companion register of the counter/timer circuit. The match companion register is associated with the match register. Other embodiments are also described.

Abstract: Methods for fabricating a device structure, as well as device structures and design structures for a bipolar junction transistor. The device structure includes a collector region in a substrate, a plurality of isolation structures extending into the substrate and comprised of an electrical insulator, and an isolation region in the substrate. The isolation structures have a length and are arranged with a pitch transverse to the length such that each adjacent pair of the isolation structures is separated by a respective section of the substrate. The isolation region is laterally separated from at least one of the isolation structures by a first portion of the collector region. The isolation region laterally separates a second portion of the collector region from the first portion of the collector region. The device structure further includes an intrinsic base on the second portion of the collector region and an emitter on the intrinsic base.

Abstract: A system may include a database configured to store information including characteristics of a plurality of components. The system may further include a server in communication with the database and configured to: receive design parameters indicative of a plurality of power supply loads to be powered; determine a plurality of power supply architectures that may be used to provide power supply solutions satisfying the plurality of loads, each power supply architecture including at least one position requiring a component configured to satisfy a load requirement; for each one of at least a subset of the plurality of power supply architectures, determine, based on the characteristics of the plurality of components, at least one component configured to satisfy the corresponding load requirement for each position of the one of the power supply architectures; and generate at least one power supply design in accordance with the power supply architectures and the determined components.

Abstract: There is provided a data processing apparatus (1) including a logic circuit (10) that is reconfigurable in each cycle and a library (2) that stores hardware control information (20). The hardware control information (20) includes a plurality of pieces of cycle-based mapping information (21) for individually mapping a plurality of cycle-based circuits, which each realize a function in each cycle for executing an application, onto the logic circuit (10) and configuration selection information (22) for selecting at least one of the plurality of pieces of cycle-based mapping information according to an execution state of the application. The data processing apparatus (1) includes a control unit (11) that reconfigures at least part of the logic region (10) using at least one of the plurality of pieces of cycle-based mapping information (21) according to a request in each cycle based on the configuration selection information (22).

Abstract: In one embodiment of the invention, a method of designing an integrated circuit including a subtraction arithmetic function is provided. The method includes generating a netlist of an area-efficient subtractor to subtract a first input vector from a second input vector. A netlist of a plurality of reduced full subtractor cells is generated with each including an exclusive-NOR gate evaluating a shared Boolean expression to generate a sum bit output and a carry bit output. The netlist of the reduced full subtractor cell is replicated for all bits of the area-efficient subtractor but for the least significant bit. One of a plurality of netlists of subtractor cells is selected for the least significant bit of the area-efficient subtractor in response to a flex bit.

Abstract: An apparatus having two or more parallel carry chain structures, each of the carry chain structures comprising a series of logical structures, where at least one of the logical structures within each of the carry chain structures has an associated input node, output node and carry node. The input node corresponds to a function input term, the output node corresponds to an output term of the function and the carry node corresponds to a carry value to a following logical structure in the series of logical structures.

Abstract: In one aspect of the present invention, a memory apparatus comprises a plurality of resettable memory cells, a plurality of memory units, and a reset information propagation logic coupled to the resettable memory cells and the memory units. The reset information propagation logic designed to write reset information into a portion of the memory units in response to one of the resettable memory cells having a reset value when one of the memory units is written into.

Abstract: Disclosed are improved methods, systems, and computer program products for implementing flexible models to perform efficient prototyping of electronic designs, which allows for very efficient analysis of the electronic designs. The flexible models allow many of the existing tools for designing electronics to perform more efficiently.

Abstract: A method of simplifying a combinational circuit establishes an initial combinational circuit operable to calculate a set of target signals. A quantity of multiplication operations performed in a first portion of the initial combinational circuit is reduced to create a first, simplified combinational circuit. The first portion includes only multiplication operations and addition operations. A quantity of addition operations performed in a second portion of the first, simplified combinational circuit is reduced to create a second, simplified combinational circuit. The second portion includes only addition operations. Also, the second, simplified combinational circuit is operable to calculate the target signals using fewer operations than the initial combinational circuit.

Abstract: An integrated circuit (IC) comprising a shielding mesh in at least one layer of the IC, the shielding mesh having a first plurality of lines which are designed to provide a first reference voltage and having a second plurality of lines which are designed to provide a second reference voltage and wherein the shielding mesh comprises a window in which signal lines are routed with less shielding than signal lines which are routed in the shielding mesh. The IC further comprising power supply lines in at least a first layer of the IC, the first layer being different than the at least one layer which contains the shielding mesh, the power supply lines being coupled to the shielding mesh and being larger in width than the first plurality of lines and the second plurality of lines.

Abstract: Described is a communication system in a first integrated circuit (IC) communicates with a second IC via single-ended communication channels. A bidirectional reference channel extends between the first and second ICs and is terminated on both ends. The termination impedances at each end of the reference channel support different modes for communicating signals in different directions. The termination impedances for the reference channel can be optimized for each signaling direction.

Abstract: An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase.

Abstract: Some aspects of the present disclosure provide for a system and method to discover which parts of a design a formal test suite can detect faults in, and thus how much of a design structure is covered by a property set. A mutatable RTL design is defined which allows for modification of a part of an RTL design from its intended behavior to a non-intended behavior, thus introducing unwanted effects. The mutatable RTL design can then be synthesized to produce a functional representation of the design. The property set can be re-run on the synthesized design to see whether the functional representation of the design is sensitive to the unwanted effect and thus whether formal verification can detect the modification.

Abstract: A clock system includes a local clock buffer adapted to receive a variable global clock signal. The local clock buffer produces a first local clock signal from the variable global clock signal. The clock system includes a pulse width logic control circuit in operable communication with the local clock buffer. The pulse width logic control circuit may be adapted to limit the first local clock signal pulse width to be less than the variable global clock signal pulse width during a slow mode. The pulse width logic control circuit may be adapted to expand the first local clock signal pulse width to be greater than the variable global clock signal pulse width during a fast mode. The limited and expanded first local clock signals may signal a local evaluation circuit to address a memory line.

Abstract: A power circuit analysis apparatus includes a segmentation unit that segments an analysis target region in a power circuit included in an analysis target circuit into a plurality of segmented regions, and an analysis unit that outputs an analysis result of the power circuit with respect to each of the plurality of segmented regions on a basis of a consumption current value in the segmented region and a number of via holes formed in each interlayer connecting power line wirings in upper and lower layers to each other in the segmented region.

Abstract: Apparatuses and processes for distributing signals in an integrated circuit are disclosed. An embodiment to use a custom layer together with a base layer on an integrated circuit for testing the integrated circuit includes having a structured network on the base layer. The custom layer connects the network to logic elements on the integrated circuit. The network may be evenly distributed across the base layer of the integrated circuit. Even distribution of the network may reduce skew of the test signals. Buffers are also placed along the structured network. The buffers may be placed to ensure a deterministic test signals distribution. Unused buffers in the base layer may be tied off to reduce current leakage.

Abstract: Disclosed are a method and an apparatus of designing a semiconductor chip. The disclosed method includes the steps of: storing a plurality of EMS (Electro Magnetic Susceptibility) semiconductor IPs (Intellectual Property) and a plurality of EMI (Electro Magnetic Interference) semiconductor IPs; selecting a proper semiconductor IP from among the plurality of EMS shielding semiconductor IPs in a case of an input pin, and selecting a proper semiconductor IP from among the plurality of EMI shielding semiconductor IPs in a case of an output pin; and designing the semiconductor chip by disposing the selected semiconductor IP.

Abstract: A disclosed method includes: accepting designation of a condition of grouping plural signal lines to be wired from a user; and switching and carrying out a grouping of the plural signal lines into plural groups based on the designated condition and a disposition pattern of start terminals and end terminals of the plural signal lines. The condition may be designated from a first requirement, a second requirement and a third requirement that includes the first requirement and the second requirement and in which a priority is set to the first requirement or the second requirement.

Abstract: A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. The child processes then notify the parent process of those objects that qualify as candidate objects, so that the parent process only has to perform the transform on the candidate objects, thereby relieving the parent process from the overhead associated with performing the transform on non-candidate objects for which the transform has been determined by the child processes as not being successful.

Abstract: Contour-related information for geometric elements in layout design data is obtained. Relevant portions of the contour-related information are provided to a canonical hash function, from which a canonical signature for the layout design data is generated.

Abstract: A computer-aided design method for developing, simulating, and testing a read-channel architecture to be implemented in a VLSI circuit. The method uses codeword/waveform classification to accelerate simulation of the read-channel's error-rate characteristics, with said classification being generated using a first read-channel simulator having a limited functionality. A second read-channel simulator having an extended functionality is then run only for some of the codewords, with the latter having been identified based on said codeword/waveform classification. The acceleration is achieved, at least in part, because the relatively highly time-consuming processing steps implemented in the second read-channel simulator are applied to fewer codewords than otherwise required by conventional simulation methods.

Abstract: An editing system includes a database server apparatus having product specification management data stored therein; and a terminal apparatus including: a display part displaying a function tree and an IO table, the function tree hierarchically indicating elements along with attributes of each of the elements based on the product specification management data and having a product name as a root of the function tree, and the IO table indicating connection data between each pin of the elements based on the product specification management data, an accepting part accepting an operation to connect one element to another element, an operation to display connection data between the elements, and an operation to edit each item of the connection data of the IO table, and an updating part updating the connection data of the product specification management data in accordance with the operations accepted by the operation accepting part.

Abstract: A system and several methods for inferring higher level descriptions of circuit connectivity from register transfer level (RTL) netlists in order to provide more understandable and manageable design descriptions for complex System-on-Chip (SOC) designs, is provided. In particular, interface matching based on connectivity propagation is automatically performed whereby port names and properties on instances of functional elements and blocks are propagated to top level design ports as well as other instances of functional elements and blocks to create a more robust description of connectivity according to the RTL netlist, and to automatically form signal groupings that comprise a higher-level abstracted description. Also, a facility is included to allow user-guided grouping of instantiated interfaces with respect to actual signal names and properties in an RTL-level design.

Abstract: A system, method and program product for modeling load effects of a load CCC (channel connected component) in a transistor network. A system is disclosed that includes an analysis system that determines allowable logical state and transition functions for nets in a load CCC for a transition or state of a driving CCC for which a load condition is being determined; a trace system that traverses paths in the load CCC from a set of input terminals; and an element replacement system that replaces circuit elements in the load CCC to create a modeled CCC, wherein a circuit element replacement is based on a type of circuit element encountered along a trace, and state and transition functions of nets connected to an encountered circuit element.

Abstract: Device structures with a reduced junction area in an SOI process, methods of making the device structures, and design structures for a lateral diode. The device structure includes one or more dielectric regions, such as STI regions, positioned in the device region and intersecting the p-n junction between an anode and cathode. The dielectric regions, which may be formed using shallow trench isolation techniques, function to reduce the width of a p-n junction with respect to the width area of the cathode at a location spaced laterally from the p-n junction and the anode. The width difference and presence of the dielectric regions creates an asymmetrical diode structure. The volume of the device region occupied by the dielectric regions is minimized to preserve the volume of the cathode and anode.

Abstract: Systems and methods for validating a circuit design are described. The circuit validation includes determining a subset of checks to apply to a portion of the overall circuit based on the pin type composition of the circuit portion.

Abstract: Within a system comprising a processor and a memory, a method of automatically documenting a circuit design can include determining an assignment of a user comment entity (UCE) of a high level modeling system (HLMS) circuit design to an HLMS block of the HLMS circuit design, translating each HLMS block of the HLMS circuit design into a hardware description language (HDL) representation of the HLMS block, and for each HLMS block assigned a UCE, inserting within the HDL representation, by the processor, content of the UCE that is assigned to the HLMS block in the form of a comment. The HDL representations can be stored within the memory.

Abstract: A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.

Abstract: Methods and apparatuses are described for reducing or eliminating X-pessimism in gate-level simulation and/or formal verification. A system can identify a set of reconvergent inputs of a combinational block in a gate-level design. Next, the system can determine whether or not the combinational block is expected to exhibit X-pessimism during gate-level simulation. If the combinational block is expected to exhibit X-pessimism during gate-level simulation, the system can modify the gate-level design to reduce X-pessimism during gate-level simulation. In some embodiments, the system can build a model for the gate-level design by using unique free input variables to represent sources of indeterminate values. The system can then use the model to perform formal verification.

Abstract: Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.

Abstract: A method of configuring a programmable integrated circuit device with a user logic design includes accepting a first user input defining the user logic design, accepting a second user input defining multithreading characteristics of at least a portion the user logic design, determining a configuration of the programmable integrated circuit device having the user logic design, multithreading the at least a portion of the configuration based on the second user input, and retiming the multithreaded configuration.

Abstract: A method for designing an integrated circuit is described. The method comprises converting behavioral descriptions of the integrated circuit to register transfer level (RTL) descriptions. The method comprises at least one of the behavioral descriptions including frame synthesis with an input frame and a corresponding output frame. In one embodiment, the method further comprises providing at least two solutions for performing partial and complete operations for simulations as hardware component combinations, associating each solution with a cost, and selecting the solution with the lowest cost as the hardware component combination for a final design of the integrated circuit.

Abstract: Aspects of the invention provide for improving a success rate of an engineering design change (ECO) for an integrated circuit. In one embodiment, aspects of the invention include a method for improving a success rate of an engineering design change (ECO) for an integrated circuit, including: identifying a plurality of spare latches within the integrated circuit; determining an input driver for each of the spare latches; and replacing each input driver with a programmable gate array, such that the programmable gate array is programmed to a functionality of the input driver.

Abstract: Searching and/or replacing graphical objects of a design using a computer system. In one aspect of the inventions, a method includes searching a graphical design for all matching instances of graphical objects that match a search pattern. A graphical replacement pattern is received and caused to be displayed based on user input, and the matching instances in the graphical design are replaced with the graphical replacement pattern. At least one result of the replacement of the matching instances is caused to be displayed on a display device.

Abstract: Searching for graphical objects of a design using a computer system. In one aspect of the inventions, a method includes defining a graphical search pattern based on input received from a user in a graphical interface displayed on a display device, where the search pattern is a graphical object and is defined with a plurality of types of characteristics. The graphical design is searched for all matching instances of graphical objects in the design that match the search pattern and match the characteristics specified by the search pattern. At least one of the matching instances is caused to be displayed on the display device as a result of the searching.

Abstract: Methods and apparatuses to automatically synthesize circuits. In one aspect of an embodiment, a method implemented on a data processing system for circuit synthesis comprises determining a Read Only Memory (ROM) of a design of a circuit, the ROM having predefined data when the circuit is initialized, and automatically generating an initialization circuit and a Random Access Memory (RAM) to implement the ROM, the initialization circuit to load the predefined data into the RAM when the circuit is initialized.

Abstract: The current application is directed to methods and systems which produce a design for an optimal approximation of a target single-qubit quantum operation comprising a representation of a quantum-circuit generated from a discrete, quantum-gate basis. The discrete quantum-gate basis comprises standard, implementable quantum gates. The methods and systems employ a database of canonical-form quantum circuits, an efficiently organized canonical-form quantum-circuit, and efficient searching to identify a minimum-cost design for decomposing and approximating an input target quantum operation.

Abstract: A universal memory I/O generating apparatus includes a defining module, a retrieving module, a generating module, and a layout module. The defining module defines a mapping table according to a pin configuration of a plurality of I/Os. The mapping table includes corresponding relationships between the plurality of IOs and a plurality of memory functions. The retrieving module retrieves control information corresponding to the mapping table from candidate information, which is associated with the corresponding relationships between the plurality of I/Os and the plurality of memory functions. The generating module generates a hardware description language (HDL) file according to the control information. The layout module programs the plurality of I/Os according to the HDL file, so that each of the I/Os can correspond to its corresponding memory function.

Abstract: In one embodiment of the invention, a method of statically analyzing an integrated circuit with process and environment variations is provided. The method includes characterizing each circuit cell of a cell library for a sensitivity to process parameter variations within a predetermined range; creating a timing graph corresponding to a netlist representing an integrated circuit design; along nodes of the timing graph, computing delay values including sensitivities to process variations; for each selected output node of the netlist, propagating a full timing value function with the sensitivities to the selected output nodes; and generating a parameterized timing report including the sensitivities to the process variations.

Abstract: A method of circuit design performed in which a description of a multi-clock-domain circuit is analyzed to locate clock domain crossings. A processor automatically identifies, for at least one of the located clock domain crossings, one or more elements of a synchronization circuit of the clock domain crossing, which require constraining. The processor then generates a constraint for implementation of the identified one or more elements in a design of the circuit.

Abstract: The memory building blocks can be used in conjunction with ASIC automatic design tools to generate a memory macro (e.g., a memory array) using a known ASIC design flow including, for example, register transfer level (RTL), synthesis, automatic place and route (APR) and timing analysis.

Abstract: A method includes extracting a first netlist from a first layout of a semiconductor circuit and estimating layout-dependent effect data based on the first netlist. A first simulation of the semiconductor circuit is performed based on the first netlist using an electronic design automation tool, and a second simulation of the semiconductor circuit is performed based on a circuit schematic using the electronic design automation tool. A weight and a sensitivity of the at least one layout-dependent effect are calculated, and the first layout of the semiconductor circuit is adjusted based on the weight and the sensitivity to provide a second layout of the semiconductor circuit. The second layout is stored in a non-transient storage medium.

Abstract: An automated method for designing an integrated circuit layout using a computer based upon an electronic circuit description and based upon cells which are selected from a cell library, each of the cells having an associated area, comprising the steps of: (a) placing each of the cells in the integrated circuit layout so that the cells can be coupled together by wires to form a circuit path having an associated predetermined delay constraint wherein the cells are coupled together based upon the electronic circuit description input to the computer; (b) connecting the cells together with the wires to form the circuit path; and (c) adjusting an area of at least one of the cells to satisfy the associated predetermined delay constraint of the circuit path.

Abstract: A method of determining a design framework is implemented by an algorithm analyzer. The method includes configuring the algorithm analyzer to perform intrinsic complexity analysis of an algorithm for a predetermined application to obtain a set of parameters representing intrinsic characteristics of the algorithm. The method also includes configuring the algorithm analyzer to establish candidate design frameworks based on the parameters. Each candidate design framework includes a set of design constraints corresponding to the algorithm and which are used when designing a hardware and/or software configuration for implementing the predetermined application. The method also includes configuring the algorithm analyzer to analyze the suitability of the set of design constraints of each candidate design framework based on given specification restrictions of the predetermined application to determine which candidate design framework(s) is suited for the predetermined application.

Abstract: A system, method and computer program product are provided for reducing a deactivation function utilizing an optimal reduction. In use, a deactivation function is identified. Additionally, reductions for the deactivation function are calculated. Further, an optimal reduction of the calculated reductions is determined. Moreover, the deactivation function is reduced, utilizing the optimal reduction.

Abstract: Methods of fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. A first portion of the intrinsic base layer is masked while a second portion of an intrinsic base layer is etched. As a consequence of the masking, the second portion of the intrinsic base layer is thinner than the first portion of the intrinsic base layer. An emitter and an extrinsic base layer are formed in respective contacting relationships with the first and second portions of the intrinsic base layer.

Abstract: Methods are used to enrich a cell library in such a way to provide a nearly continuous choice of cells to implement a circuit design. The emphasis of the design method is on automatic determination of the needed cell sizes and variants. The method exploits different variants on drive strengths, P/N ratios, topology variants, internal buffering, and so forth. The method allows enriching libraries to become more suitable for efficient timing closure. The method also offers means to adapt the preexisting cells to fit the final distribution, minimizing the number of new cells to be created.