Logic Design Processing Patents (Class 716/101)
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Patent number: 8407637Abstract: A method of analyzing electrical stability of an active circuit splits a frequency response of an electrical or electronic circuit according to sub-bands (134, 136, 138) and in each sub-band (134, 136, 138) implements a step of determining an identification transfer function adapted for a stability analysis. The step of determining the transfer function is automatic and executed in the form of an identification loop, parameterized according to a current order of transfer function, and stopped when the norm of a phase error function for the error between the phase (222, 224, 226) of the current identified transfer function and that of the frequency response has exceeded a predetermined phase error threshold value.Type: GrantFiled: October 27, 2009Date of Patent: March 26, 2013Assignee: Centre National d'Etudes SpatialesInventors: Alain Mallet, Aitziber Anakabe Iturriaga, Geoffroy Soubercaze-Pun, Juan Maria Collantes Metola
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Patent number: 8407648Abstract: A computer-implemented method for component arrangement in a PCB layout device is provided. The device includes wiring diagrams. First, generates a PCB encapsulation diagram corresponding to the selected wiring diagram. Then, obtains the coordinates of each electronic component in the selected wiring diagram. Next, generates a prompt to prompt the user to select a reference point in the PCB encapsulation diagram. Then, obtains the coordinates of the reference point. Next, determines an abscissa difference and an ordinate difference between one component in the wiring diagram and the reference point. Then, determines the coordinates of each encapsulated component in the PCB encapsulation diagram according to the abscissa difference, the ordinate difference, and the coordinates of each electronic component in the wiring diagram. And last, moves each encapsulated component to the determined corresponding coordinates of each encapsulated component in the PCB encapsulation diagram.Type: GrantFiled: April 28, 2011Date of Patent: March 26, 2013Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventor: Xiao-Cheng Sheng
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Patent number: 8407659Abstract: In a method of designing a printed circuit board, a package capacitance, a package inductance, and a chip capacitance of an actual memory device are calculated. A signal line capacitance and a signal line inductance per unit length of a signal line are calculated based on characteristics of the printed circuit board. A length of the signal line for each pin is determined based on the package capacitance and the signal line capacitance.Type: GrantFiled: July 2, 2010Date of Patent: March 26, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hoon Jeong, Chang-Woo Ko, Ki-Jae Song, Hun-Kyo Seo
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Patent number: 8402407Abstract: A semiconductor integrated circuit pattern verification method includes executing simulation to obtain a simulation pattern to be formed on a substrate on the basis of a semiconductor integrated circuit design pattern, comparing the simulation pattern and the design pattern that is required on the substrate to detect a first difference value, extracting error candidates at which the first difference value is not less than a first predetermined value, comparing pattern shapes at the error candidates to detect a second difference value, combining, into one group, patterns whose second difference values are not more than a second predetermined value, and extracting a predetermined number of patterns from each group and verifying error candidates of the extracted patterns.Type: GrantFiled: January 20, 2011Date of Patent: March 19, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Shigeki Nojima
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Patent number: 8402419Abstract: Power consumption estimation is performed at the system level in a design process, thus allowing early evaluation of feasibility and other considerations relating to logic/DSP design and hardware implementation of a proposed electronic design. Evaluation of the system level power consumption estimate(s) permits adjustment of a system level representation of the proposed electronic design, prior to investment of substantial resources in the electronic design. Other estimates, including other power consumption estimates, may be performed to adjust the proposed electronic design as well. Such estimates may be made in response to gate level power consumption estimates and/or hardware level power consumption estimates.Type: GrantFiled: January 19, 2011Date of Patent: March 19, 2013Assignee: Altera CorporationInventors: Jordan Plofsky, Philippe Molson, Francois Pequillat
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Patent number: 8400679Abstract: A system and method for routing and processing jobs in a production environment considers the setup characteristics of each print job. Each set of jobs may be classified as a first job processing speed set, a second job processing speed set, or another job processing speed set based on the corresponding setup characteristics. First job processing speed sets are routed to a first group of job processing resources, while second job processing speed sets are routed to a second group of job processing speed resources. Each resource group may include an autonomous cell.Type: GrantFiled: September 19, 2011Date of Patent: March 19, 2013Assignee: Xerox CorporationInventor: Sudhendu Rai
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Patent number: 8402408Abstract: An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.Type: GrantFiled: December 28, 2011Date of Patent: March 19, 2013Assignee: Altera CorporationInventors: Babette van Antwerpen, Michael D. Hutton, Gregg Baeckler, Richard Yuan
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Patent number: 8402183Abstract: A system and method for coordinating control setting with respect to an automated input/output (I/O) processor. A state machine having a transition algorithm can be configured in association with a storage controller in order to permit multiple entities to safely transmit an I/O request to an I/O device. Specific combinations of control bits associated with a fast path engine can be determined by identifying different modes with respect to the behavior of the fast path engine. Each mode can be assigned as a state with respect to the state machine. An I/O path exception and error condition that can cause transitions between the states can be determined and the transitions can be assigned from one state to another state. A generic logic template can then be configured to govern the transitions with respect to the state machine. The logic can be executed when an event occurs in order to trigger multiple state transition and/or modifications with respect to the hardware control bits of the fast path engine.Type: GrantFiled: October 6, 2010Date of Patent: March 19, 2013Assignee: LSI CorporationInventors: Nick Pelis, Larry Rawe
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Publication number: 20130063109Abstract: A power regulation scheme includes a first voltage regulation portion having a first voltage regulator, a second voltage regulator, and a switching system. The first voltage regulation portion is connected in parallel with a second voltage regulation portion. The second voltage regulation portion regulates an input voltage if an open condition occurs within the first voltage regulation portion. The switching system forces the second voltage regulator to regulate the input voltage if a short condition occurs within the first voltage regulator.Type: ApplicationFiled: May 31, 2012Publication date: March 14, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Patrick K. Egan, Jordan R. Keuseman, Michael L. Miller
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Patent number: 8397183Abstract: A method, system and computer program product are disclosed for creating the appropriate block level shapes to manufacture asymmetric field effect transistors (FETs). In one embodiment, the method comprises obtaining an integrated circuit design having an active region level (RX) and a gate region level (PC), each of the RX and PC levels having a multitude of shapes representing semiconductor regions; and defining a new level SD having a multitude of SD level shapes from the RX and the PC level shapes. This method further comprises identifying which ones of the new shapes are source regions and which ones are drain regions; determining which ones of the source regions are pointing up and which ones are pointing down; and copying the shapes of source regions that are pointing up and the shapes of the source regions that are pointing down onto additional, defined levels.Type: GrantFiled: February 3, 2010Date of Patent: March 12, 2013Assignee: International Business Machines CorporationInventors: Leland Chang, Jeffrey W. Sleight
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Patent number: 8397202Abstract: Systems and methods for performing a signature analysis on sorted data to identify one or more outliers in a dataset. The method includes determining, with a control platform, a percentile range of a sorted dataset, wherein the percentile range includes a first plurality of qualified vector patterns; determining a signature of the percentile range; determining a signature of a second plurality of vector patterns, wherein the second plurality of vector patterns includes a first test vector pattern that is outside of the percentile range; and comparing the signature of the percentile range to the signature of the second plurality of vector patterns. The method further includes, based at least in part on the comparing, identifying the first vector pattern as one of (i) a qualifying vector pattern or (ii) an outlier.Type: GrantFiled: October 17, 2011Date of Patent: March 12, 2013Assignee: Marvell International Ltd.Inventor: Bede C. Nnaji
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Publication number: 20130057991Abstract: Device structures and design structures for a silicon controlled rectifier, as well as methods for fabricating a silicon controlled rectifier. The device structure includes first and second layers of different materials disposed on a top surface of a device region containing first and second p-n junctions of the silicon controlled rectifier. The first layer is laterally positioned on the top surface in vertical alignment with the first p-n junction. The second layer is laterally positioned on the top surface of the device region in vertical alignment with the second p-n junction. The material comprising the second layer has a higher electrical resistivity than the material comprising the first layer.Type: ApplicationFiled: September 7, 2011Publication date: March 7, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kiran V. Chatty, Robert J. Gauthier, JR., Junjun Li, Alain Loiseau
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Patent number: 8392859Abstract: A method and system for debugging using replicated logic and trigger logic is described. A representation of a circuit is compiled. One or more signals are selected for triggering and trigger logic is inserted into the circuit. A portion of the circuit is selected for replication. The selected portion of the circuit is replicated and delay logic is inserted to delay the inputs into the replicated portion of the circuit. The representation of the circuit is recompiled and programmed into a hardware device. A debugger may then be invoked. One or more of the triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of steps that led to the trigger condition may then be recorded.Type: GrantFiled: January 14, 2010Date of Patent: March 5, 2013Assignee: Synopsys, Inc.Inventors: Chun Kit Ng, Kenneth S. McElvain
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Patent number: 8386979Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.Type: GrantFiled: January 22, 2009Date of Patent: February 26, 2013Assignee: Synopsys, Inc.Inventors: Kenneth S. McElvain, William Halpin
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Patent number: 8386988Abstract: A semiconductor integrated circuit includes a first circuit part that is designed under a first corner condition with respect to a process variation, a second circuit part that is designed under a second corner condition narrower than the first condition, and a control part that changes an operating voltage supplied to the first circuit part and the second circuit part according to a delay amount of the first circuit part, and starts the second circuit part when a delay characteristic caused by a change in the operating voltage conforms to a delay characteristic under the second corner condition.Type: GrantFiled: January 12, 2011Date of Patent: February 26, 2013Assignee: Renesas Electronics CorporationInventor: Masahiro Nomura
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Patent number: 8381163Abstract: A power-gated retention flop circuit is disclosed. In one embodiment, a retention flop includes a first latch coupled to a first global voltage node and a virtual voltage node and configured to receive a data input signal, and a second latch coupled to receive the data input signal from the first latch, wherein the second latch is coupled to the first global voltage node and a second global voltage node. The second latch is configured to provide a data output signal based on the data input signal. A power-gating circuit is coupled between the virtual voltage node and the second global voltage node, wherein the power-gating circuit is configured to, when active, couple the virtual voltage node to the second global voltage node. Thus, the first latch may be powered down while the second latch remains powered on.Type: GrantFiled: November 22, 2010Date of Patent: February 19, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Jeremy P. Schreiber, Aaron Grenat
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Patent number: 8381145Abstract: An apparatus for analyzing a fault behavior, includes a satisfiability modulo theories (SMT) conversion block for performing SMT conversion with respect to a protocol state machine diagram and a sequence diagram of a software design model. Further, the apparatus for analyzing the fault behavior includes an SMT processing block for performing a SMT processing using respective logic formulas corresponding to the protocol state machine diagram and the sequence diagram and outputted from the SMT conversion block, and determining whether the result of the SMT processing is satisfied to output an occurrable behavior scenario when the result of the SMT processing is satisfied.Type: GrantFiled: October 26, 2010Date of Patent: February 19, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: Sachoun Park, Jung Hee Lee
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Patent number: 8381142Abstract: A method for designing a system on a target device is described. In one embodiment of the method, a plurality of registers is replaced with at least one register and a timing exception. In one embodiment, the registers in the plurality of registers are in series or substantially in series. In one embodiment, the timing exception is a multi-cycle exception. In one embodiment, the method also includes identifying a critical combinational logic path that is followed or preceded by the plurality of registers. Further, in one aspect, the timing exception is removed and registers are inserted into the critical combinational logic path to account for the removed timing exception. In one embodiment, a network flow algorithm is performed to determine the locations for inserting registers.Type: GrantFiled: October 9, 2007Date of Patent: February 19, 2013Assignee: Altera CorporationInventor: Michael D. Hutton
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Patent number: 8375338Abstract: Methods and systems estimate a rate of corruption of storage bits in a logic circuit. One or more processors execute instructions that cause the processors to perform the operations that follow. A description is input describing an environment of the logic circuit, and the description of the environment includes a position of the logic circuit. An atomic particle flux density at the logic circuit is estimated as a function of the description of the environment. A specification is input that specifies the storage bits in the logic circuit. The rate of corruption of the storage bits is determined as a function of the atomic particle flux density and a quantification of the storage bits in the logic circuit.Type: GrantFiled: December 21, 2010Date of Patent: February 12, 2013Assignee: Xilinx, Inc.Inventors: Jameel Hussein, Austin H. Lesea, Kenneth D. Chapman, Ching Y. Hu
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Patent number: 8370781Abstract: Design and verification support related to integrated circuits that includes acquiring a first use case diagram representing a function of an object subject to design and verification and an activity diagram representing a processing procedure of the object; analyzing a structure of the activity diagram acquired at the acquiring step; converting the activity diagram to a second use case diagram representing a function of the object, based on the structure analyzed at the analyzing; verifying uniformity of the first use case diagram and the second use case diagram; and outputting a verification result obtained at the verifying uniformity.Type: GrantFiled: August 30, 2007Date of Patent: February 5, 2013Assignee: Fujitsu LimitedInventors: Ryosuke Oishi, Akio Matsuda
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Patent number: 8370784Abstract: Systems and methods are disclosed to automatically design a custom integrated circuit based on algorithmic process or code as input and using highly automated tools that requires virtually no human involvement is disclosed.Type: GrantFiled: July 13, 2010Date of Patent: February 5, 2013Assignee: Algotochip CorporationInventors: Satish Padmanabhan, Plus Ng, Anand Pandurangan, Suresh Kadiyala, Ananth Durbha, Tak Shigihara
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Patent number: 8370775Abstract: A method for determining a predicted soft error rate (SER) for an integrated circuit device design includes calculating the SER based on a predicted amount of charge imparted by a one or more particles to the integrated circuit device based on the design. The SER is further based on a predicted sensitivity level of a region of the integrated circuit device to the charge imparted by the one or more particles, and can also be based on the energy spectrum of the particles.Type: GrantFiled: February 2, 2010Date of Patent: February 5, 2013Assignee: Advanced Micro Devices, Inc.Inventor: Cristian Constantinescu
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Patent number: 8365133Abstract: A testing apparatus includes a vector memory unit storing original test vector data in which an input signal to be inputted to a circuit subjected to inspection is described, a vector generator generating generated test vector data from the original test vector data, an output part outputting test vector data to be inputted to the inspected circuit, a fault occurrence rate memory unit storing a fault occurrence rate of the input signal, a random number generator generating random number data, and a comparison part comparing the fault occurrence rate of the input signal with the random number data. The vector output part outputs the generated test vector data when the random number data is smaller than the fault occurrence rate of the input signal, and outputs the original test vector data when the random number data is larger than the fault occurrence rate of the input signal.Type: GrantFiled: February 23, 2010Date of Patent: January 29, 2013Assignee: Sony CorporationInventor: Shinichiro Chikada
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Patent number: 8365119Abstract: Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.Type: GrantFiled: April 15, 2010Date of Patent: January 29, 2013Assignee: Rambus Inc.Inventor: Stephen G. Tell
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Patent number: 8365110Abstract: A computer executable tool facilitates integrated circuit design and debugging by working directly at the Register Transfer Level, where most design activities take place. The tool determines when an integrated circuit design produces incorrect output responses for a given set of input vectors. The tool accesses the expected responses and returns the signal paths in the integrated circuit that are responsible for the errors along with suggested changes for fixing the errors. The tool may operate at the RTL, which is above the gate-level abstraction which means that the design errors will be much more readily understood to the designer, and may improve scalability and efficiency.Type: GrantFiled: May 27, 2008Date of Patent: January 29, 2013Assignee: The Regents of the University of MichiganInventors: Kai-Hui Chang, Ilya Wagner, Igor Markov, Valeria Bertacco
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Patent number: 8365109Abstract: In one embodiment, a method of generating a circuit design is provided. For each data terminal connecting a plurality of components in a circuit design, a respective list of dimensions of data used by the data terminal are determined. A plurality of exchange orderings are generated that each indicate an order in which dimensions are exchanged between the lists. For each exchange ordering, dimensions are exchanged between the lists according to the exchange ordering to produce a set of supplemented lists of dimensions. A set of buffers for buffering data between the data terminals are determined based on the supplemented lists of dimensions. Memory requirements are determined for each of the set of buffers. The circuit design is modified to include the one of the determined sets of buffers having a lowest memory requirement.Type: GrantFiled: June 27, 2012Date of Patent: January 29, 2013Assignee: Xilinx, Inc.Inventors: Thomas P. Perry, Richard L. Walke
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Patent number: 8359557Abstract: A method is provided for generation of a circuit design. A plurality of components, including at least a processor and a peripheral device, is instantiated in a circuit design. One or more parameterizable data bus interface blocks are automatically selected based on the master-slave relationships, requirements, and capabilities of the components. The one or more parameterizable data bus interface blocks are instantiated in the circuit design. In response to user input, values are assigned to one or more parameters of the processor. The plurality of components and data bus interface blocks are automatically parameterized by determining appropriate parameter values according to the parameters of the processor and capabilities and requirements of the components and data bus interface blocks.Type: GrantFiled: May 3, 2011Date of Patent: January 22, 2013Assignee: Xilinx, Inc.Inventors: Xi Chen, Jibin Han, Paulo L. Dutra, Thien Than, Biping Wu
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Publication number: 20130019213Abstract: Disclosed is a hardware accelerator for development engineering processes for a programmable logic device, such as for an FPGA.Type: ApplicationFiled: March 14, 2012Publication date: January 17, 2013Applicant: TicTran CorpInventors: Edward F. Panofsky, Richard A. Karp
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Publication number: 20130019214Abstract: A worst-case temperature calculation unit 206 calculates, based on heat value information of each layer of a three-dimensional integrated circuit to be designed and stack structure information of the three-dimensional integrated circuit, a worst-case temperature of a layer during operation that is targeted for logic synthesis. A logic synthesis library selection unit 208 selects a library appropriate for the calculated worst-case temperature. A logic synthesis unit 209 performs logic synthesis on the targeted layer with use of the selected library.Type: ApplicationFiled: February 17, 2012Publication date: January 17, 2013Inventors: Takashi Morimoto, Takashi Hashimoto
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Publication number: 20130007676Abstract: The present invention provides in one aspect a method of defining a logic cell library composed of complex functions and simple functions, with some of the complex functions obtained from identifying logic function patterns. In another aspect the present invention provides a method of designing a representation of an integrated circuit that uses complex functions and simple functions, with the complex functions including a plurality of non-standard complex Boolean logic functions that are determined to collectively provide for logic pattern minimization.Type: ApplicationFiled: September 11, 2012Publication date: January 3, 2013Inventors: Dipti Motiani, Veerbhan Kheterpal, Lawrence T. Pileggi
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Patent number: 8347258Abstract: A package includes a die and at least one further die. The die has an interface configured to receive a transaction request from the further die via an interconnect and to transmit a response to the transaction request to said further die via the interconnect. The die also has mapping circuitry which is configured to allocate to the received transaction a local source identity information as source identity information, the local source identity information comprising one of a set of reusable local source identity information. This ensures the order of transactions tagged with a same original source identity and target and allows transactions tagged with different source identifiers to be processed out of order.Type: GrantFiled: February 16, 2011Date of Patent: January 1, 2013Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (R&D) Ltd.Inventors: Ignazio Antonino Urzi, Philippe D'Audigier, Olivier Sauvage, Stuart Ryan, Andrew Michael Jones
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Publication number: 20120326766Abstract: Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR.Type: ApplicationFiled: June 24, 2011Publication date: December 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Renata Camillo-Castillo, Erik M. Dahlstrom, Robert J. Gauthier, JR., Ephrem G. Gebreselasie, Richard A. Phelps, Yun Shi, Andreas D. Stricker
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Patent number: 8341564Abstract: A method and system are provided for optimizing migrated implementation of a system design. In certain applications, a source hierarchical structure system and a target hierarchical structure system are provided, the hierarchy is abstracted out, intrinsic parameters are encoded and compared between source hierarchical structure and target hierarchical structure to arrive at an optimized change order list for transforming/migrating the source hierarchical structure system to the target hierarchical structure system.Type: GrantFiled: October 21, 2010Date of Patent: December 25, 2012Assignee: Cadence Design Systems, Inc.Inventor: Jonathan R. Fales
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Patent number: 8336007Abstract: A verifiable duplex multiplier circuit is provided. In one mode, the circuitry of the duplex multiplier functions as an N-bit×N-bit multiplier. In another mode, the circuitry of the duplex multiplier operates as dual N/2-bit×N/2-bit multipliers. Because the same circuitry can be used to serve as both an N×N multiplier and as dual N/2×N/2 multipliers, integrated circuit resources are conserved. The duplex multiplier circuitry uses an architecture that can be automatically synthesized using a logic synthesis tool. Verification operations can be performed using logic-equivalency error checking tools. Exhaustive verification is possible using this approach, even when relatively large duplex multipliers (e.g., duplex multipliers with N values of 16 or more) are used.Type: GrantFiled: January 5, 2012Date of Patent: December 18, 2012Assignee: Altera CorporationInventor: Guy Dupenloup
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Patent number: 8332800Abstract: A method for identifying and removing redundant signal paths includes determining whether a given input to a logic circuit is coupled to both an input of a cone of logic of a data input of a clocked state element and a clock gate circuit that is coupled to disable a clock input to the clocked state element. The method may include removing the given input from the cone of logic such that the given input is no longer coupled to the input of the cone of logic responsive to determining that the given input is coupled to both the input of the cone of logic and the clock gate circuit. The method may include preserving the given input to the clock gate circuit such that the given input continues to be coupled to the clock gate circuit after being removed from the input of the cone of logic.Type: GrantFiled: June 3, 2011Date of Patent: December 11, 2012Assignee: Apple Inc.Inventor: Ben D. Jarrett
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Patent number: 8332785Abstract: In an analyzing apparatus, an input accepting unit accepts input information including an analysis condition of a circuit element (circuit) to be analyzed, an analysis-SPICE-file generating unit generates an analysis SPICE file based on the input information, and an analysis-SPICE-file executing unit executes the analysis SPICE file, thereby analyzing the characteristic of the circuit element.Type: GrantFiled: June 22, 2009Date of Patent: December 11, 2012Assignee: Fujitsu LimitedInventor: Takashi Ohba
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Patent number: 8332789Abstract: A method may include receiving an input from an optimization control that indicates a value along a scale, wherein the value is indicative of a design tradeoff between at least optimization for a first parameter of an electrical design and an optimization for a second parameter of the electrical design, wherein the value places an emphasis on the first parameter and an emphasis on the second parameter such that when the value on the scale is closer to the first parameter a larger emphasis is placed on the first parameter of the electrical design and when the value on the scale is closer to the second parameter a larger emphasis is placed on the second parameter of the electrical design. The method may further include choosing components for the electrical design based on the value indicated using the optimization control, the emphases affecting the components selected for the electrical design.Type: GrantFiled: May 10, 2011Date of Patent: December 11, 2012Assignee: National Semiconductor CorporationInventors: Jeffrey Robert Perry, Malcolm Humphrey, Mark Davidson, Dien Mac, Denislav D. Petkov
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Patent number: 8332794Abstract: A programmable transistor array circuit is disclosed comprising a semiconductor substrate; and a plurality of basic transistor units (BTUs) arranged in rows and columns of uniformly spaced cells, the BTUs further comprising PMOS transistor units (PTUs), NMOS transistor units (NTUs) and dummy transistor units (DTUs) each BTU having conductors arranged in a single direction running through the BTUs and the conductors being uniformly spaced with respect to each other. The arrangement of the BTUs is subject to restricted design rules. Logical transistor units (LTUs) are formed from the BTUs using first and second layers of metallization. Methods for producing integrated circuits are disclosed forming programmable transistor arrays and implementing customer specified system designs upon the programmable transistor arrays.Type: GrantFiled: October 23, 2009Date of Patent: December 11, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Oscar M. K. Law, Kuo H. Wu
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Publication number: 20120305984Abstract: An electrostatic discharge (ESD) protection circuit, methods of fabricating an ESD protection circuit, methods of providing ESD protection, and design structures for an ESD protection circuit. An NFET may be formed in a p-well and a PFET may be formed in an n-well. A butted p-n junction formed between the p-well and n-well results in an NPNP structure that forms an SCR integrated with the NFET and PFET. The NFET, PFET and SCR are configured to collectively protect a pad, such as a power pad, from ESD events. During normal operation, the NFET, PFET, and SCR are biased by an RC-trigger circuit so that the ESD protection circuit is in a high impedance state. During an ESD event while the chip is unpowered, the RC-trigger circuit outputs trigger signals that cause the SCR, NFET, and PFET to enter into conductive states and cooperatively to shunt ESD currents away from the protected pad.Type: ApplicationFiled: May 31, 2011Publication date: December 6, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John B. Campi, JR., Shunhua T. Chang, Kiran V. Chatty, Robert J. Gauthier, JR., Junjun Li, Rahul Mishra, Mujahid Muhammad
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Patent number: 8327309Abstract: A system on a chip comprises a plurality of circuit blocks, a programmable processor and a communication circuit. Design information includes connection data including an identification of the direct mutual connection and first and second circuit blocks coupled by the direct mutual connection. An additional register is added to the system on a chip coupled to the direct mutual connection. Verification programs are used includescomprising instructions for the processor to access registers in the second one of the circuit blocks, to use the connection data, or information derived therefrom to select the first one of the circuit blocks, and to issue the standardized call to the interface program of the selected further one of the circuit blocks.Type: GrantFiled: August 8, 2008Date of Patent: December 4, 2012Assignee: Synopsys, Inc.Inventors: Jan Stuyt, Bernard W. De Ruyter, Roelof P. De Jong, Pieter Struik, Joris H. J. Geurts
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Patent number: 8327302Abstract: A technique for performing an analysis of a logic design includes detecting an initial transient behavior in a logic design embodied in a netlist. A duration of the initial transient behavior is also determined. Reduction information on the logic design is gathered based on the initial transient behavior. The netlist is then modified based on the reduction information.Type: GrantFiled: October 16, 2009Date of Patent: December 4, 2012Assignee: International Business Machines CorporationInventors: Jason R. Baumgartner, Michael L. Case, Robert L. Kanzelman, Hari Mony
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Patent number: 8321823Abstract: Computer-implemented systems and methods that provide an efficient technique for performing a large class of permutations on data vectors of length 2n, n>1, implemented with streaming width 2k (where 1?k?n?1). The technique applies to any permutation Q on 2n datawords that can be specified as a linear transform, i.e., as an n×n bit matrix (a matrix containing only 1s and 0s) P on the bit level. The relationship between Q and P is as follows: If Q maps (dataword) i to (dataword) j, then the bit representation of j is the bit-matrix-vector product of P with the bit representation of i. Given such a permutation specified by the matrix P and given the streaming width (k), an architectural framework (or datapath) is calculated to implement the permutation.Type: GrantFiled: October 2, 2008Date of Patent: November 27, 2012Assignee: Carnegie Mellon UniversityInventors: Markus Pueschel, Peter A. Milder, James C. Hoe
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Patent number: 8321825Abstract: A method for synthesizing relative timing (RT) constraints on an integrated circuit design is disclosed. Initially, multiple trace status tables are received, each containing a trace error identified by a formal verification engine that was utilized to perform a RT verification on an integrated circuit design. An error causing signal is then recognized for each of the trace errors. For each of error causing signals, two associating signals are identified, and the two associating signals are then utilized to locate a common point of convergence (POC). The POC is further utilized to locate a common point of divergence (POD), and an RT constraint can be generated based on the identified POC and POD. All the generated RT constraints are applied to constrain the integrated circuit design such that the integrated circuit design is able to pass RT verifications in the future without any timing violations.Type: GrantFiled: May 22, 2012Date of Patent: November 27, 2012Assignee: University of UtahInventors: Kenneth S. Stevens, Yang Xu
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Patent number: 8321193Abstract: An integrated circuit including an I/O register, wherein based on the behavior level design data, I/O register access information is generated. Then, based on the I/O register access information and association of an SW address with an HW address, address map information is generated. The SW address being used when the processor device accesses the I/O register, and the HW address being used when the user logical circuit accesses the I/O register. Based on the behavior level design data and the address map information, behavior level design data is generated.Type: GrantFiled: June 15, 2009Date of Patent: November 27, 2012Assignee: Hitachi, Ltd.Inventor: Shuntaro Seno
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Patent number: 8316338Abstract: A method of simplifying a combinational circuit establishes an initial combinational circuit operable to calculate a set of target signals. A quantity of multiplication operations performed in a first portion of the initial combinational circuit is reduced to create a first, simplified combinational circuit. The first portion includes only multiplication operations and addition operations. A quantity of addition operations performed in a second portion of the first, simplified combinational circuit is reduced to create a second, simplified combinational circuit. The second portion includes only addition operations. Also, the second, simplified combinational circuit is operable to calculate the target signals using fewer operations than the initial combinational circuit.Type: GrantFiled: February 9, 2009Date of Patent: November 20, 2012Assignees: The United States of America, as Represented by the Secretary of Commerce, The National Institute of Standards & Technology, University of Southern DenmarkInventors: Rene Caupolican Peralta, Joan Boyar
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Patent number: 8312398Abstract: The present invention is directed towards designing integrated circuit and provides systems and methods for lithography-aware floorplanning. According to one embodiment of the invention, a method for circuit floorplanning is provided. The method comprises generating a floorplan through a floorplanner, performing a lithography-analysis within the floorplanner on at least a portion of the floorplan, and generating one or more violations that result from the lithography-analysis. Some embodiment, in addition to viewing a floorplan, further comprise of modifying the floorplan. Furthermore, some embodiments provide a method that further comprises fixing the violations that result from the lithography analysis.Type: GrantFiled: April 15, 2009Date of Patent: November 13, 2012Assignee: Cadence Design Systems, Inc.Inventors: Chayan Majumder, Pawan Fangaria
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Patent number: 8312400Abstract: A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard.Type: GrantFiled: June 10, 2011Date of Patent: November 13, 2012Assignee: Fujitsu LimitedInventors: Ryosuke Oishi, Akio Matsuda, Koichiro Takayama, Tsuneo Nakata
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Patent number: 8302043Abstract: A method and system for verifying a logic circuit design using dynamic clock gating is disclosed. The method comprises choosing at least one master seed to determine initial values as initialization for said logic circuit and/or stimuli data for at least one interface of said logic circuit, choosing at least two different dynamic clock gating configurations for every chosen master seed, executing a functional simulation with said logic circuit for every chosen dynamic clock gating configuration by using said determined initialization and/or stimuli data based on a corresponding master seed, comparing simulation results of functional simulations against each other executed with said logic circuit for at least two different chosen dynamic clock gating configurations, and reporting an error if said at least two simulation results are not identical.Type: GrantFiled: September 7, 2010Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Christian Habermann, Christian Jacobi, Matthias Pflanz, Hans-Werner Tast, Ralf Winkelmann
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Patent number: 8302042Abstract: A method of designing a circuit is described. In an embodiment, a physical design implementation for the circuit is created using a plurality of entities. These entities are named “genomes”. Each entity includes a portion of a functional description of the circuit that has been synthesized into a gate-level implementation. An entity is selected to facilitate the physical design implementation meeting a plurality of design constraints. Several steps (e.g., beginning with selection of an entity) of this method are repeated several times to meet the design constraints. As a consequence, the physical design implementation provides more accurate information for use in a final physical design implementation. Moreover, the physical design implementation can be created faster than prior techniques while still allowing a global view of the physical design implementation in meeting design constraints.Type: GrantFiled: January 10, 2007Date of Patent: October 30, 2012Assignee: Oasys Design SystemsInventors: Hermanus Arts, Paul van Besouw, Johnson Limqueco
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Patent number: 8302040Abstract: A method and computer program product for modeling a semiconductor transistor device structure having an active device area, a gate structure, and including a conductive line feature connected to the gate structure and disposed above the active device area, the conductive line feature including a conductive landing pad feature disposed near an edge of the active device area in a circuit to be modeled. The method includes determining a distance between an edge defined by the landing pad feature to an edge of the active device area, and, from modeling a lithographic rounding effect of the landing pad feature, determining changes in width of the active device area as a function of the distance between an edge defined by the landing pad feature to an edge of the active device area. From these data, an effective change in active device area width (deltaW adder) is related to the determined distance.Type: GrantFiled: May 4, 2011Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, Gerald M. Davidson, Paul A. Hyde, Judith H. McCullen, Shreesh Narasimha