Abstract: A semiconductor device includes a substrate main body, a plurality of first bump pads, and redistribution layer (RDL). The first bump pads are disposed adjacent to a surface of the substrate main body, each of the first bump pads has a first profile from a top view, the first profile has a first width along a first direction and a second width along a second direction perpendicular to the first direction, and the first width of the first profile is greater than the second width of the first profile. The RDL is disposed adjacent to the surface of the substrate main body, and the RDL includes a first portion disposed between two first bump pads.

Abstract: The semiconductor die includes a base body, protruding portions and bonding pads. The base body has sidewalls. The protruding portions are laterally protruding from the sidewalls respectively. The bonding pads are disposed on the protruding portions respectively. The wafer dicing method includes following operations. Chips are formed on a semiconductor wafer. Bonding pads are formed at a border line between every two of the adjacent chips. A scribe line is formed and disposed along the bonding pads. A photolithographic pattern is formed on a top layer of the semiconductor wafer to expose the scribe line. The scribe line is etched to a depth in the semiconductor wafer substantially below the top layer to form an etched pattern. A back surface of the semiconductor wafer is thinned until the etched pattern in the semiconductor wafer is exposed.

Abstract: A method for is used for forming a semiconductor device. The method includes forming an ILD layer on a substrate and a buffer layer on the ILD layer, wherein at least one contact is formed in the ILD layer; forming an opening through the buffer layer, the ILD layer, and the substrate; forming a liner structure layer over the substrate, wherein an exposed surface of the opening is covered by the liner structure layer; depositing a conductive material over the substrate to fill the opening; performing a polishing process, to polish over the substrate and stop at the buffer layer, wherein the liner structure layer and the conductive material remaining in the opening form a conductive via; performing an etching back process, to remove the buffer layer and expose the ILD layer, wherein a top portion of the conductive via is also exposed and higher than the ILD layer.

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a plurality of fins on the semiconductor substrate; forming a plurality of gate structures on the plurality of fins and sidewall spacers on side surfaces of the gate structures; forming a first dielectric layer on the semiconductor substrate; recessing the gate structures to form a plurality of trenches on top surfaces of the gate structures; forming a mask material layer filling the trenches and on the first dielectric layer; forming a protective layer on the top surfaces of the remaining gate structures and a mask layer on a portion of the first dielectric layer between adjacent gate structures by etching the mask material layer; forming contact through-holes in the first dielectric layer between adjacent gates structure at both sides of the mask layer; and forming a metal contact via in each of the contact through-holes.

Abstract: A first semiconductor substrate layer supports a first transistor including a first source-drain formed by a doped region of the substrate layer. A second semiconductor substrate layer supports a second transistor including a second source-drain formed by a doped region of the substrate layer. The second semiconductor substrate layer is stacked over the first semiconductor substrate layer and separated therefrom by an insulating layer. A metal wiring extends from an electrical contact with the doped region for the first source-drain, through the insulating layer and passing through an electrical isolation structure in the second semiconductor substrate layer to make an electrical contact with the doped region for the second source-drain. The electrical isolation structure is formed by one of a trench isolation or the doped region of the second source-drain itself. The isolation structure has a thickness equal to a thickness of the second semiconductor substrate layer.

Abstract: A mask frame assembly includes a mask having pattern openings and a frame including a first support portion configured to support an end of the mask and having a clamping slot and a support slot adjacent to the clamping slot; and a second support portion connected to the first support portion.

Abstract: A semiconductor device is provided which comprises a metal interconnect structure having a metal alloy capping layer formed within a surface region of the metal interconnect structure, as well as methods for fabricating the semiconductor device. For example, a method comprises forming a metal interconnect structure in a dielectric layer, and applying a surface treatment to a surface of the metal interconnect structure to form a point defect layer in the surface of the metal interconnect structure. A metallic capping layer is then formed on the point defect layer of the metal interconnect structure, and a thermal anneal process is performed to convert the point defect layer into a metal alloy capping layer by infusion of metal atoms of the metallic capping layer into the point defect layer. The resulting metal alloy capping layer comprises an alloy of metallic materials of the metal capping layer and the metal interconnect structure.

Abstract: Techniques are disclosed for forming a through-body-via (TBV) in a semiconductor die. In accordance with some embodiments, a TBV provided using the disclosed techniques includes a polymer-based barrier layer and an electrically conductive seed layer formed by applying an electrically conductive ink directly to the barrier layer and then curing it in situ. In some embodiments, after curing, the resultant seed layer may be a thin, substantially conformal, electrically conductive metal film over which the TBV interconnect metal can be deposited. In some example cases, a polyimide, parylene, benzocyclobutene (BCB), and/or polypropylene carbonate (PPC) barrier layer and an ink containing copper (Cu) and/or silver (Ag), of nanoparticle-based or metal complex-based formulation, may be used in forming the TBV.

Abstract: A method is provided for forming a feature of a target material on a substrate. The method including: forming a feature of a sacrificial material on the substrate; and forming the feature of the target material by a deposition process during which the feature of the sacrificial material is removed from the substrate by forming a volatile reaction product with a precursor of the deposition process, wherein the sacrificial material is replaced by the target material and the target material is selectively deposited on surface portions of the substrate, which portions were covered by the feature of the sacrificial material, to form the feature of the target material.

Abstract: A vibrator includes a base, a lid, and a functional element that is stored in a cavity formed by the base and the lid, in which the lid is provided with a sealing hole that penetrates through the lid and a sealing member that air-tightly seals the sealing hole, and in which the functional element includes a diffusion object shielding portion having a region of an accommodation opening which overlaps at least part of a region of a first opening of the sealing hole on a surface of the lid on the cavity side in a plan view of the functional element and the lid.

Abstract: A composition for the marking of assets comprising: a base material; and two or more encoding compounds wherein each of the two or more encoding compounds are provided at measurable concentrations.

Abstract: A system, method and apparatus for making a semiconductor die includes forming multiple semiconductor devices in a respective portion of a semiconductor wafer. An electrical interconnect structure is formed over the semiconductor devices and provide electrical connections to the semiconductor devices. The electrical interconnect structure including one or more metallization layers. Each of the metallization layers includes conductive lines. At least one portion of at least one of the metallization layers includes a density of the conductive lines that varies as compared to the other portions of the metallization layers. At least one support structure is formed in the electrical interconnect structure. The semiconductor wafer can be a thinned semiconductor wafer.

Abstract: A mask assembly and a thin film deposition method using the same are provided. The mask assembly includes a mask frame including first to fourth sides. The first to fourth sides form a rectangle. Inner sides of the rectangle define a window. The mask frame has a plurality of substrate seating portions provided to project toward the window from at least two corners. The two corners face each other in a diagonal direction. The mask assembly includes four corners positioned where the first to fourth sides of the mask assembly meet each other. A mask includes a plurality of openings for deposition. The plurality of openings are arranged to correspond to the window.

Abstract: Controlling dimensions of nanowires includes lithographically forming a trench in a layer of a polymer resin with a width less than one micrometer where the polymer resin has a thickness less than one micrometer and is deposited over an electrically conductive substrate, depositing a nanowire material within the trench to form a nanowire, and obtaining the nanowire from the trench with a removal mechanism.

Abstract: A method of forming a Ti film on a substrate disposed in a chamber by introducing a processing gas containing a TiCl4 gas as a Ti source and a H2 gas as a reducing gas and by generating plasma in the chamber, includes introducing an Ar gas as a plasma generation gas into the chamber, converting the Ar gas into plasma to generate Ar ions, and acting the Ar ions on the Ti film to promote desorption of Cl from the Ti film.

Abstract: A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a dataset specifying a plurality features to be formed on the workpiece. A first patterning of a hard mask of the workpiece is performed based on a first set of features of the plurality of features, and a first spacer material is deposited on a sidewall of the patterned hard mask. A second patterning is performed based on a second set of features, and a second spacer material is deposited on a sidewall of the first spacer material. A third patterning is performed based on a third set of features. A portion of the workpiece is selectively processed using a pattern defined by a remainder of at least one of the patterned hard mask layer, the first spacer material, or the second spacer material.

Abstract: Metal filling processes for semiconductor devices and methods of fabricating semiconductor devices. One method includes, for instance: obtaining a wafer with at least one contact opening; depositing a metal alloy into at least a portion of the at least one contact opening; separating the metal alloy into a first metal layer and a second metal layer; depositing a barrier stack over the wafer; forming at least one trench opening; forming at least one via opening; and depositing at least one metal material into the trench openings and via openings. An intermediate semiconductor device is also disclosed.

Abstract: A range-pattern-matching-type DRC-based process hotspot detection is provided that considers edge tolerances and incomplete specification (“don't care”) regions in foundry-provided hotspot patterns. First, all possible topological patterns are enumerated for the foundry-provided hotspot pattern. Next, critical topological features are extracted from each pattern topology and converted to critical design rules using Modified Transitive Closure Graphs (MTCGs). Third, the extracted critical design rules are arranged in an order that facilitates searching space reduction techniques, and then the DRC process is sequentially repeated on a user's entire layout pattern for each critical design rule in a first group, then searching space reduction is performed to generate a reduced layout pattern, and then DRC process is performed for all remaining critical design rules using the reduced layout pattern.

Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls.

Abstract: Embodiments of the invention describe a method for controlling etching in pitch doubling. According to one embodiment, the method includes receiving a substrate having a pattern thereon defined by spacers formed on sidewalls of a plurality mandrels, and transferring the pattern defined by the spacers into the substrate using a plasma etch process that etches the mandrels and the substrate, the transferring forming first recessed features in the substrate below the mandrels and second recessed features in the substrate between the mandrels, where the plasma etch process utilizes an etching gas containing O2 gas, and the relative amount of O2 gas in the etching gas is selected to control the depth of the first recessed features relative to the depth of second recessed features. According to another embodiment, the substrate contains a mask layer thereon and a pattern on the mask layer.

Abstract: A method of fabricating a nanowire array is disclosed. The method includes forming a mask layer over a substrate, wherein the mask layer includes a plurality of openings; growing a first plurality of nanowires through the plurality of openings; forming a conformal layer over the first plurality of nanowires and the mask layer; planarizing the conformal layer over the first plurality of nanowires to form a coplanar top surface defined by the first plurality of nanowires and the conformal layer; removing a portion of the conformal layer and a portion of the mask layer to expose the substrate, wherein the portions of the conformal layer and the mask layer are located between adjacent nanowires from the plurality of nanowires; and growing a second plurality of nanowires on the exposed substrate.

Abstract: The electric characteristics of a semiconductor device using an oxide semiconductor are improved. The reliability of a semiconductor device using an oxide semiconductor is improved. The semiconductor device includes an element layer. The element layer includes a first film, a transistor, and a second film. The first film and the second film are partly in contact with each other. The region in which the first film and the second film are in contact with each other has a closed-loop shape when seen from above. The transistor is located between the first film and the second film. The region in which the first film and the second film are in contact with each other is located between a side surface of the element layer and the transistor.

Abstract: A plating apparatus 20 includes a substrate holding device 110 configured to hold a substrate W; a discharging device 21 configured to discharge a plating liquid 35 toward the substrate W held by the substrate holding device 110; and a plating liquid supplying device 30 connected to the discharging device 21 and configured to supply the plating liquid 35 to the discharging device 21. A gas supplying device 170 is configured to heat a heating gas G having a higher specific heat capacity than air and supply the heated heating gas G toward the substrate W held by the substrate holding device 110. Further, a controller 160 is configured to control at least the discharging device 21, the plating liquid supplying device 30, and the gas supplying device 170.

Abstract: A carrier substrate includes a dielectric layer, a first circuit layer, an insulation layer, conductive blocks, and a first conductive structure. The dielectric layer has a first surface, a second surface, and blind vias. The first circuit layer is embedded in the first surface and the blind vias extend from the second surface to the first circuit layer. The insulation layer is disposed on the first surface and has a third surface, a fourth surface, and first openings exposing the first circuit layer. The conductive blocks fill the first openings and connect with the first circuit layer. A top surface of each of the conductive blocks is higher than the third surface of the insulation layer. The first conductive structure includes conductive vias filling the blind vias and a second circuit layer disposed on a portion of the second surface.

Abstract: A semiconductor device includes a substrate having a first and second region, a first structure and a second structure. The first structure is formed over the substrate in the first region. The first structure has a first height. The second structure is formed over the substrate in the second region. The second structure has a second height different from the first height.

Abstract: The present invention provides a method for forming a through-via, including the steps of (1) forming an alloy film as a diffusion-preventive layer that prevents diffusion of copper, in an area on a side wall of a hole formed in a substrate that extends from an entrance of the hole to a central part of the hole, by use of an electroless cobalt plating solution or an electroless nickel plating solution containing at least cobalt ion or nickel ion, a complexing agent, a reductant, and a pH adjusting agent; (2) forming an alloy film as a diffusion-preventive layer in an area on the side wall of the hole formed in the substrate that extends from the central part of the hole to a bottom of the hole, by use of an electroless cobalt plating solution or an electroless nickel plating solution containing at least the cobalt ion or the nickel ion, the complexing agent, the reductant, the pH adjusting agent, and an amino group-containing polymer; and (3) stacking a copper seed layer on the diffusion-preventive layer form

Abstract: A structure includes an electrical interconnection between a first substrate including a plurality of protrusions and a second substrate including a plurality of solder bumps, the plurality of protrusions includes sharp tips that penetrate the plurality of solder bumps, and a permanent electrical interconnection is established by physical contact between the plurality of protrusions and the plurality of solder bumps including a metallurgical joint.

Abstract: A semiconductor device includes: a chip having at least one electrically conductive contact at a first side of the chip; an extension layer extending laterally from one or more sides of the chip; a redistribution layer on a surface of the extension layer and the first side, and coupled to the contact; an interposer having at least one electrically conductive contact at a first surface of the interposer and coupled to the redistribution layer, and at least one electrically conductive contact at a second surface of the interposer opposite to the first surface; a molding material at least partially enclosing the chip and the redistribution layer, and in contact with the interposer. Another semiconductor device includes: an interposer; a redistribution layer over the interposer; a circuit having first and second circuit portions, wherein the redistribution layer includes the first circuit portion, and the interposer includes the second circuit portion.

Abstract: Provided herein are methods of depositing void-free cobalt into features with high aspect ratios. Methods involve (a) partially filling a feature with cobalt, (b) exposing the feature to a plasma generated from nitrogen-containing gas to selectively inhibit cobalt nucleation on surfaces near or at the top of the feature, optionally repeating (a) and (b), and depositing bulk cobalt into the feature by chemical vapor deposition. Methods may also involve exposing a feature including a barrier layer to a plasma generated from nitrogen-containing gas to selectively inhibit cobalt nucleation. The methods may be performed at low temperatures less than about 400° C. using cobalt-containing precursors.

Abstract: A solar cell includes a substrate, an emitter region positioned at a first surface of the substrate, a first electrode positioned on the first surface of the substrate, a back passivation layer positioned on a second surface opposite the first surface of the substrate, and a second electrode which is positioned on the back passivation layer and is electrically connected to the substrate through holes of the back passivation layer. The second electrode includes connection electrodes positioned inside the holes of the back passivation layer and a back electrode layer positioned on the connection electrodes and the back passivation layer. An adhesion enhanced layer is positioned between the back electrode layer and the back passivation layer and contains at least one of intrinsic amorphous silicon and intrinsic microcrystalline silicon.

Abstract: One illustrative method disclosed herein includes, among other things, forming an inverted, generally T-shaped mandrel feature having a base mandrel structure and a substantially vertically oriented fin mandrel structure, the base mandrel structure having a lateral width that is greater than a lateral width of the fin mandrel structure, forming a sidewall spacer adjacent the sidewalls of the base mandrel structure and the fin mandrel structure, performing at least one etching process to remove portions of the inverted, generally T-shaped mandrel feature not covered by a sidewall spacer, wherein, after the etching process is completed, the sidewall spacers and remaining portions of the mandrel feature, collectively, define a fin pattern, and performing at least one additional process operation to form a plurality of fins in the substrate that correspond to the fin pattern.

Abstract: A nanostructure dispersion comprising a mixture of host metallic nanostructures and metallic nanoparticles is provided. The nanostructures and nanoparticles are attracted to each other and remain attracted upon deposition of the mixture onto a substrate to form a transparent conductor. Also provided is a method of fabricating a transparent conductor.

Abstract: An embodiment is a semiconductor device comprising a first gate structure over a semiconductor substrate, a first etch stop layer (ESL) over the semiconductor substrate and the first gate, the first ESL having a curved top surface, and a first inter-layer dielectric (ILD) on the first ESL, the first ILD having a curved top surface. The semiconductor device further comprises a second ESL on the first ILD, the second ESL having a curved top surface, and a second ILD on the second ESL.

Abstract: Disclosed is a film-forming method wherein a manganese-containing film is formed on a substrate having a surface to which an insulating film and a copper wiring line are exposed. The film-forming method includes forming a manganese-containing film on the copper wiring line by a CVD method which uses a manganese compound.

Abstract: A method of forming a semiconductor structure that includes forming a first recess and a second recess between a first pair of sidewall spacers and a second pair of sidewall spacers respectively, the first and second pair of sidewall spacers surrounding a fin on top of a buried dielectric layer, the fin is formed from a top most semiconductor layer of a semiconductor-on-insulator substrate. A high-k dielectric layer is deposited within the first and second recesses and a dummy titanium nitride layer is deposited on the high-k dielectric layer. The high-k dielectric layer and the dummy titanium nitride layer are removed from the second recess and a silicon cap layer is deposited within the first and second recesses. Next, dopants are implanted into the silicon cap layer in the second recess without implanting dopants into the silicon cap layer in the first recess to form a BJT device.

Abstract: A method of forming a semiconductor device package includes bonding a front surface of a first substrate to a second substrate, and thinning a back surface of the first substrate. The method includes depositing and patterning a dielectric layer on the thinned back surface of the first substrate, and etching the first substrate after the depositing and the patterning of the dielectric layer are performed to form a through silicon via to enable electrical connection with a first level metal of the first substrate. The method includes depositing an isolation layer to line the through silicon via is formed, and etching the isolation layer at the bottom of the through silicon via. The method includes depositing a conductive layer to line the through silicon via after the isolation layer at the bottom of the through silicon via is etched, and deposited a copper film over the conductive layer.

Abstract: A semiconductor device has a semiconductor substrate having a first surface and a second surface, a through electrode penetrating through the semiconductor substrate and having a protrusion protruding from the second surface, and an insulation layer on the second surface, which covers the side surface of the protrusion, has an opening through which to expose the end surface of the protrusion, and has a thickness greater than the length of the protrusion.

Abstract: A pressure sensor using the MEMS element and the manufacture method thereof utilize the semiconductor processes to form the micro channel connecting to the chamber, open the micro channel, coat the anti-sticking layer on the inner surface of the chamber, and then seal the micro channel to keep the chamber airtight. Therefore, the manufacture method may essentially simplify the process to coat the anti-sticking layer on the inner surface of the airtight chamber to prevent the sticking and failing of the movable MEMS element.

Abstract: A substrate includes a stacked trace formed from a trace and a first buildup trace stacked on the trace. The first buildup trace contacts and is electrically connected to the trace along the entire length of the trace. The current carrying cross-sectional area of the stacked trace is greater than the current carrying cross-sectional area of the trace. Accordingly, a plurality of the stacked traces can be formed with a small width and thus small pitch yet with a large current carrying cross-sectional area.

Abstract: Integrated circuits with tungsten components having a smooth surface and methods for producing such integrated circuits are provided. A method of producing the integrated circuits includes forming a nucleation layer overlying a substrate and within a cavity, where the nucleation layer includes tungsten. A nucleation layer thickness is reduced, and a fill layer if formed overlying the nucleation layer.

Abstract: Devices and methods for forming semiconductor devices with metal-titanium oxide contacts are provided. One intermediate semiconductor device includes, for instance: a substrate, at least one field-effect transistor disposed on the substrate, a first contact region positioned over at least a first portion of the at least one field-effect transistor between a spacer and an interlayer dielectric, and a second contact region positioned over at least a second portion of the at least one field-effect transistor between a spacer and an interlayer dielectric. One method includes, for instance: obtaining an intermediate semiconductor device and forming at least one contact on the intermediate semiconductor device.

Abstract: Provided are a semiconductor device including a through via plug and a method of manufacturing the same. In the semiconductor device, since a redistributed interconnection pattern is disposed on a protection film of a convex-concave structure having a protrusion and a recessed portion, the semiconductor device may have improved reliability while preventing a leakage current. In the method of manufacturing the semiconductor device, since an end surface of through via structure is exposed by removing a protection film and an insulating film liner using a selective etching process, damage to the through via structure is minimized, thereby preventing copper contamination in a substrate.

Abstract: The present invention provides nanowires and nanoribbons that are well suited for use in thermoelectric applications. The nanowires and nanoribbons are characterized by a periodic compositional longitudinal modulation. The nanowires are constructed using lithographic techniques from thin semiconductor membranes, or “nanomembranes.

Abstract: A method for fabricating a solar cell is disclosed. The method can include forming a dielectric region on a surface of a solar cell structure and forming a first metal layer on the dielectric region. The method can also include forming a second metal layer on the first metal layer and locally heating a particular region of the second metal layer, where heating includes forming a metal bond between the first and second metal layer and forming a contact between the first metal layer and the solar cell structure. The method can include forming an adhesive layer on the first metal layer and forming a second metal layer on the adhesive layer, where the adhesive layer mechanically couples the second metal layer to the first metal layer and allows for an electrical connection between the second metal layer to the first metal layer.

Abstract: A method for fabricating a plurality of conductive lines in an integrated circuit includes providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer, forming a spacer in a layer of the multi-layer structure residing above the layer of conductive metal, wherein the spacer is formed from a metal-containing atomic layer deposition material, and transferring a pattern from the spacer to the layer of conductive metal using a sidewall image transfer technique, wherein the transferring results in a formation of the plurality of conductive lines in the layer of conductive material.

Abstract: A semiconductor device includes at least one ohmic contact region between a semiconductor substrate of the semiconductor device and an electrically conductive structure arranged adjacent to the semiconductor substrate. Further, the semiconductor device includes at least one Schottky contact region between the semiconductor substrate of the semiconductor device and the electrically conductive structure. The at least one ohmic contact region is arranged adjacent to the at least one Schottky contact region. The semiconductor substrate includes a first doping layer arranged adjacent to the electrically conductive structure. An average doping concentration of the surface region of the first doping layer in an area of the at least one ohmic contact region differs from an average doping concentration of the surface region of the first doping layer in an area of the at least one Schottky contact region by less than 10%.

Abstract: An organosilicate polymer is used as mandrel in a two exposure double patterning process. The mandrel layer is formed from the organosilicate polymer and is patterned with a first etching process. Spacers are formed adjacent the mandrel using low temperature process. The spacer material can be a low temperature oxide. The mandrel layer is then further pattered with a second lithographic etching process. A hard mask layer is then printed with a pattern defined by the spacers and the mandrel. The hard mask can be TiN. The process provides a simplified method of double patterning that eliminates the need for a capping layer over the hard mask.

Abstract: A method for fabricating a phase-change memory cell is described. The method includes forming a dielectric layer (228) on a metal layer (226) above a substrate. A phase-change material layer (230) is formed on the dielectric layer. A contact region (232) is formed, within the dielectric layer, between the phase-change material layer and the metal layer by breaking-down a portion of the dielectric layer.

Abstract: A method of an embodiment comprises forming a dielectric layer on a first side of an image sensor substrate, and exposing the dielectric layer to ultraviolet (UV) radiation. The image sensor substrate comprises a photo diode. A structure of an embodiment comprises a substrate and a charge-less dielectric. The substrate comprises a photo diode. The charge-less dielectric layer is on a first side of the substrate, and a total charge of the charge-less dielectric results in an average voltage drop of less than 0.2 V across the charge-less dielectric layer.

Abstract: Methods and apparatus are disclosed which reduce the stress concentration at the redistribution layers (RDLs) of a package device. A package device may comprise a seed layer above a passivation layer, covering an opening of the passivation layer, and covering and in contact with a contact pad. A RDL is formed above the passivation layer, above and in contact with the seed layer, covering the opening of the passivation layer, and electrically connected to the contact pad through the seed layer. The RDL has an end portion with a surface that is smooth without a right angle. The surface of the end portion of the RDL may have an obtuse angle, or a curved surface.