Abstract: A method for manufacturing a compound semiconductor device, the method includes: forming a compound semiconductor laminated structure; removing a part of the compound semiconductor laminated structure, so as to form a concave portion; and cleaning the inside of the concave portion by using a detergent, wherein the detergent contains a base resin compatible with residues present in the concave portion and a solvent.

Abstract: A first electrode, an intrinsic first compound semiconductor layer over the first electrode, a second compound semiconductor layer whose band gap is smaller than that of the first compound semiconductor layer on the first compound semiconductor layer, and a second electrode over the second compound semiconductor layer are provided.

Abstract: Disclosed are a method which improves the performance of a semiconductor element, and a semiconductor element with improved performance. The method for forming a semiconductor element structure includes a heterojunction forming step in which a heterojunction is formed between a strained semiconductor layer (21) in which a strained state is maintained, and relaxed semiconductor layers (23, 25). The heterojunction is formed by performing ion implantation from the surface of a substrate (50) which has a strained semiconductor layer (20) partially covered with a covering layer (30) on an insulating oxide film (40), and altering the strained semiconductor layer (20) where there is no shielding from the covering layer (30) to relaxed semiconductor layers (23, 25) by relaxing the strained state of the strained semiconductor layer (20), while maintaining the strained state of the strained semiconductor layer (21) where there is shielding from the covering layer (30).

Abstract: According to one embodiment, provided are a first photoelectric conversion layer provided for a first wavelength band, a second photoelectric conversion layer provided for a second wavelength band, and a color separation element adapted to separate an incident light into a transmission light including the first wavelength band and a reflection light including the second wavelength band, wherein an angle of incidence of the incident light with respect to a reflection surface of the color separation element is set so that a vertically polarized light and a horizontally polarized light are included in the reflection light.

Abstract: Optoelectronic device including light-emitting means in the form of nanowires (2, 3) having a core/shell-type structure and produced on a substrate (11), in which said nanowires comprise an active zone (22, 32) including at least two types of quantum wells associated with different emission wavelengths and distributed among at least two different regions (220, 221; 320, 321) of said active zone, in which the device also includes a first electrical contact zone (15) on the substrate and a second electrical contact zone (16) on the emitting means, in which said second zone is arranged so that, as the emitting means are distributed according to at least two groups, the electrical contact is achieved for each of said at least two groups at a different region of the active zone, and the electrical power supply is controlled so as to obtain the emission of a multi-wavelength light.

Abstract: Disclosed herein is a semiconducting nanoparticle comprising a one-dimensional semiconducting nanoparticle having a first end and a second end; where the second end is opposed to the first end; and two first endcaps, one of which contacts the first end and the other of which contacts the second end respectively of the one-dimensional semiconducting nanoparticle; where the first endcap that contacts the first end comprises a first semiconductor and where the first endcap extends from the first end of the one-dimensional semiconducting nanoparticle to form a first nanocrystal heterojunction; where the first endcap that contacts the second end comprises a second semiconductor; where the first endcap extends from the second end of the one-dimensional semiconducting nanoparticle to form a second nanocrystal heterojunction; and where the first semiconductor and the second semiconductor are chemically different from each other.

Abstract: Two-terminal electronic devices, such as photodetectors, photovoltaic devices and electroluminescent devices, are provided. The devices include a first electrode residing on a substrate, wherein the first electrode comprises a layer of metal; an I-layer comprising an inorganic insulating or broad band semiconducting material residing on top of the first electrode, and aligned with the first electrode, wherein the inorganic insulating or broad band semiconducting material is a compound of the metal of the first electrode; a semiconductor layer, preferably comprising a p-type semiconductor, residing over the I-layer; and a second electrode residing over the semiconductor layer, the electrode comprising a layer of a conductive material. The band gap of the material of the semiconductor layer, is preferably smaller than the band gap of the I-layer material. The band gap of the material of the I-layer is preferably greater than 2.5 eV.

Abstract: A light emitting diode having a transparent substrate and a method for manufacturing the same. The light emitting diode is formed by creating two semiconductor multilayers and bonding them. The first semiconductor multilayer is formed on a non-transparent substrate. The second semiconductor multilayer is created by forming an amorphous interface layer on a transparent substrate. The two semiconductor multilayers are bonded and the non-transparent substrate is removed, leaving a semiconductor multilayer with a transparent substrate.

Abstract: Bias-switchable dual-band infrared detectors and methods of manufacturing such detectors are provided. The infrared detectors are based on a back-to-back heterojunction diode design, where the detector structure consists of, sequentially, a top contact layer, a unipolar hole barrier layer, an absorber layer, a unipolar electron barrier, a second absorber, a second unipolar hole barrier, and a bottom contact layer. In addition, by substantially reducing the width of one of the absorber layers, a single-band infrared detector can also be formed.

Abstract: Light emitting devices include a light emitting diode (“LED”) and a recipient luminophoric medium that is configured to down-convert at least some of the light emitted by the LED. In some embodiments, the recipient luminophoric medium includes a first broad-spectrum luminescent material and a narrow-spectrum luminescent material. The broad-spectrum luminescent material may down-convert radiation emitted by the LED to radiation having a peak wavelength in the red color range. The narrow-spectrum luminescent material may also down-convert radiation emitted by the LED into the cyan, green or red color range.

Abstract: An optoelectronic semiconductor chip, the latter includes a carrier and a semiconductor layer sequence grown on the carrier. The semiconductor layer sequence is based on a nitride-compound semiconductor material and contains at least one active zone for generating electromagnetic radiation and at least one waveguide layer, which indirectly or directly adjoins the active zone. A waveguide being formed. In addition, the semiconductor layer sequence includes a p-cladding layer adjoining the waveguide layer on a p-doped side and/or an n-cladding layer on an n-doped side of the active zone. The waveguide layer indirectly or directly adjoins the cladding layer. An effective refractive index of a mode guided in the waveguide is in this case greater than a refractive index of the carrier.

Abstract: The disclosure provides for a direct wafer bonding method including providing a bonding layer upon a first and second wafer, and directly bonding the first and second wafers together under heat and pressure. The method may be used for directly bonding an GaAs-based, InP-based, GaP-based, GaSb-based, or Ga(In)N-based device to a GaAs device by introducing a highly doped (Al)(Ga)InP(As)(Sb) layer between the devices. The bonding layer material forms a bond having high bond strength, low electrical resistance, and high optical transmittance.

Abstract: The present invention relates to colloidal quantum dots, to a process for producing such colloidal quantum dots, to the use thereof and to optoelectronic components comprising colloidal quantum dots.

Abstract: The present invention relates to a horizontal biosensor, comprising a reduced graphene oxide layer formed on a substrate; a molecular linker formed on the reduced graphene oxide layer; and a metal nanoparticle layer formed on the molecular linker.

Abstract: Embodiments of a thin-film heterostructure thermoelectric material and methods of fabrication thereof are disclosed. In general, the thermoelectric material is formed in a Group IIa and IV-VI materials system. The thermoelectric material includes an epitaxial heterostructure and exhibits high heat pumping and figure-of-merit performance in terms of Seebeck coefficient, electrical conductivity, and thermal conductivity over broad temperature ranges through appropriate engineering and judicious optimization of the epitaxial heterostructure.

Abstract: Disclosed is a light emitting element, which emits light with small power consumption and high luminance. The light emitting element has: a IV semiconductor substrate; two or more core multi-shell nanowires disposed on the IV semiconductor substrate; a first electrode connected to the IV semiconductor substrate; and a second electrode, which covers the side surfaces of the core multi-shell nanowires, and which is connected to the side surfaces of the core multi-shell nanowires. Each of the core multi-shell nanowires has: a center nanowire composed of a first conductivity type III-V compound semiconductor; a first barrier layer composed of the first conductivity type III-V compound semiconductor; a quantum well layer composed of a III-V compound semiconductor; a second barrier layer composed of a second conductivity type III-V compound semiconductor; and a capping layer composed of a second conductivity type III-V compound semiconductor.

Abstract: A method of controlling ferroelectric characteristics of integrated circuit device components includes forming a ferroelectrically controllable dielectric layer over a substrate; and forming a stress exerting structure proximate the ferroelectrically controllable dielectric layer such that a substantially uniaxial strain is induced in the ferroelectrically controllable dielectric layer by the stress exerting structure; wherein the ferroelectrically controllable dielectric layer comprises one or more of: a ferroelectric oxide layer and a normally non-ferroelectric material layer that does not exhibit ferroelectric properties in the absence of an applied stress.

Abstract: A method is provided for fabricating a nano field-effect vacuum tube. The method includes providing a substrate having an insulating layer and a sacrificial layer; and forming a sacrificial line, a source sacrificial layer and a drain sacrificial layer. The method also includes forming a trench in the insulating layer; and forming a dielectric layer on the surface of the sacrificial line. Further, the method includes forming a metal layer on the dielectric layer to fill up the trench, cover the sacrificial line and expose the source sacrificial layer and the drain sacrificial layer; and removing the source sacrificial layer and the drain sacrificial layer. Further, the method also includes removing the sacrificial line to form a through channel; forming an isolation layer on the metal layer; and forming a source region and a drain region on the insulating layer at both ends of the metal layer.

Abstract: A single-walled carbon nanotube-based planar photodetector includes a substrate; a first electrode and a second electrode disposed on the substrate and spaced apart from each other; a plurality of single-walled carbon nanotubes, each of the plurality of single-walled carbon nanotubes contacting the first electrode and the second electrode; and an adsorbent attached to a surface of at least one of the plurality of single-walled carbon nanotubes, wherein the adsorbent is capable of doping the at least one of the plurality of single-walled carbon nanotubes by photo-excitation.

Abstract: Semiconductor heterojunction structures comprising lattice mismatched, single-crystalline semiconductor materials and methods of fabricating the heterojunction structures are provided. The heterojunction structures comprise at least one three-layer junction comprising two layers of single-crystalline semiconductor and a current tunneling layer sandwiched between and separating the two layers of single-crystalline semiconductor material. Also provided are devices incorporating the heterojunction structures, methods of making the devices and method of using the devices.

Abstract: Various embodiments provide materials and methods for integrating exemplary heterostructure field-effect transistor (HFET) driver circuit or thyristor driver circuit with LED structures to reduce or eliminate resistance and/or inductance associated with their conventional connections.

Abstract: A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate, and forming a quantum well layer on the semiconductor substrate. The method also includes forming a potential energy barrier layer on the semiconductor substrate, and forming an isolation structure to isolate different transistor regions. Further, the method includes patterning the transistor region to form trenches by removing portions of the quantum well layer and the potential energy barrier layer corresponding to a source region and a drain region, and filling trenches with a semiconductor material to form a source and a drain. Further, the method also includes forming a gate structure on a portion of the quantum well layer and the potential energy barrier layer corresponding to a gate region.

Abstract: In a semiconductor device 100, it is possible to prevent C from piling up at a boundary face between an epitaxial layer 22 and a group III nitride semiconductor substrate 10 by the presence of 30×1010 pieces/cm2 to 2000×1010 pieces/cm2 of sulfide in terms of S and 2 at % to 20 at % of oxide in terms of O in a surface layer 12 with a front surface 10a having a specific plane orientation. Accordingly, a high-resistivity layer is prevented from being formed at the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10. Consequently, it is possible to improve the emission intensity of the semiconductor device 100.

Abstract: A method of fabricating a substrate for a semipolar III-nitride device, comprising patterning and forming one or more mesas on a surface of a semipolar III-nitride substrate or epilayer, thereby forming a patterned surface of the semipolar III-nitride substrate or epilayer including each of the mesas with a dimension l along a direction of a threading dislocation glide, wherein the threading dislocation glide results from a III-nitride layer deposited heteroepitaxially and coherently on a non-patterned surface of the substrate or epilayer.

Abstract: Quantum dot (QD) gate FETs and the use of quantum dot (QD) gate FETs for the purpose of sensing analytes and proteins is disclosed and described. Analytes, proteins, miRNAs, and DNAs functionalized to the QDs change the charge density in the gate and hence the current-voltage characteristics. In one embodiment, QD-FETs, such as 3-state configurations, the binding of chemical and biological species change the drain current-gate voltage characteristics resulting in detection. In one embodiment, DNA sensing is done by its binding to an existing reference DNA functionalized on to quantum dots which are located in the gate region of the FET.

Abstract: A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided.

Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).

Abstract: A floating body memory cell, memory circuit, and method for fabricating floating body memory cells. The floating body memory cell includes a bi-layer heterojunction having a first semiconductor coupled to a second semiconductor. The first semiconductor and the second semiconductor have different energy band gaps. The floating body memory cell includes a buried insulator layer. The floating body memory cell includes a back transistor gate separated from the second semiconductor of the bi-layer heterojunction by at least the buried insulated layer. The floating body memory cell also includes a front transistor gate coupled to the first semiconductor of the bi-layer heterojunction.

Abstract: A semiconductor device includes: a first semiconductor layer; a second semiconductor layer; a two-dimensional carrier gas layer; a source electrode; a drain electrode; a gate electrode; and an auxiliary electrode located above the two-dimensional carrier gas layer between the gate electrode and the drain electrode. Channel resistance of the two-dimensional carrier gas layer between the gate electrode and the auxiliary electrode is set higher than channel resistance of the two-dimensional carrier gas layer between the gate electrode and the source electrode.

Abstract: Lateral epitaxial overgrowth of non-polar III-nitride seed layers reduces threading dislocations in the non-polar III-nitride thin films. First, a thin patterned dielectric mask is applied to the seed layer. Second, a selective epitaxial regrowth is performed to achieve a lateral overgrowth based on the patterned mask. Upon regrowth, the non-polar III-nitride films initially grow vertically through openings in the dielectric mask before laterally overgrowing the mask in directions perpendicular to the vertical growth direction. Threading dislocations are reduced in the overgrown regions by (1) the mask blocking the propagation of dislocations vertically into the growing film and (2) the bending of dislocations through the transition from vertical to lateral growth.

Abstract: A simple method that makes it possible to manufacture a highly-workable organic solar cell module having a plurality of connected organic solar cells is provided. The method includes: a first electrode substrate forming step of forming a plurality of first electrode layers on a first substrate to form a first electrode substrate; preparing a single piece of second electrode substrate-forming base material having at least a second electrode layer and capable of being cut into a plurality of second electrode substrates; a functional layer forming step; a cutting step to form a plurality of second electrode substrates; a bonding step so that the first and second electrode substrates are bonded together; and a connecting step of electrically connecting the first electrode layer of one of the organic solar cells to the second electrode layer of another organic solar cell which is adjacent to the one organic solar cell.

Abstract: A method of forming a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, the trench including a plurality of sidewalls and a bottom wall. The method includes depositing a first conductive material within the trench proximate to one of the sidewalls and depositing a second conductive material within the trench. The method further includes depositing a material to form a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a magnetic field with a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a magnetic field with a configurable magnetic orientation. The method further includes selectively removing a portion of the MTJ structure to create an opening in the MTJ structure.

Abstract: An embodiment includes a heterojunction tunneling field effect transistor including a source, a channel, and a drain; wherein (a) the channel includes a major axis, corresponding to channel length, and a minor axis that corresponds to channel width and is orthogonal to the major axis; (b) the channel length is less than 10 nm long; (c) the source is doped with a first polarity and has a first conduction band; (d) the drain is doped with a second polarity, which is opposite the first polarity, and the drain has a second conduction band with higher energy than the first conduction band. Other embodiments are described herein.

Abstract: A layer in which the potential level difference normally unrequired for device operation is generated is positively inserted in a device structure. The potential level difference has such a function that even if a semiconductor having a small bandgap is exposed on a mesa side surface, a potential drop amount of the portion is suppressed, and a leakage current inconvenient for device operation can be reduced. This effect can be commonly obtained for a heterostructure bipolar transistor, a photodiode, an electroabsorption modulator, and so on. In the photodiode, since the leakage current is alleviated, the device size can be reduced, so that in addition to improvement of operating speed with a reduction in series resistance, it is advantageous that the device can be densely disposed in an array.

Abstract: The carbon nanotube-based electronic and photonic devices are disclosed. The devices are united by the same technology as well as similar elements for their fabrication. The devices consist of the vertically grown semiconductor nanotube having two Schottky barriers at the nanotube ends and one Schottky barrier at the middle of the nanotube. Depending on the Schottky barrier heights and bias arrangements, the disclosed devices can operate either as transistors, CNT MESFET and CNT Hot Electron Transistor, or as a CNT Photon Emitter.

Abstract: III-N semiconductor-on-silicon integrated circuit structures and techniques are disclosed. In some cases, the structure includes a first semiconductor layer formed on a nucleation layer, the first semiconductor layer including a 3-D GaN layer on the nucleation layer and having a plurality of 3-D semiconductor structures, and a 2-D GaN layer on the 3-D GaN layer. The structure also may include a second semiconductor layer formed on or within the first semiconductor layer, wherein the second semiconductor layer includes AlGaN on the 2-D GaN layer and a GaN layer on the AlGaN layer. Another structure includes a first semiconductor layer formed on a nucleation layer, the first semiconductor layer comprising a 2-D GaN layer on the nucleation layer, and a second semiconductor layer formed on or within the first semiconductor layer, wherein the second semiconductor layer includes AlGaN on the 2-D GaN layer and a GaN layer on the AlGaN layer.

Abstract: An AlGaN/GaN-HEMT has a structure including: compound semiconductor layers formed on a substrate; a gate electrode, a gate pad that has a current path formed between the gate electrode and itself, and a semiconductor layer that is spontaneously polarized and piezoelectrically polarized, which are formed on the compound semiconductor layer; and a gate electrode connection layer formed on the semiconductor layer, wherein the gate electrode connection layer and the gate electrode are electrically connected with each other. This structure which is relatively simple allows the AlGaN/GaN-HEMT to realize an intended normally-off operation without causing such inconveniences as increase in a sheet resistance, increase in an on-resistance, and increase in a leakage current.

Abstract: To provide an epitaxial substrate for electronic devices, in which current flows in a lateral direction, which enables accurate measurement of the sheet resistance of HEMTs without contact, and to provide a method of efficiently producing the epitaxial substrate for electronic devices, the method characteristically includes the steps of forming a barrier layer against impurity diffusion on one surface of a high-resistance Si-single crystal substrate, forming a buffer as an insulating layer on the other surface of the high-resistance Si-single crystal substrate, producing an epitaxial substrate by epitaxially growing a plurality of III-nitride layers on the buffer to form a main laminate, and measuring resistance of the main laminate of the epitaxial substrate without contact.

Abstract: A graphene-based composite structure is disclosed. The graphene-based composite structure includes a graphene layer, a transition metal layer, and a substrate. The graphene layer, transition metal layer, and substrate are stacked together in series to form a sandwich structure. The graphene layer and the transition metal layer are coupled by d-p orbitals hybridization. The transition metal layer and the substrate are also coupled by d-p orbitals hybridization. A method for making graphene-based composite structure is also disclosed.

Abstract: A semiconductor device includes a silicon substrate, an aluminum nitride layer which is arranged on the silicon substrate and has a region where silicon is doped thereof as an impurity, a buffer layer which is arranged on the aluminum nitride layer and has a structure where a plurality of nitride semiconductor films are laminated, and a semiconductor functional layer which is arranged on the buffer layer and made of nitride semiconductor.

Abstract: A light emitting device and method for making the same is disclosed. The light-emitting device includes an active layer sandwiched between a p-type semiconductor layer and an n-type semiconductor layer. The active layer emits light when holes from the p-type semiconductor layer combine with electrons from the n-type semiconductor layer therein. The active layer includes a number of sub-layers and has a plurality of pits in which the side surfaces of a plurality of the sub-layers are in contact with the p-type semiconductor material such that holes from the p-type semiconductor material are injected into those sub-layers through the exposed side surfaces without passing through another sub-layer. The pits can be formed by utilizing dislocations in the n-type semiconductor layer and etching the active layer using an etching atmosphere in the same chamber used to deposit the semiconductor layers without removing the partially fabricated device.

Abstract: The present invention is directed to a novel synthetic method for producing nanoscale heterostructures, and particularly nanoscale heterostructure particles, rods and sheets, that comprise a metal core and a monocrystalline semiconductor shell with substantial lattice mismatches between them. More specifically, the invention concerns the use of controlled soft acid-base coordination reactions between molecular complexes and colloidal nanostructures to drive the nanoscale monocrystalline growth of the semiconductor shell with a lattice structure incommensurate with that of the core. The invention also relates to more complex hybrid core-shell structures that exhibit azimuthal and radial nano-tailoring of structures. The invention is additionally directed to the use of such compositions in semiconductor devices.

Abstract: Non-planar semiconductor devices having channel regions with low band-gap cladding layers are described. For example, a semiconductor device includes a vertical arrangement of a plurality of nanowires disposed above a substrate. Each nanowire includes an inner region having a first band gap and an outer cladding layer surrounding the inner region. The cladding layer has a second, lower band gap. A gate stack is disposed on and completely surrounds the channel region of each of the nanowires. The gate stack includes a gate dielectric layer disposed on and surrounding the cladding layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the channel regions of the nanowires.

Abstract: A method of forming a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, the trench including a first sidewall, a second sidewall, a third sidewall, a fourth sidewall, and a bottom wall. The method includes depositing a first conductive material within the trench proximate to the first sidewall and depositing a second conductive material within the trench. The method further includes depositing a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a magnetic field with a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a magnetic field with a configurable magnetic orientation. The method further includes selectively removing a portion of the MTJ structure that is adjacent to the fourth sidewall to create an opening such that the MTJ structure is substantially u-shaped.

Abstract: A nitride semiconductor device is provided, in which a superlattice strain buffer layer using AlGaN layers having a low Al content or GaN layers is formed with good flatness, and a nitride semiconductor layer with good flatness and crystallinity is formed on the superlattice strain buffer layer. A nitride semiconductor device includes a substrate; an AlN strain buffer layer made of AlN formed on the substrate; a superlattice strain buffer layer formed on the AlN strain buffer layer; and a nitride semiconductor layer formed on the superlattice strain buffer layer, and is characterized in that the superlattice strain buffer layer has a superlattice structure formed by alternately stacking first layers made of AlxGa1-xN (0?x?0.25), which further contain p-type impurity, and second layers made of AlN.

Abstract: An optoelectric device including microwires or nanowires on a support, each microwire or nanowire including at least one portion mainly containing a III-V compound in contact with the support, wherein the III-V compound is based on a first group-V element and on a second group-III element, wherein a surface of the support includes first areas of a first material promoting the growth of the III-V compound according to the polarity of the first element distributed in a second area of a second material promoting the growth of the compound according to the polarity of the second element, the microwires or nanowires being located on the first areas.

Abstract: A light emitting diode (LED) and a method for fabricating the same, capable of improving brightness by forming a InGaN layer having a low concentration of indium, and whose lattice constant is similar to that of an active layer of the LED, is provided. The LED includes: a buffer layer disposed on a sapphire substrate; a GaN layer disposed on the buffer layer; a doped GaN layer disposed on the GaN layer; a GaN layer having indium disposed on the GaN layer; an active layer disposed on the GaN layer having indium; and a P-type GaN disposed on the active layer. Here, an empirical formula of the GaN layer having indium is given by In(x)Ga(1?x)N and a range of x is given by 0<x<2, and a thickness of the GaN layer having indium is 50-200 ?.

Abstract: Various embodiments provide non-planar nanowires, nanowire arrays, and nanowire networks as well as methods of their formation and applications. The non-planar nanowires and their arrays can be formed in a controlled manner on surfaces having a non-planar orientation. In embodiments, two or more adjacent nanowires from different surfaces can grow to merge together forming one or more nanowire branches and thus forming a nanowire network. In embodiments, the non-planar nanowires and nanowire networks can be used for cantilever oscillation, switching and transistor actions.

Abstract: The present invention discloses a semiconductor device, comprising: a substrate, a gate stack structure on the substrate, source and drain regions in the substrate on both sides of the gate stack structure, and a channel region between the source and drain regions in the substrate, characterized in that the source region in the source and drain regions comprises GeSn alloy, and a tunnel dielectric layer is optionally comprised between the GeSn alloy of the source region and the channel region. In accordance with the semiconductor device and method for manufacturing the same of the present invention, GeSn alloy having a narrow band gap is formed by implanting precursors and performing a laser rapid annealing, the on-state current of TFET is effectively enhanced, accordingly it has an important application prospect in a high performance low power consumption application.

Abstract: A compound semiconductor device includes: a substrate; a first compound semiconductor layer formed over the substrate; a second compound semiconductor layer formed over the first compound semiconductor layer; and an upper electrode formed over the first compound semiconductor layer, wherein two-dimensional hole gas is generated in a region of the first compound semiconductor layer, the region being located at an interface between the first compound semiconductor layer and the second compound semiconductor layer, so as to have a hole concentration that decreases with increasing distance from the upper electrode.